./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test3-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test3-2.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2f1036b64b29bd922a31935b87e7c90d1acbba8f8044f40e2525bb03d5de1e7f --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 16:47:18,026 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 16:47:18,084 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-04 16:47:18,088 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 16:47:18,089 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 16:47:18,089 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 16:47:18,105 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 16:47:18,106 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 16:47:18,106 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 16:47:18,106 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 16:47:18,106 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 16:47:18,106 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 16:47:18,106 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 16:47:18,106 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 16:47:18,106 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 16:47:18,107 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 16:47:18,107 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 16:47:18,108 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 16:47:18,108 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 16:47:18,108 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 16:47:18,108 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 16:47:18,108 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 16:47:18,109 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-04 16:47:18,109 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 16:47:18,109 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-04 16:47:18,109 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 16:47:18,109 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 16:47:18,109 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 16:47:18,109 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 16:47:18,109 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 16:47:18,110 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-04 16:47:18,110 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 16:47:18,110 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 16:47:18,110 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 16:47:18,110 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 16:47:18,110 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 16:47:18,110 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 16:47:18,110 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 16:47:18,110 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 16:47:18,111 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 16:47:18,111 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2f1036b64b29bd922a31935b87e7c90d1acbba8f8044f40e2525bb03d5de1e7f [2025-03-04 16:47:18,385 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 16:47:18,392 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 16:47:18,393 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 16:47:18,394 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 16:47:18,394 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 16:47:18,397 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test3-2.i [2025-03-04 16:47:19,490 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fc660dcf0/0e2ec62b4dc646c883e9a74067ccb35f/FLAG5c78430ed [2025-03-04 16:47:19,769 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 16:47:19,770 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test3-2.i [2025-03-04 16:47:19,788 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fc660dcf0/0e2ec62b4dc646c883e9a74067ccb35f/FLAG5c78430ed [2025-03-04 16:47:20,053 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fc660dcf0/0e2ec62b4dc646c883e9a74067ccb35f [2025-03-04 16:47:20,055 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 16:47:20,056 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 16:47:20,056 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 16:47:20,057 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 16:47:20,059 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 16:47:20,060 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,060 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1bdba412 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20, skipping insertion in model container [2025-03-04 16:47:20,060 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,094 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 16:47:20,385 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:47:20,396 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 16:47:20,478 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:47:20,503 INFO L204 MainTranslator]: Completed translation [2025-03-04 16:47:20,504 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20 WrapperNode [2025-03-04 16:47:20,504 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 16:47:20,504 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 16:47:20,504 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 16:47:20,504 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 16:47:20,508 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,523 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,581 INFO L138 Inliner]: procedures = 177, calls = 330, calls flagged for inlining = 10, calls inlined = 14, statements flattened = 1601 [2025-03-04 16:47:20,581 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 16:47:20,582 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 16:47:20,583 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 16:47:20,583 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 16:47:20,589 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,589 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,604 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,687 INFO L175 MemorySlicer]: Split 303 memory accesses to 3 slices as follows [2, 267, 34]. 88 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0, 0]. The 62 writes are split as follows [0, 58, 4]. [2025-03-04 16:47:20,687 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,687 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,718 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,724 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,727 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,729 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,737 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 16:47:20,741 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 16:47:20,741 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 16:47:20,741 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 16:47:20,741 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20" (1/1) ... [2025-03-04 16:47:20,746 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:47:20,755 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:47:20,767 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:47:20,769 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 16:47:20,785 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-03-04 16:47:20,785 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-03-04 16:47:20,785 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2025-03-04 16:47:20,785 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#0 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#1 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#2 [2025-03-04 16:47:20,786 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#0 [2025-03-04 16:47:20,786 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#1 [2025-03-04 16:47:20,786 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#2 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#0 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#1 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#2 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#0 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#1 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#2 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-03-04 16:47:20,786 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#2 [2025-03-04 16:47:20,787 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 16:47:20,787 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 16:47:20,964 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 16:47:20,966 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 16:47:22,074 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L733: call ULTIMATE.dealloc(main_~#i~0#1.base, main_~#i~0#1.offset);havoc main_~#i~0#1.base, main_~#i~0#1.offset; [2025-03-04 16:47:22,155 INFO L? ?]: Removed 368 outVars from TransFormulas that were not future-live. [2025-03-04 16:47:22,155 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 16:47:22,208 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 16:47:22,209 INFO L336 CfgBuilder]: Removed 1 assume(true) statements. [2025-03-04 16:47:22,210 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:47:22 BoogieIcfgContainer [2025-03-04 16:47:22,210 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 16:47:22,211 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 16:47:22,211 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 16:47:22,215 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 16:47:22,215 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:47:22,215 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 04:47:20" (1/3) ... [2025-03-04 16:47:22,216 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@61d95018 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:47:22, skipping insertion in model container [2025-03-04 16:47:22,216 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:47:22,216 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:47:20" (2/3) ... [2025-03-04 16:47:22,217 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@61d95018 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:47:22, skipping insertion in model container [2025-03-04 16:47:22,217 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:47:22,217 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:47:22" (3/3) ... [2025-03-04 16:47:22,218 INFO L363 chiAutomizerObserver]: Analyzing ICFG uthash_SAX_test3-2.i [2025-03-04 16:47:22,265 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 16:47:22,265 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 16:47:22,265 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 16:47:22,265 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 16:47:22,265 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 16:47:22,265 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 16:47:22,265 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 16:47:22,265 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 16:47:22,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 448 states, 443 states have (on average 1.6162528216704288) internal successors, (716), 443 states have internal predecessors, (716), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:22,305 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 435 [2025-03-04 16:47:22,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:22,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:22,311 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:22,312 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-03-04 16:47:22,312 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 16:47:22,313 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 448 states, 443 states have (on average 1.6162528216704288) internal successors, (716), 443 states have internal predecessors, (716), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:22,329 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 435 [2025-03-04 16:47:22,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:22,330 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:22,330 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:22,330 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-03-04 16:47:22,334 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:22,335 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false;" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume !true;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:22,338 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:22,338 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 1 times [2025-03-04 16:47:22,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:22,344 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964369864] [2025-03-04 16:47:22,344 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:22,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:22,409 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:22,424 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:22,424 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:22,424 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:22,424 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:22,431 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:22,435 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:22,437 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:22,437 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:22,464 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:22,467 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:22,467 INFO L85 PathProgramCache]: Analyzing trace with hash -1630813254, now seen corresponding path program 1 times [2025-03-04 16:47:22,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:22,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1810977860] [2025-03-04 16:47:22,468 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:22,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:22,480 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-04 16:47:22,485 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-04 16:47:22,486 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:22,486 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:22,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:22,519 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:22,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1810977860] [2025-03-04 16:47:22,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1810977860] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:22,520 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:22,520 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:47:22,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010347058] [2025-03-04 16:47:22,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:22,523 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:22,524 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:22,542 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-04 16:47:22,542 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-04 16:47:22,545 INFO L87 Difference]: Start difference. First operand has 448 states, 443 states have (on average 1.6162528216704288) internal successors, (716), 443 states have internal predecessors, (716), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 3.0) internal successors, (6), 2 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:22,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:22,626 INFO L93 Difference]: Finished difference Result 442 states and 634 transitions. [2025-03-04 16:47:22,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 442 states and 634 transitions. [2025-03-04 16:47:22,633 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 423 [2025-03-04 16:47:22,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 442 states to 433 states and 625 transitions. [2025-03-04 16:47:22,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 433 [2025-03-04 16:47:22,644 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 433 [2025-03-04 16:47:22,645 INFO L73 IsDeterministic]: Start isDeterministic. Operand 433 states and 625 transitions. [2025-03-04 16:47:22,648 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:22,649 INFO L218 hiAutomatonCegarLoop]: Abstraction has 433 states and 625 transitions. [2025-03-04 16:47:22,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 433 states and 625 transitions. [2025-03-04 16:47:22,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 433 to 433. [2025-03-04 16:47:22,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 433 states, 429 states have (on average 1.442890442890443) internal successors, (619), 428 states have internal predecessors, (619), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:22,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 625 transitions. [2025-03-04 16:47:22,679 INFO L240 hiAutomatonCegarLoop]: Abstraction has 433 states and 625 transitions. [2025-03-04 16:47:22,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-04 16:47:22,685 INFO L432 stractBuchiCegarLoop]: Abstraction has 433 states and 625 transitions. [2025-03-04 16:47:22,685 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 16:47:22,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 433 states and 625 transitions. [2025-03-04 16:47:22,687 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 423 [2025-03-04 16:47:22,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:22,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:22,688 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:22,688 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:22,688 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:22,689 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem32#1 := read~int#1(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem32#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem33#1 := read~int#1(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem33#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem34#1 := read~int#1(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem34#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:22,690 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:22,690 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 2 times [2025-03-04 16:47:22,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:22,690 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [541713133] [2025-03-04 16:47:22,690 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:47:22,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:22,703 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:22,712 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:22,712 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:47:22,712 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:22,712 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:22,720 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:22,728 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:22,729 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:22,730 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:22,736 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:22,737 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:22,737 INFO L85 PathProgramCache]: Analyzing trace with hash -11240698, now seen corresponding path program 1 times [2025-03-04 16:47:22,737 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:22,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927855949] [2025-03-04 16:47:22,737 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:22,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:22,779 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes. [2025-03-04 16:47:22,797 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements. [2025-03-04 16:47:22,801 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:22,801 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:23,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:23,093 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:23,093 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927855949] [2025-03-04 16:47:23,094 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1927855949] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:23,094 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:23,094 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:47:23,094 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [689882685] [2025-03-04 16:47:23,094 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:23,094 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:23,094 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:23,095 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:47:23,095 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:47:23,095 INFO L87 Difference]: Start difference. First operand 433 states and 625 transitions. cyclomatic complexity: 197 Second operand has 4 states, 4 states have (on average 18.5) internal successors, (74), 4 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:23,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:23,263 INFO L93 Difference]: Finished difference Result 436 states and 621 transitions. [2025-03-04 16:47:23,263 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 436 states and 621 transitions. [2025-03-04 16:47:23,267 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 426 [2025-03-04 16:47:23,270 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 436 states to 436 states and 621 transitions. [2025-03-04 16:47:23,270 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 436 [2025-03-04 16:47:23,271 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 436 [2025-03-04 16:47:23,271 INFO L73 IsDeterministic]: Start isDeterministic. Operand 436 states and 621 transitions. [2025-03-04 16:47:23,275 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:23,275 INFO L218 hiAutomatonCegarLoop]: Abstraction has 436 states and 621 transitions. [2025-03-04 16:47:23,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 436 states and 621 transitions. [2025-03-04 16:47:23,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 436 to 433. [2025-03-04 16:47:23,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 433 states, 429 states have (on average 1.4265734265734267) internal successors, (612), 428 states have internal predecessors, (612), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:23,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 618 transitions. [2025-03-04 16:47:23,291 INFO L240 hiAutomatonCegarLoop]: Abstraction has 433 states and 618 transitions. [2025-03-04 16:47:23,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:47:23,292 INFO L432 stractBuchiCegarLoop]: Abstraction has 433 states and 618 transitions. [2025-03-04 16:47:23,292 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 16:47:23,292 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 433 states and 618 transitions. [2025-03-04 16:47:23,293 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 423 [2025-03-04 16:47:23,294 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:23,294 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:23,294 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:23,294 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:23,295 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:23,295 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:23,295 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:23,296 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 3 times [2025-03-04 16:47:23,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:23,296 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597090578] [2025-03-04 16:47:23,296 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:47:23,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:23,304 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:23,308 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:23,308 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:47:23,308 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:23,308 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:23,314 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:23,316 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:23,316 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:23,316 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:23,324 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:23,325 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:23,325 INFO L85 PathProgramCache]: Analyzing trace with hash 913882765, now seen corresponding path program 1 times [2025-03-04 16:47:23,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:23,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200450656] [2025-03-04 16:47:23,325 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:23,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:23,389 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes. [2025-03-04 16:47:23,555 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements. [2025-03-04 16:47:23,555 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:23,556 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:23,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:23,961 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:23,961 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1200450656] [2025-03-04 16:47:23,961 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1200450656] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:23,962 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:23,962 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-04 16:47:23,962 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1696746917] [2025-03-04 16:47:23,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:23,962 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:23,962 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:23,963 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-04 16:47:23,963 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-04 16:47:23,963 INFO L87 Difference]: Start difference. First operand 433 states and 618 transitions. cyclomatic complexity: 190 Second operand has 6 states, 6 states have (on average 12.333333333333334) internal successors, (74), 6 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:24,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:24,591 INFO L93 Difference]: Finished difference Result 467 states and 661 transitions. [2025-03-04 16:47:24,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 467 states and 661 transitions. [2025-03-04 16:47:24,594 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 457 [2025-03-04 16:47:24,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 467 states to 467 states and 661 transitions. [2025-03-04 16:47:24,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 467 [2025-03-04 16:47:24,597 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 467 [2025-03-04 16:47:24,597 INFO L73 IsDeterministic]: Start isDeterministic. Operand 467 states and 661 transitions. [2025-03-04 16:47:24,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:24,600 INFO L218 hiAutomatonCegarLoop]: Abstraction has 467 states and 661 transitions. [2025-03-04 16:47:24,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 467 states and 661 transitions. [2025-03-04 16:47:24,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 467 to 462. [2025-03-04 16:47:24,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 462 states, 458 states have (on average 1.4148471615720524) internal successors, (648), 457 states have internal predecessors, (648), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:24,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 462 states to 462 states and 654 transitions. [2025-03-04 16:47:24,614 INFO L240 hiAutomatonCegarLoop]: Abstraction has 462 states and 654 transitions. [2025-03-04 16:47:24,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-04 16:47:24,615 INFO L432 stractBuchiCegarLoop]: Abstraction has 462 states and 654 transitions. [2025-03-04 16:47:24,616 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 16:47:24,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 462 states and 654 transitions. [2025-03-04 16:47:24,617 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 452 [2025-03-04 16:47:24,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:24,617 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:24,619 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:24,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:24,621 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:24,621 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:24,621 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:24,621 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 4 times [2025-03-04 16:47:24,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:24,621 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399278684] [2025-03-04 16:47:24,621 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:47:24,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:24,628 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 16:47:24,634 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:24,634 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 16:47:24,634 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:24,634 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:24,637 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:24,638 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:24,638 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:24,638 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:24,641 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:24,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:24,642 INFO L85 PathProgramCache]: Analyzing trace with hash -1098993694, now seen corresponding path program 1 times [2025-03-04 16:47:24,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:24,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2038620891] [2025-03-04 16:47:24,642 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:24,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:24,693 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-04 16:47:24,760 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-04 16:47:24,760 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:24,760 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:24,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:24,997 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:24,997 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2038620891] [2025-03-04 16:47:24,998 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2038620891] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:24,998 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:24,999 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:47:24,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953609552] [2025-03-04 16:47:24,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:24,999 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:24,999 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:24,999 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:47:24,999 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:47:25,000 INFO L87 Difference]: Start difference. First operand 462 states and 654 transitions. cyclomatic complexity: 197 Second operand has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:25,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:25,259 INFO L93 Difference]: Finished difference Result 471 states and 667 transitions. [2025-03-04 16:47:25,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 471 states and 667 transitions. [2025-03-04 16:47:25,261 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 461 [2025-03-04 16:47:25,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 471 states to 471 states and 667 transitions. [2025-03-04 16:47:25,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 471 [2025-03-04 16:47:25,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 471 [2025-03-04 16:47:25,265 INFO L73 IsDeterministic]: Start isDeterministic. Operand 471 states and 667 transitions. [2025-03-04 16:47:25,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:25,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 471 states and 667 transitions. [2025-03-04 16:47:25,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471 states and 667 transitions. [2025-03-04 16:47:25,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471 to 463. [2025-03-04 16:47:25,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 463 states, 459 states have (on average 1.4139433551198257) internal successors, (649), 458 states have internal predecessors, (649), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:25,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 655 transitions. [2025-03-04 16:47:25,274 INFO L240 hiAutomatonCegarLoop]: Abstraction has 463 states and 655 transitions. [2025-03-04 16:47:25,274 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:47:25,274 INFO L432 stractBuchiCegarLoop]: Abstraction has 463 states and 655 transitions. [2025-03-04 16:47:25,275 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 16:47:25,275 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 463 states and 655 transitions. [2025-03-04 16:47:25,276 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 453 [2025-03-04 16:47:25,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:25,277 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:25,278 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:25,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:25,278 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:25,279 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:25,279 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:25,279 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 5 times [2025-03-04 16:47:25,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:25,280 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511033638] [2025-03-04 16:47:25,280 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 16:47:25,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:25,287 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:25,289 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:25,289 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:47:25,289 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:25,289 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:25,292 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:25,293 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:25,293 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:25,293 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:25,298 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:25,298 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:25,298 INFO L85 PathProgramCache]: Analyzing trace with hash 543445499, now seen corresponding path program 1 times [2025-03-04 16:47:25,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:25,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101262690] [2025-03-04 16:47:25,299 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:25,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:25,322 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-04 16:47:25,341 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-04 16:47:25,341 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:25,341 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:25,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:25,554 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:25,554 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1101262690] [2025-03-04 16:47:25,554 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1101262690] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:25,554 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:25,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-04 16:47:25,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [729475438] [2025-03-04 16:47:25,554 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:25,554 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:25,555 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:25,555 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-04 16:47:25,555 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-04 16:47:25,555 INFO L87 Difference]: Start difference. First operand 463 states and 655 transitions. cyclomatic complexity: 197 Second operand has 7 states, 7 states have (on average 10.714285714285714) internal successors, (75), 7 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:26,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:26,127 INFO L93 Difference]: Finished difference Result 475 states and 672 transitions. [2025-03-04 16:47:26,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 475 states and 672 transitions. [2025-03-04 16:47:26,129 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 465 [2025-03-04 16:47:26,132 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 475 states to 475 states and 672 transitions. [2025-03-04 16:47:26,133 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 475 [2025-03-04 16:47:26,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 475 [2025-03-04 16:47:26,134 INFO L73 IsDeterministic]: Start isDeterministic. Operand 475 states and 672 transitions. [2025-03-04 16:47:26,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:26,135 INFO L218 hiAutomatonCegarLoop]: Abstraction has 475 states and 672 transitions. [2025-03-04 16:47:26,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 475 states and 672 transitions. [2025-03-04 16:47:26,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 475 to 472. [2025-03-04 16:47:26,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 472 states, 468 states have (on average 1.4145299145299146) internal successors, (662), 467 states have internal predecessors, (662), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:26,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 668 transitions. [2025-03-04 16:47:26,141 INFO L240 hiAutomatonCegarLoop]: Abstraction has 472 states and 668 transitions. [2025-03-04 16:47:26,142 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-04 16:47:26,142 INFO L432 stractBuchiCegarLoop]: Abstraction has 472 states and 668 transitions. [2025-03-04 16:47:26,143 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 16:47:26,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 472 states and 668 transitions. [2025-03-04 16:47:26,144 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 462 [2025-03-04 16:47:26,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:26,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:26,145 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:26,145 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:26,145 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:26,146 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:26,147 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:26,147 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 6 times [2025-03-04 16:47:26,147 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:26,147 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1993939377] [2025-03-04 16:47:26,147 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 16:47:26,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:26,154 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:26,156 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:26,157 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 16:47:26,157 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:26,157 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:26,159 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:26,162 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:26,162 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:26,162 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:26,167 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:26,168 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:26,170 INFO L85 PathProgramCache]: Analyzing trace with hash -355172186, now seen corresponding path program 1 times [2025-03-04 16:47:26,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:26,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1975092069] [2025-03-04 16:47:26,170 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:26,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:26,198 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-04 16:47:26,219 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-04 16:47:26,219 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:26,219 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:26,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:26,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:26,535 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1975092069] [2025-03-04 16:47:26,535 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1975092069] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:26,535 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:26,535 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-04 16:47:26,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1974995773] [2025-03-04 16:47:26,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:26,536 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:26,536 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:26,536 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-04 16:47:26,536 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-04 16:47:26,536 INFO L87 Difference]: Start difference. First operand 472 states and 668 transitions. cyclomatic complexity: 201 Second operand has 9 states, 9 states have (on average 8.444444444444445) internal successors, (76), 9 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:27,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:27,358 INFO L93 Difference]: Finished difference Result 486 states and 686 transitions. [2025-03-04 16:47:27,359 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 486 states and 686 transitions. [2025-03-04 16:47:27,361 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 476 [2025-03-04 16:47:27,363 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 486 states to 486 states and 686 transitions. [2025-03-04 16:47:27,363 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 486 [2025-03-04 16:47:27,364 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 486 [2025-03-04 16:47:27,364 INFO L73 IsDeterministic]: Start isDeterministic. Operand 486 states and 686 transitions. [2025-03-04 16:47:27,364 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:27,365 INFO L218 hiAutomatonCegarLoop]: Abstraction has 486 states and 686 transitions. [2025-03-04 16:47:27,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 486 states and 686 transitions. [2025-03-04 16:47:27,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 486 to 480. [2025-03-04 16:47:27,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 480 states, 476 states have (on average 1.411764705882353) internal successors, (672), 475 states have internal predecessors, (672), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:27,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 678 transitions. [2025-03-04 16:47:27,371 INFO L240 hiAutomatonCegarLoop]: Abstraction has 480 states and 678 transitions. [2025-03-04 16:47:27,372 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-04 16:47:27,373 INFO L432 stractBuchiCegarLoop]: Abstraction has 480 states and 678 transitions. [2025-03-04 16:47:27,374 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-04 16:47:27,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 678 transitions. [2025-03-04 16:47:27,375 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 470 [2025-03-04 16:47:27,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:27,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:27,376 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:27,376 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:27,376 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:27,376 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:27,376 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:27,376 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 7 times [2025-03-04 16:47:27,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:27,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1194962164] [2025-03-04 16:47:27,377 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 16:47:27,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:27,382 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:27,384 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:27,384 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:27,384 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:27,384 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:27,387 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:27,391 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:27,391 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:27,391 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:27,395 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:27,396 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:27,396 INFO L85 PathProgramCache]: Analyzing trace with hash -991834742, now seen corresponding path program 1 times [2025-03-04 16:47:27,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:27,397 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77137449] [2025-03-04 16:47:27,397 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:27,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:27,420 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-04 16:47:27,434 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-04 16:47:27,435 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:27,435 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:27,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:27,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:27,582 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77137449] [2025-03-04 16:47:27,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [77137449] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:27,582 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:27,582 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-04 16:47:27,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1624129363] [2025-03-04 16:47:27,582 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:27,582 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:27,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:27,583 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-04 16:47:27,583 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-03-04 16:47:27,583 INFO L87 Difference]: Start difference. First operand 480 states and 678 transitions. cyclomatic complexity: 203 Second operand has 6 states, 6 states have (on average 12.666666666666666) internal successors, (76), 6 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:27,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:27,997 INFO L93 Difference]: Finished difference Result 483 states and 681 transitions. [2025-03-04 16:47:27,997 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 483 states and 681 transitions. [2025-03-04 16:47:28,003 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 473 [2025-03-04 16:47:28,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 483 states to 483 states and 681 transitions. [2025-03-04 16:47:28,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 483 [2025-03-04 16:47:28,005 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 483 [2025-03-04 16:47:28,005 INFO L73 IsDeterministic]: Start isDeterministic. Operand 483 states and 681 transitions. [2025-03-04 16:47:28,006 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:28,006 INFO L218 hiAutomatonCegarLoop]: Abstraction has 483 states and 681 transitions. [2025-03-04 16:47:28,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 483 states and 681 transitions. [2025-03-04 16:47:28,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 483 to 483. [2025-03-04 16:47:28,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 483 states, 479 states have (on average 1.4091858037578289) internal successors, (675), 478 states have internal predecessors, (675), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:28,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 483 states to 483 states and 681 transitions. [2025-03-04 16:47:28,012 INFO L240 hiAutomatonCegarLoop]: Abstraction has 483 states and 681 transitions. [2025-03-04 16:47:28,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-04 16:47:28,017 INFO L432 stractBuchiCegarLoop]: Abstraction has 483 states and 681 transitions. [2025-03-04 16:47:28,017 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-04 16:47:28,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 483 states and 681 transitions. [2025-03-04 16:47:28,018 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 473 [2025-03-04 16:47:28,018 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:28,018 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:28,018 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:28,018 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:28,018 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:28,019 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:28,019 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:28,019 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 8 times [2025-03-04 16:47:28,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:28,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380327760] [2025-03-04 16:47:28,019 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:47:28,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:28,025 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:28,026 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:28,026 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:47:28,026 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:28,026 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:28,028 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:28,029 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:28,029 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:28,029 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:28,033 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:28,033 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:28,033 INFO L85 PathProgramCache]: Analyzing trace with hash 1651284044, now seen corresponding path program 1 times [2025-03-04 16:47:28,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:28,033 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453762466] [2025-03-04 16:47:28,033 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:28,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:28,078 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-04 16:47:28,262 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-04 16:47:28,262 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:28,263 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:28,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:28,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:28,737 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1453762466] [2025-03-04 16:47:28,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1453762466] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:28,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:28,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-04 16:47:28,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [170011721] [2025-03-04 16:47:28,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:28,738 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:28,738 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:28,738 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-04 16:47:28,738 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-04 16:47:28,738 INFO L87 Difference]: Start difference. First operand 483 states and 681 transitions. cyclomatic complexity: 203 Second operand has 13 states, 13 states have (on average 5.923076923076923) internal successors, (77), 13 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:30,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:30,333 INFO L93 Difference]: Finished difference Result 581 states and 821 transitions. [2025-03-04 16:47:30,333 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 581 states and 821 transitions. [2025-03-04 16:47:30,336 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 571 [2025-03-04 16:47:30,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 581 states to 581 states and 821 transitions. [2025-03-04 16:47:30,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 581 [2025-03-04 16:47:30,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 581 [2025-03-04 16:47:30,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 581 states and 821 transitions. [2025-03-04 16:47:30,339 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:30,339 INFO L218 hiAutomatonCegarLoop]: Abstraction has 581 states and 821 transitions. [2025-03-04 16:47:30,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 581 states and 821 transitions. [2025-03-04 16:47:30,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 581 to 489. [2025-03-04 16:47:30,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 489 states, 485 states have (on average 1.4082474226804125) internal successors, (683), 484 states have internal predecessors, (683), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:30,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 489 states to 489 states and 689 transitions. [2025-03-04 16:47:30,346 INFO L240 hiAutomatonCegarLoop]: Abstraction has 489 states and 689 transitions. [2025-03-04 16:47:30,346 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-04 16:47:30,347 INFO L432 stractBuchiCegarLoop]: Abstraction has 489 states and 689 transitions. [2025-03-04 16:47:30,347 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-04 16:47:30,347 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 489 states and 689 transitions. [2025-03-04 16:47:30,348 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 479 [2025-03-04 16:47:30,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:30,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:30,348 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:30,349 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:30,349 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:30,349 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:30,349 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:30,349 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 9 times [2025-03-04 16:47:30,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:30,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1282557763] [2025-03-04 16:47:30,349 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:47:30,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:30,356 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:30,358 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:30,358 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:47:30,358 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:30,358 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:30,361 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:30,362 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:30,363 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:30,363 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:30,368 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:30,368 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:30,368 INFO L85 PathProgramCache]: Analyzing trace with hash -134165989, now seen corresponding path program 1 times [2025-03-04 16:47:30,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:30,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893410878] [2025-03-04 16:47:30,368 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:30,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:30,393 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-04 16:47:30,455 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-04 16:47:30,455 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:30,456 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:30,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:30,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:30,639 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893410878] [2025-03-04 16:47:30,639 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1893410878] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:30,639 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:30,639 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-04 16:47:30,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1549730170] [2025-03-04 16:47:30,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:30,640 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:30,640 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:30,640 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-04 16:47:30,640 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-04 16:47:30,640 INFO L87 Difference]: Start difference. First operand 489 states and 689 transitions. cyclomatic complexity: 205 Second operand has 7 states, 7 states have (on average 11.0) internal successors, (77), 7 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:31,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:31,218 INFO L93 Difference]: Finished difference Result 496 states and 698 transitions. [2025-03-04 16:47:31,218 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 496 states and 698 transitions. [2025-03-04 16:47:31,219 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 486 [2025-03-04 16:47:31,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 496 states to 496 states and 698 transitions. [2025-03-04 16:47:31,221 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 496 [2025-03-04 16:47:31,222 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 496 [2025-03-04 16:47:31,222 INFO L73 IsDeterministic]: Start isDeterministic. Operand 496 states and 698 transitions. [2025-03-04 16:47:31,223 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:31,223 INFO L218 hiAutomatonCegarLoop]: Abstraction has 496 states and 698 transitions. [2025-03-04 16:47:31,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states and 698 transitions. [2025-03-04 16:47:31,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 489. [2025-03-04 16:47:31,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 489 states, 485 states have (on average 1.4082474226804125) internal successors, (683), 484 states have internal predecessors, (683), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:31,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 489 states to 489 states and 689 transitions. [2025-03-04 16:47:31,229 INFO L240 hiAutomatonCegarLoop]: Abstraction has 489 states and 689 transitions. [2025-03-04 16:47:31,229 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-04 16:47:31,230 INFO L432 stractBuchiCegarLoop]: Abstraction has 489 states and 689 transitions. [2025-03-04 16:47:31,230 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-04 16:47:31,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 489 states and 689 transitions. [2025-03-04 16:47:31,231 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 479 [2025-03-04 16:47:31,231 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:31,231 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:31,231 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:31,232 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:31,232 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:31,232 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:31,232 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:31,232 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 10 times [2025-03-04 16:47:31,232 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:31,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288775171] [2025-03-04 16:47:31,233 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:47:31,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:31,238 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 16:47:31,239 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:31,240 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 16:47:31,240 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:31,240 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:31,242 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:31,243 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:31,243 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:31,243 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:31,247 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:31,247 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:31,247 INFO L85 PathProgramCache]: Analyzing trace with hash 443876327, now seen corresponding path program 1 times [2025-03-04 16:47:31,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:31,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741469640] [2025-03-04 16:47:31,248 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:31,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:31,270 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-04 16:47:31,331 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-04 16:47:31,331 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:31,331 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:31,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:31,727 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:31,727 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741469640] [2025-03-04 16:47:31,727 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [741469640] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:31,728 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:31,728 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-04 16:47:31,728 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274953351] [2025-03-04 16:47:31,728 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:31,728 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:31,728 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:31,728 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-04 16:47:31,728 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-04 16:47:31,729 INFO L87 Difference]: Start difference. First operand 489 states and 689 transitions. cyclomatic complexity: 205 Second operand has 13 states, 13 states have (on average 6.0) internal successors, (78), 13 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:33,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:33,211 INFO L93 Difference]: Finished difference Result 583 states and 823 transitions. [2025-03-04 16:47:33,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 583 states and 823 transitions. [2025-03-04 16:47:33,213 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 573 [2025-03-04 16:47:33,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 583 states to 583 states and 823 transitions. [2025-03-04 16:47:33,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 583 [2025-03-04 16:47:33,217 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 583 [2025-03-04 16:47:33,217 INFO L73 IsDeterministic]: Start isDeterministic. Operand 583 states and 823 transitions. [2025-03-04 16:47:33,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:33,218 INFO L218 hiAutomatonCegarLoop]: Abstraction has 583 states and 823 transitions. [2025-03-04 16:47:33,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 583 states and 823 transitions. [2025-03-04 16:47:33,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 583 to 490. [2025-03-04 16:47:33,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 490 states, 486 states have (on average 1.4094650205761317) internal successors, (685), 485 states have internal predecessors, (685), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:33,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 490 states to 490 states and 691 transitions. [2025-03-04 16:47:33,225 INFO L240 hiAutomatonCegarLoop]: Abstraction has 490 states and 691 transitions. [2025-03-04 16:47:33,225 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-04 16:47:33,226 INFO L432 stractBuchiCegarLoop]: Abstraction has 490 states and 691 transitions. [2025-03-04 16:47:33,226 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-04 16:47:33,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 490 states and 691 transitions. [2025-03-04 16:47:33,227 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 480 [2025-03-04 16:47:33,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:33,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:33,228 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:33,228 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:33,228 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:33,228 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:33,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:33,228 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 11 times [2025-03-04 16:47:33,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:33,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195939201] [2025-03-04 16:47:33,228 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 16:47:33,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:33,234 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:33,235 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:33,235 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:47:33,236 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:33,236 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:33,237 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:33,238 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:33,238 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:33,238 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:33,242 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:33,242 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:33,243 INFO L85 PathProgramCache]: Analyzing trace with hash 113708166, now seen corresponding path program 1 times [2025-03-04 16:47:33,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:33,243 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1434871130] [2025-03-04 16:47:33,243 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:33,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:33,265 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-04 16:47:33,334 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-04 16:47:33,334 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:33,334 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:33,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:33,540 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:33,540 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1434871130] [2025-03-04 16:47:33,540 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1434871130] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:33,540 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:33,540 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-04 16:47:33,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982481510] [2025-03-04 16:47:33,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:33,540 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:33,540 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:33,540 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-04 16:47:33,540 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-04 16:47:33,541 INFO L87 Difference]: Start difference. First operand 490 states and 691 transitions. cyclomatic complexity: 206 Second operand has 9 states, 9 states have (on average 8.666666666666666) internal successors, (78), 9 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:34,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:34,296 INFO L93 Difference]: Finished difference Result 510 states and 717 transitions. [2025-03-04 16:47:34,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 510 states and 717 transitions. [2025-03-04 16:47:34,298 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 500 [2025-03-04 16:47:34,300 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 510 states to 510 states and 717 transitions. [2025-03-04 16:47:34,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 510 [2025-03-04 16:47:34,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 510 [2025-03-04 16:47:34,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 510 states and 717 transitions. [2025-03-04 16:47:34,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:34,301 INFO L218 hiAutomatonCegarLoop]: Abstraction has 510 states and 717 transitions. [2025-03-04 16:47:34,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 510 states and 717 transitions. [2025-03-04 16:47:34,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 510 to 493. [2025-03-04 16:47:34,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 493 states, 489 states have (on average 1.408997955010225) internal successors, (689), 488 states have internal predecessors, (689), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:34,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 493 states to 493 states and 695 transitions. [2025-03-04 16:47:34,306 INFO L240 hiAutomatonCegarLoop]: Abstraction has 493 states and 695 transitions. [2025-03-04 16:47:34,307 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 16:47:34,307 INFO L432 stractBuchiCegarLoop]: Abstraction has 493 states and 695 transitions. [2025-03-04 16:47:34,307 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-04 16:47:34,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 493 states and 695 transitions. [2025-03-04 16:47:34,308 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 483 [2025-03-04 16:47:34,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:34,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:34,309 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:34,309 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:34,309 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:34,309 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:34,310 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:34,310 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 12 times [2025-03-04 16:47:34,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:34,310 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298619972] [2025-03-04 16:47:34,310 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 16:47:34,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:34,317 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:34,318 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:34,318 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 16:47:34,318 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:34,318 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:34,320 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:34,321 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:34,321 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:34,321 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:34,326 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:34,326 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:34,326 INFO L85 PathProgramCache]: Analyzing trace with hash -2093628317, now seen corresponding path program 1 times [2025-03-04 16:47:34,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:34,326 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [731222918] [2025-03-04 16:47:34,326 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:34,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:34,349 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-04 16:47:34,361 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-04 16:47:34,362 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:34,362 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:34,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:34,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:34,528 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [731222918] [2025-03-04 16:47:34,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [731222918] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:34,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:34,529 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-04 16:47:34,530 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [186167859] [2025-03-04 16:47:34,530 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:34,530 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:34,530 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:34,530 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-04 16:47:34,530 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2025-03-04 16:47:34,531 INFO L87 Difference]: Start difference. First operand 493 states and 695 transitions. cyclomatic complexity: 207 Second operand has 9 states, 9 states have (on average 8.666666666666666) internal successors, (78), 9 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:35,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:35,159 INFO L93 Difference]: Finished difference Result 506 states and 711 transitions. [2025-03-04 16:47:35,159 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 506 states and 711 transitions. [2025-03-04 16:47:35,161 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 496 [2025-03-04 16:47:35,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 506 states to 506 states and 711 transitions. [2025-03-04 16:47:35,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 506 [2025-03-04 16:47:35,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 506 [2025-03-04 16:47:35,163 INFO L73 IsDeterministic]: Start isDeterministic. Operand 506 states and 711 transitions. [2025-03-04 16:47:35,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:35,164 INFO L218 hiAutomatonCegarLoop]: Abstraction has 506 states and 711 transitions. [2025-03-04 16:47:35,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 506 states and 711 transitions. [2025-03-04 16:47:35,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 506 to 493. [2025-03-04 16:47:35,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 493 states, 489 states have (on average 1.408997955010225) internal successors, (689), 488 states have internal predecessors, (689), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:35,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 493 states to 493 states and 695 transitions. [2025-03-04 16:47:35,171 INFO L240 hiAutomatonCegarLoop]: Abstraction has 493 states and 695 transitions. [2025-03-04 16:47:35,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-04 16:47:35,174 INFO L432 stractBuchiCegarLoop]: Abstraction has 493 states and 695 transitions. [2025-03-04 16:47:35,174 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-04 16:47:35,174 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 493 states and 695 transitions. [2025-03-04 16:47:35,176 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 483 [2025-03-04 16:47:35,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:35,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:35,176 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:35,176 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:35,177 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:35,177 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 32 % 4294967296;main_#t~bitwise48#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:35,177 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:35,178 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 13 times [2025-03-04 16:47:35,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:35,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [484243255] [2025-03-04 16:47:35,178 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 16:47:35,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:35,186 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:35,188 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:35,188 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:35,188 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:35,188 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:35,190 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:35,191 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:35,191 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:35,191 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:35,197 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:35,198 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:35,198 INFO L85 PathProgramCache]: Analyzing trace with hash 2124861184, now seen corresponding path program 1 times [2025-03-04 16:47:35,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:35,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202381356] [2025-03-04 16:47:35,198 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:35,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:35,231 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-04 16:47:35,389 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-04 16:47:35,390 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:35,390 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:35,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:35,967 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:35,967 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202381356] [2025-03-04 16:47:35,967 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [202381356] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:35,967 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:35,967 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-04 16:47:35,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674307761] [2025-03-04 16:47:35,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:35,967 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:35,967 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:35,968 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-04 16:47:35,968 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2025-03-04 16:47:35,968 INFO L87 Difference]: Start difference. First operand 493 states and 695 transitions. cyclomatic complexity: 207 Second operand has 9 states, 9 states have (on average 8.666666666666666) internal successors, (78), 9 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:36,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:36,504 INFO L93 Difference]: Finished difference Result 488 states and 686 transitions. [2025-03-04 16:47:36,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 488 states and 686 transitions. [2025-03-04 16:47:36,506 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 478 [2025-03-04 16:47:36,508 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 488 states to 488 states and 686 transitions. [2025-03-04 16:47:36,508 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 488 [2025-03-04 16:47:36,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 488 [2025-03-04 16:47:36,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 488 states and 686 transitions. [2025-03-04 16:47:36,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:36,509 INFO L218 hiAutomatonCegarLoop]: Abstraction has 488 states and 686 transitions. [2025-03-04 16:47:36,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 488 states and 686 transitions. [2025-03-04 16:47:36,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 488 to 483. [2025-03-04 16:47:36,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 483 states, 479 states have (on average 1.407098121085595) internal successors, (674), 478 states have internal predecessors, (674), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:36,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 483 states to 483 states and 680 transitions. [2025-03-04 16:47:36,514 INFO L240 hiAutomatonCegarLoop]: Abstraction has 483 states and 680 transitions. [2025-03-04 16:47:36,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-04 16:47:36,516 INFO L432 stractBuchiCegarLoop]: Abstraction has 483 states and 680 transitions. [2025-03-04 16:47:36,516 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-04 16:47:36,516 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 483 states and 680 transitions. [2025-03-04 16:47:36,518 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 473 [2025-03-04 16:47:36,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:36,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:36,518 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:36,518 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:36,518 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:36,518 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise46#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:36,519 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:36,519 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 14 times [2025-03-04 16:47:36,519 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:36,519 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961025276] [2025-03-04 16:47:36,519 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:47:36,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:36,525 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:36,527 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:36,527 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:47:36,527 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:36,527 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:36,529 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:36,530 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:36,530 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:36,530 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:36,534 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:36,535 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:36,535 INFO L85 PathProgramCache]: Analyzing trace with hash 1630450693, now seen corresponding path program 1 times [2025-03-04 16:47:36,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:36,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694257171] [2025-03-04 16:47:36,536 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:36,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:36,557 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-04 16:47:36,610 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-04 16:47:36,611 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:36,611 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:36,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:36,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:36,972 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1694257171] [2025-03-04 16:47:36,972 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1694257171] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:36,972 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:36,972 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2025-03-04 16:47:36,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832513958] [2025-03-04 16:47:36,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:36,973 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:36,973 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:36,973 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2025-03-04 16:47:36,973 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2025-03-04 16:47:36,973 INFO L87 Difference]: Start difference. First operand 483 states and 680 transitions. cyclomatic complexity: 202 Second operand has 12 states, 12 states have (on average 6.583333333333333) internal successors, (79), 12 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:38,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:38,174 INFO L93 Difference]: Finished difference Result 537 states and 756 transitions. [2025-03-04 16:47:38,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 537 states and 756 transitions. [2025-03-04 16:47:38,176 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 527 [2025-03-04 16:47:38,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 537 states to 537 states and 756 transitions. [2025-03-04 16:47:38,178 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 537 [2025-03-04 16:47:38,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 537 [2025-03-04 16:47:38,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 537 states and 756 transitions. [2025-03-04 16:47:38,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:38,179 INFO L218 hiAutomatonCegarLoop]: Abstraction has 537 states and 756 transitions. [2025-03-04 16:47:38,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 537 states and 756 transitions. [2025-03-04 16:47:38,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 537 to 493. [2025-03-04 16:47:38,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 493 states, 489 states have (on average 1.4049079754601228) internal successors, (687), 488 states have internal predecessors, (687), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:38,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 493 states to 493 states and 693 transitions. [2025-03-04 16:47:38,185 INFO L240 hiAutomatonCegarLoop]: Abstraction has 493 states and 693 transitions. [2025-03-04 16:47:38,185 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-04 16:47:38,186 INFO L432 stractBuchiCegarLoop]: Abstraction has 493 states and 693 transitions. [2025-03-04 16:47:38,186 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-04 16:47:38,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 493 states and 693 transitions. [2025-03-04 16:47:38,187 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 483 [2025-03-04 16:47:38,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:38,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:38,188 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:38,188 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:38,188 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:38,188 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise46#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:38,188 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:38,188 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 15 times [2025-03-04 16:47:38,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:38,188 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583986971] [2025-03-04 16:47:38,189 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:47:38,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:38,195 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:38,196 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:38,196 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:47:38,196 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:38,196 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:38,198 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:38,199 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:38,199 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:38,199 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:38,203 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:38,203 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:38,203 INFO L85 PathProgramCache]: Analyzing trace with hash -203034153, now seen corresponding path program 1 times [2025-03-04 16:47:38,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:38,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514416436] [2025-03-04 16:47:38,204 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:38,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:38,227 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-04 16:47:38,239 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-04 16:47:38,239 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:38,239 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:38,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:38,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:38,456 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [514416436] [2025-03-04 16:47:38,456 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [514416436] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:38,457 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:38,457 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-04 16:47:38,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [553241065] [2025-03-04 16:47:38,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:38,457 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:38,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:38,458 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-04 16:47:38,458 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2025-03-04 16:47:38,458 INFO L87 Difference]: Start difference. First operand 493 states and 693 transitions. cyclomatic complexity: 205 Second operand has 10 states, 10 states have (on average 7.9) internal successors, (79), 10 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:39,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:39,066 INFO L93 Difference]: Finished difference Result 509 states and 714 transitions. [2025-03-04 16:47:39,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 509 states and 714 transitions. [2025-03-04 16:47:39,068 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 499 [2025-03-04 16:47:39,070 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 509 states to 509 states and 714 transitions. [2025-03-04 16:47:39,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 509 [2025-03-04 16:47:39,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 509 [2025-03-04 16:47:39,070 INFO L73 IsDeterministic]: Start isDeterministic. Operand 509 states and 714 transitions. [2025-03-04 16:47:39,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:39,072 INFO L218 hiAutomatonCegarLoop]: Abstraction has 509 states and 714 transitions. [2025-03-04 16:47:39,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 509 states and 714 transitions. [2025-03-04 16:47:39,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 509 to 503. [2025-03-04 16:47:39,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 503 states, 499 states have (on average 1.4008016032064128) internal successors, (699), 498 states have internal predecessors, (699), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:39,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 503 states to 503 states and 705 transitions. [2025-03-04 16:47:39,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 503 states and 705 transitions. [2025-03-04 16:47:39,080 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 16:47:39,080 INFO L432 stractBuchiCegarLoop]: Abstraction has 503 states and 705 transitions. [2025-03-04 16:47:39,080 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-04 16:47:39,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 503 states and 705 transitions. [2025-03-04 16:47:39,081 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 493 [2025-03-04 16:47:39,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:39,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:39,082 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:39,082 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:39,082 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:39,082 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:39,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:39,083 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 16 times [2025-03-04 16:47:39,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:39,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2042358803] [2025-03-04 16:47:39,083 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:47:39,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:39,090 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 16:47:39,091 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:39,091 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 16:47:39,091 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:39,091 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:39,093 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:39,095 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:39,095 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:39,095 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:39,100 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:39,101 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:39,101 INFO L85 PathProgramCache]: Analyzing trace with hash 1787289780, now seen corresponding path program 1 times [2025-03-04 16:47:39,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:39,101 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294349363] [2025-03-04 16:47:39,101 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:39,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:39,121 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-04 16:47:39,160 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-04 16:47:39,161 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:39,161 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:39,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:39,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:39,320 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294349363] [2025-03-04 16:47:39,320 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294349363] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:39,320 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:39,320 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-04 16:47:39,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494202535] [2025-03-04 16:47:39,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:39,320 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:39,320 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:39,321 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-04 16:47:39,321 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-04 16:47:39,321 INFO L87 Difference]: Start difference. First operand 503 states and 705 transitions. cyclomatic complexity: 207 Second operand has 7 states, 7 states have (on average 11.285714285714286) internal successors, (79), 7 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:39,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:39,852 INFO L93 Difference]: Finished difference Result 508 states and 710 transitions. [2025-03-04 16:47:39,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 508 states and 710 transitions. [2025-03-04 16:47:39,854 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 498 [2025-03-04 16:47:39,855 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 508 states to 508 states and 710 transitions. [2025-03-04 16:47:39,855 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 508 [2025-03-04 16:47:39,856 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 508 [2025-03-04 16:47:39,856 INFO L73 IsDeterministic]: Start isDeterministic. Operand 508 states and 710 transitions. [2025-03-04 16:47:39,856 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:39,856 INFO L218 hiAutomatonCegarLoop]: Abstraction has 508 states and 710 transitions. [2025-03-04 16:47:39,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 508 states and 710 transitions. [2025-03-04 16:47:39,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 508 to 503. [2025-03-04 16:47:39,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 503 states, 499 states have (on average 1.3987975951903808) internal successors, (698), 498 states have internal predecessors, (698), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:39,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 503 states to 503 states and 704 transitions. [2025-03-04 16:47:39,861 INFO L240 hiAutomatonCegarLoop]: Abstraction has 503 states and 704 transitions. [2025-03-04 16:47:39,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-04 16:47:39,862 INFO L432 stractBuchiCegarLoop]: Abstraction has 503 states and 704 transitions. [2025-03-04 16:47:39,862 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-04 16:47:39,862 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 503 states and 704 transitions. [2025-03-04 16:47:39,863 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 493 [2025-03-04 16:47:39,864 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:39,864 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:39,864 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:39,864 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:39,864 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:39,865 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise46#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:39,865 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:39,865 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 17 times [2025-03-04 16:47:39,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:39,865 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15189569] [2025-03-04 16:47:39,865 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 16:47:39,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:39,871 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:39,872 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:39,872 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:47:39,872 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:39,872 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:39,874 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:39,874 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:39,874 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:39,874 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:39,878 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:39,879 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:39,879 INFO L85 PathProgramCache]: Analyzing trace with hash -495079916, now seen corresponding path program 1 times [2025-03-04 16:47:39,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:39,879 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342602105] [2025-03-04 16:47:39,879 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:39,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:39,902 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-04 16:47:39,927 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-04 16:47:39,927 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:39,927 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:40,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:40,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:40,172 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [342602105] [2025-03-04 16:47:40,172 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [342602105] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:40,172 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:40,172 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-04 16:47:40,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2035616160] [2025-03-04 16:47:40,173 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:40,173 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:40,173 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:40,173 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-04 16:47:40,174 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2025-03-04 16:47:40,174 INFO L87 Difference]: Start difference. First operand 503 states and 704 transitions. cyclomatic complexity: 206 Second operand has 10 states, 10 states have (on average 7.9) internal successors, (79), 10 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:40,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:40,920 INFO L93 Difference]: Finished difference Result 518 states and 725 transitions. [2025-03-04 16:47:40,920 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 725 transitions. [2025-03-04 16:47:40,921 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 508 [2025-03-04 16:47:40,922 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 725 transitions. [2025-03-04 16:47:40,922 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2025-03-04 16:47:40,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2025-03-04 16:47:40,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 725 transitions. [2025-03-04 16:47:40,923 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:40,923 INFO L218 hiAutomatonCegarLoop]: Abstraction has 518 states and 725 transitions. [2025-03-04 16:47:40,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 725 transitions. [2025-03-04 16:47:40,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 503. [2025-03-04 16:47:40,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 503 states, 499 states have (on average 1.3987975951903808) internal successors, (698), 498 states have internal predecessors, (698), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:40,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 503 states to 503 states and 704 transitions. [2025-03-04 16:47:40,928 INFO L240 hiAutomatonCegarLoop]: Abstraction has 503 states and 704 transitions. [2025-03-04 16:47:40,930 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 16:47:40,930 INFO L432 stractBuchiCegarLoop]: Abstraction has 503 states and 704 transitions. [2025-03-04 16:47:40,930 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-04 16:47:40,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 503 states and 704 transitions. [2025-03-04 16:47:40,931 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 493 [2025-03-04 16:47:40,931 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:40,931 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:40,931 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:40,931 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:40,932 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:40,932 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:40,932 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:40,932 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 18 times [2025-03-04 16:47:40,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:40,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405088108] [2025-03-04 16:47:40,932 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 16:47:40,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:40,937 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:40,938 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:40,938 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 16:47:40,938 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:40,939 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:40,940 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:40,941 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:40,941 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:40,941 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:40,945 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:40,945 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:40,945 INFO L85 PathProgramCache]: Analyzing trace with hash 813753336, now seen corresponding path program 1 times [2025-03-04 16:47:40,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:40,945 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2110054073] [2025-03-04 16:47:40,945 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:40,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:40,967 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-04 16:47:40,999 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-04 16:47:40,999 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:40,999 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:41,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:41,130 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:41,130 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2110054073] [2025-03-04 16:47:41,130 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2110054073] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:41,130 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:41,130 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-04 16:47:41,130 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50723645] [2025-03-04 16:47:41,130 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:41,131 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:41,131 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:41,132 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-04 16:47:41,132 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-04 16:47:41,132 INFO L87 Difference]: Start difference. First operand 503 states and 704 transitions. cyclomatic complexity: 206 Second operand has 7 states, 7 states have (on average 11.285714285714286) internal successors, (79), 7 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:41,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:41,676 INFO L93 Difference]: Finished difference Result 508 states and 710 transitions. [2025-03-04 16:47:41,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 508 states and 710 transitions. [2025-03-04 16:47:41,677 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 498 [2025-03-04 16:47:41,678 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 508 states to 508 states and 710 transitions. [2025-03-04 16:47:41,678 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 508 [2025-03-04 16:47:41,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 508 [2025-03-04 16:47:41,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 508 states and 710 transitions. [2025-03-04 16:47:41,679 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:41,679 INFO L218 hiAutomatonCegarLoop]: Abstraction has 508 states and 710 transitions. [2025-03-04 16:47:41,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 508 states and 710 transitions. [2025-03-04 16:47:41,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 508 to 507. [2025-03-04 16:47:41,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 507 states, 503 states have (on average 1.3976143141153081) internal successors, (703), 502 states have internal predecessors, (703), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:41,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 507 states to 507 states and 709 transitions. [2025-03-04 16:47:41,684 INFO L240 hiAutomatonCegarLoop]: Abstraction has 507 states and 709 transitions. [2025-03-04 16:47:41,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-04 16:47:41,684 INFO L432 stractBuchiCegarLoop]: Abstraction has 507 states and 709 transitions. [2025-03-04 16:47:41,684 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-04 16:47:41,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 507 states and 709 transitions. [2025-03-04 16:47:41,685 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 497 [2025-03-04 16:47:41,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:41,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:41,686 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:41,686 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:41,686 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:41,686 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise46#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:41,687 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:41,687 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 19 times [2025-03-04 16:47:41,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:41,687 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1674214457] [2025-03-04 16:47:41,687 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 16:47:41,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:41,692 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:41,693 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:41,693 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:41,693 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:41,693 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:41,695 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:41,695 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:41,695 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:41,696 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:41,700 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:41,700 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:41,700 INFO L85 PathProgramCache]: Analyzing trace with hash -201957554, now seen corresponding path program 1 times [2025-03-04 16:47:41,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:41,700 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497431882] [2025-03-04 16:47:41,700 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:41,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:41,720 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-04 16:47:41,780 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-04 16:47:41,780 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:41,780 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:41,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:41,908 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:41,908 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497431882] [2025-03-04 16:47:41,908 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [497431882] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:41,908 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:41,908 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-04 16:47:41,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325117804] [2025-03-04 16:47:41,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:41,909 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:41,909 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:41,909 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-04 16:47:41,910 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2025-03-04 16:47:41,910 INFO L87 Difference]: Start difference. First operand 507 states and 709 transitions. cyclomatic complexity: 207 Second operand has 9 states, 9 states have (on average 8.88888888888889) internal successors, (80), 9 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:42,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:42,521 INFO L93 Difference]: Finished difference Result 553 states and 774 transitions. [2025-03-04 16:47:42,521 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 553 states and 774 transitions. [2025-03-04 16:47:42,523 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 543 [2025-03-04 16:47:42,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 553 states to 553 states and 774 transitions. [2025-03-04 16:47:42,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 553 [2025-03-04 16:47:42,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 553 [2025-03-04 16:47:42,524 INFO L73 IsDeterministic]: Start isDeterministic. Operand 553 states and 774 transitions. [2025-03-04 16:47:42,525 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:42,525 INFO L218 hiAutomatonCegarLoop]: Abstraction has 553 states and 774 transitions. [2025-03-04 16:47:42,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states and 774 transitions. [2025-03-04 16:47:42,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 522. [2025-03-04 16:47:42,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 522 states, 518 states have (on average 1.3918918918918919) internal successors, (721), 517 states have internal predecessors, (721), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:42,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 522 states to 522 states and 727 transitions. [2025-03-04 16:47:42,530 INFO L240 hiAutomatonCegarLoop]: Abstraction has 522 states and 727 transitions. [2025-03-04 16:47:42,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 16:47:42,531 INFO L432 stractBuchiCegarLoop]: Abstraction has 522 states and 727 transitions. [2025-03-04 16:47:42,531 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-04 16:47:42,531 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 522 states and 727 transitions. [2025-03-04 16:47:42,532 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 512 [2025-03-04 16:47:42,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:42,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:42,532 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:42,532 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:42,532 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:42,533 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise45#1;assume main_#t~bitwise45#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:42,533 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:42,533 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 20 times [2025-03-04 16:47:42,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:42,534 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068423876] [2025-03-04 16:47:42,534 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:47:42,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:42,539 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:42,540 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:42,540 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:47:42,540 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:42,540 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:42,541 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:42,542 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:42,542 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:42,542 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:42,550 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:42,551 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:42,551 INFO L85 PathProgramCache]: Analyzing trace with hash -2114419265, now seen corresponding path program 1 times [2025-03-04 16:47:42,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:42,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587475570] [2025-03-04 16:47:42,551 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:42,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:42,575 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-04 16:47:42,703 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-04 16:47:42,704 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:42,704 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:43,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:43,283 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:43,283 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1587475570] [2025-03-04 16:47:43,283 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1587475570] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:43,283 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:43,283 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2025-03-04 16:47:43,283 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [973215979] [2025-03-04 16:47:43,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:43,284 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:43,284 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:43,284 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2025-03-04 16:47:43,285 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=265, Unknown=0, NotChecked=0, Total=306 [2025-03-04 16:47:43,285 INFO L87 Difference]: Start difference. First operand 522 states and 727 transitions. cyclomatic complexity: 210 Second operand has 18 states, 18 states have (on average 4.444444444444445) internal successors, (80), 18 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:45,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:45,206 INFO L93 Difference]: Finished difference Result 633 states and 887 transitions. [2025-03-04 16:47:45,206 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 887 transitions. [2025-03-04 16:47:45,208 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 623 [2025-03-04 16:47:45,209 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 887 transitions. [2025-03-04 16:47:45,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2025-03-04 16:47:45,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2025-03-04 16:47:45,210 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 887 transitions. [2025-03-04 16:47:45,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:45,210 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 887 transitions. [2025-03-04 16:47:45,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 887 transitions. [2025-03-04 16:47:45,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 536. [2025-03-04 16:47:45,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 536 states, 532 states have (on average 1.3909774436090225) internal successors, (740), 531 states have internal predecessors, (740), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:45,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 536 states and 746 transitions. [2025-03-04 16:47:45,215 INFO L240 hiAutomatonCegarLoop]: Abstraction has 536 states and 746 transitions. [2025-03-04 16:47:45,215 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2025-03-04 16:47:45,216 INFO L432 stractBuchiCegarLoop]: Abstraction has 536 states and 746 transitions. [2025-03-04 16:47:45,216 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-03-04 16:47:45,216 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 536 states and 746 transitions. [2025-03-04 16:47:45,217 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 526 [2025-03-04 16:47:45,217 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:45,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:45,218 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:45,218 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:45,218 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:45,219 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise45#1;assume main_#t~bitwise45#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:45,219 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:45,219 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 21 times [2025-03-04 16:47:45,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:45,219 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101074102] [2025-03-04 16:47:45,219 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:47:45,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:45,225 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:45,226 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:45,226 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:47:45,226 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:45,226 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:45,227 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:45,228 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:45,228 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:45,228 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:45,233 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:45,233 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:45,233 INFO L85 PathProgramCache]: Analyzing trace with hash 1177092653, now seen corresponding path program 1 times [2025-03-04 16:47:45,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:45,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320819773] [2025-03-04 16:47:45,234 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:45,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:45,255 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-04 16:47:45,285 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-04 16:47:45,285 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:45,285 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:45,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:47:45,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:47:45,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320819773] [2025-03-04 16:47:45,544 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320819773] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:47:45,544 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:47:45,544 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-04 16:47:45,544 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84364148] [2025-03-04 16:47:45,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:47:45,544 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:47:45,545 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:47:45,545 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-04 16:47:45,545 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-03-04 16:47:45,545 INFO L87 Difference]: Start difference. First operand 536 states and 746 transitions. cyclomatic complexity: 215 Second operand has 10 states, 10 states have (on average 8.0) internal successors, (80), 10 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:47:46,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:47:46,448 INFO L93 Difference]: Finished difference Result 548 states and 763 transitions. [2025-03-04 16:47:46,448 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 548 states and 763 transitions. [2025-03-04 16:47:46,450 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 538 [2025-03-04 16:47:46,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 548 states to 548 states and 763 transitions. [2025-03-04 16:47:46,451 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 548 [2025-03-04 16:47:46,452 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 548 [2025-03-04 16:47:46,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 548 states and 763 transitions. [2025-03-04 16:47:46,452 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:47:46,452 INFO L218 hiAutomatonCegarLoop]: Abstraction has 548 states and 763 transitions. [2025-03-04 16:47:46,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 548 states and 763 transitions. [2025-03-04 16:47:46,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 548 to 540. [2025-03-04 16:47:46,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 540 states, 536 states have (on average 1.3899253731343284) internal successors, (745), 535 states have internal predecessors, (745), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:47:46,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 540 states to 540 states and 751 transitions. [2025-03-04 16:47:46,457 INFO L240 hiAutomatonCegarLoop]: Abstraction has 540 states and 751 transitions. [2025-03-04 16:47:46,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 16:47:46,457 INFO L432 stractBuchiCegarLoop]: Abstraction has 540 states and 751 transitions. [2025-03-04 16:47:46,458 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-03-04 16:47:46,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 540 states and 751 transitions. [2025-03-04 16:47:46,458 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 530 [2025-03-04 16:47:46,460 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:47:46,460 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:47:46,460 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:47:46,460 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:47:46,461 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1, main_#t~post160#1, main_#t~mem161#1, main_#t~mem163#1, main_#t~mem162#1, main_#t~mem164#1, main_#t~mem165#1, main_#t~mem167#1, main_#t~mem166#1, main_#t~mem168#1, main_#t~mem169#1, main_#t~mem171#1, main_#t~mem170#1, main_#t~mem172#1, main_#t~mem173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~switch183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem204#1.base, main_#t~mem204#1.offset, main_#t~mem205#1, main_#t~bitwise206#1, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1, main_#t~mem215#1, main_#t~mem216#1, main_#t~short217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~nondet219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1.base, main_#t~mem221#1.offset, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~short226#1, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1.base, main_#t~mem237#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem249#1, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~bitwise250#1, main_#t~mem251#1.base, main_#t~mem251#1.offset, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~mem253#1, main_#t~post254#1, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~post265#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem266#1, main_#t~mem267#1, main_#t~mem268#1, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~ite271#1.base, main_#t~ite271#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~short274#1, main_#t~mem275#1.base, main_#t~mem275#1.offset, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1, main_#t~mem284#1.base, main_#t~mem284#1.offset, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem297#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1, main_#t~bitwise298#1, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1, main_#t~post302#1, main_#t~mem303#1.base, main_#t~mem303#1.offset, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1, main_#t~post313#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite315#1.base, main_#t~ite315#1.offset, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:47:46,461 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#1(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#1(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#1(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#1(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem89#1.base, 12 + main_#t~mem89#1.offset, 4);havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#1(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post160#1 := main_#t~mem159#1;call write~int#2(1 + main_#t~post160#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem159#1;havoc main_#t~post160#1;" [2025-03-04 16:47:46,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:46,461 INFO L85 PathProgramCache]: Analyzing trace with hash 26208, now seen corresponding path program 22 times [2025-03-04 16:47:46,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:46,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [311126272] [2025-03-04 16:47:46,462 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:47:46,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:46,470 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 16:47:46,471 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:46,471 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 16:47:46,471 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:46,471 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:47:46,473 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:47:46,474 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:47:46,474 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:46,474 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:47:46,478 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:47:46,479 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:47:46,479 INFO L85 PathProgramCache]: Analyzing trace with hash -651871746, now seen corresponding path program 1 times [2025-03-04 16:47:46,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:47:46,479 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482594475] [2025-03-04 16:47:46,479 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:47:46,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:47:46,501 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-04 16:47:46,556 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-04 16:47:46,556 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:47:46,556 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:47:58,849 WARN L286 SmtUtils]: Spent 12.01s on a formula simplification that was a NOOP. DAG size: 32 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2025-03-04 16:48:06,816 WARN L286 SmtUtils]: Spent 7.96s on a formula simplification that was a NOOP. DAG size: 10 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2025-03-04 16:48:20,000 WARN L286 SmtUtils]: Spent 13.17s on a formula simplification that was a NOOP. DAG size: 39 (called from [L 388] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2025-03-04 16:48:32,010 WARN L286 SmtUtils]: Spent 12.01s on a formula simplification that was a NOOP. DAG size: 26 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2025-03-04 16:48:41,914 WARN L286 SmtUtils]: Spent 9.90s on a formula simplification that was a NOOP. DAG size: 10 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify)