./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/kundu2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e2fb8bed Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/kundu2.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf --- Real Ultimate output --- This is Ultimate 0.3.0-?-e2fb8be-m [2025-03-09 07:34:03,805 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-09 07:34:03,859 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-09 07:34:03,862 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-09 07:34:03,864 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-09 07:34:03,864 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-09 07:34:03,885 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-09 07:34:03,886 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-09 07:34:03,886 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-09 07:34:03,886 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-09 07:34:03,886 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-09 07:34:03,887 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-09 07:34:03,887 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-09 07:34:03,887 INFO L153 SettingsManager]: * Use SBE=true [2025-03-09 07:34:03,887 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-09 07:34:03,887 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-09 07:34:03,888 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-09 07:34:03,888 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-09 07:34:03,888 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-09 07:34:03,888 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-09 07:34:03,888 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-09 07:34:03,888 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-09 07:34:03,888 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-09 07:34:03,888 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-09 07:34:03,888 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-09 07:34:03,888 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-09 07:34:03,889 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-09 07:34:03,889 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-09 07:34:03,889 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-09 07:34:03,889 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-09 07:34:03,889 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-09 07:34:03,889 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-09 07:34:03,889 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-09 07:34:03,889 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-09 07:34:03,890 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-09 07:34:03,890 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-09 07:34:03,890 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-09 07:34:03,890 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-09 07:34:03,890 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-09 07:34:03,890 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-09 07:34:03,890 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf [2025-03-09 07:34:04,128 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-09 07:34:04,135 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-09 07:34:04,137 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-09 07:34:04,138 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-09 07:34:04,139 INFO L274 PluginConnector]: CDTParser initialized [2025-03-09 07:34:04,140 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/kundu2.cil.c [2025-03-09 07:34:05,273 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/53c04d9a9/c693f6c0e8b149c8bcf1002d1ead2cc3/FLAG0e6d2d57f [2025-03-09 07:34:05,537 INFO L384 CDTParser]: Found 1 translation units. [2025-03-09 07:34:05,537 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu2.cil.c [2025-03-09 07:34:05,549 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/53c04d9a9/c693f6c0e8b149c8bcf1002d1ead2cc3/FLAG0e6d2d57f [2025-03-09 07:34:05,855 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/53c04d9a9/c693f6c0e8b149c8bcf1002d1ead2cc3 [2025-03-09 07:34:05,857 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-09 07:34:05,859 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-09 07:34:05,860 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-09 07:34:05,860 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-09 07:34:05,864 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-09 07:34:05,865 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 07:34:05" (1/1) ... [2025-03-09 07:34:05,868 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2d6bf1fb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:05, skipping insertion in model container [2025-03-09 07:34:05,868 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 07:34:05" (1/1) ... [2025-03-09 07:34:05,891 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-09 07:34:06,014 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 07:34:06,024 INFO L200 MainTranslator]: Completed pre-run [2025-03-09 07:34:06,061 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 07:34:06,076 INFO L204 MainTranslator]: Completed translation [2025-03-09 07:34:06,077 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06 WrapperNode [2025-03-09 07:34:06,077 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-09 07:34:06,078 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-09 07:34:06,078 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-09 07:34:06,078 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-09 07:34:06,082 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06" (1/1) ... [2025-03-09 07:34:06,089 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06" (1/1) ... [2025-03-09 07:34:06,114 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 49, statements flattened = 520 [2025-03-09 07:34:06,117 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-09 07:34:06,117 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-09 07:34:06,118 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-09 07:34:06,118 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-09 07:34:06,124 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06" (1/1) ... [2025-03-09 07:34:06,124 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06" (1/1) ... [2025-03-09 07:34:06,126 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06" (1/1) ... [2025-03-09 07:34:06,146 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-09 07:34:06,147 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06" (1/1) ... [2025-03-09 07:34:06,147 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06" (1/1) ... [2025-03-09 07:34:06,154 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06" (1/1) ... [2025-03-09 07:34:06,159 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06" (1/1) ... [2025-03-09 07:34:06,159 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06" (1/1) ... [2025-03-09 07:34:06,160 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06" (1/1) ... [2025-03-09 07:34:06,170 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-09 07:34:06,170 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-09 07:34:06,170 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-09 07:34:06,170 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-09 07:34:06,171 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06" (1/1) ... [2025-03-09 07:34:06,176 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 07:34:06,189 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 07:34:06,202 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 07:34:06,209 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-09 07:34:06,227 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-09 07:34:06,228 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-09 07:34:06,228 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-09 07:34:06,228 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-09 07:34:06,281 INFO L256 CfgBuilder]: Building ICFG [2025-03-09 07:34:06,283 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-09 07:34:06,714 INFO L? ?]: Removed 101 outVars from TransFormulas that were not future-live. [2025-03-09 07:34:06,714 INFO L307 CfgBuilder]: Performing block encoding [2025-03-09 07:34:06,732 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-09 07:34:06,732 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-09 07:34:06,732 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:34:06 BoogieIcfgContainer [2025-03-09 07:34:06,732 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-09 07:34:06,733 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-09 07:34:06,733 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-09 07:34:06,737 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-09 07:34:06,738 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:34:06,738 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.03 07:34:05" (1/3) ... [2025-03-09 07:34:06,739 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c6a0085 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 07:34:06, skipping insertion in model container [2025-03-09 07:34:06,739 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:34:06,739 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:34:06" (2/3) ... [2025-03-09 07:34:06,739 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c6a0085 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 07:34:06, skipping insertion in model container [2025-03-09 07:34:06,739 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:34:06,739 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:34:06" (3/3) ... [2025-03-09 07:34:06,740 INFO L363 chiAutomizerObserver]: Analyzing ICFG kundu2.cil.c [2025-03-09 07:34:06,781 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-09 07:34:06,782 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-09 07:34:06,782 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-09 07:34:06,782 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-09 07:34:06,782 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-09 07:34:06,783 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-09 07:34:06,783 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-09 07:34:06,783 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-09 07:34:06,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 192 states, 191 states have (on average 1.4712041884816753) internal successors, (281), 191 states have internal predecessors, (281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:06,809 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 155 [2025-03-09 07:34:06,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:06,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:06,818 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:06,818 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:06,818 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-09 07:34:06,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 192 states, 191 states have (on average 1.4712041884816753) internal successors, (281), 191 states have internal predecessors, (281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:06,827 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 155 [2025-03-09 07:34:06,829 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:06,829 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:06,830 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:06,831 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:06,836 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume !(1 == ~P_2_i~0);~P_2_st~0 := 2;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:34:06,837 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume !true;" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-09 07:34:06,840 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:06,841 INFO L85 PathProgramCache]: Analyzing trace with hash -2102344992, now seen corresponding path program 1 times [2025-03-09 07:34:06,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:06,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [376648826] [2025-03-09 07:34:06,846 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:06,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:06,903 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-09 07:34:06,917 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-09 07:34:06,917 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:06,917 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:07,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:07,006 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:07,007 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [376648826] [2025-03-09 07:34:07,007 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [376648826] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:07,007 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:07,007 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:34:07,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1836711263] [2025-03-09 07:34:07,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:07,012 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:34:07,012 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:07,013 INFO L85 PathProgramCache]: Analyzing trace with hash 1180024626, now seen corresponding path program 1 times [2025-03-09 07:34:07,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:07,013 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531698617] [2025-03-09 07:34:07,013 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:07,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:07,026 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-03-09 07:34:07,028 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-03-09 07:34:07,028 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:07,028 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:07,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:07,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:07,046 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [531698617] [2025-03-09 07:34:07,046 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [531698617] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:07,046 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:07,047 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 07:34:07,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [731661363] [2025-03-09 07:34:07,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:07,048 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:34:07,049 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:34:07,069 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:34:07,070 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:34:07,073 INFO L87 Difference]: Start difference. First operand has 192 states, 191 states have (on average 1.4712041884816753) internal successors, (281), 191 states have internal predecessors, (281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:07,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:34:07,120 INFO L93 Difference]: Finished difference Result 184 states and 266 transitions. [2025-03-09 07:34:07,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 184 states and 266 transitions. [2025-03-09 07:34:07,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 143 [2025-03-09 07:34:07,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 184 states to 176 states and 258 transitions. [2025-03-09 07:34:07,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176 [2025-03-09 07:34:07,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176 [2025-03-09 07:34:07,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176 states and 258 transitions. [2025-03-09 07:34:07,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:34:07,135 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176 states and 258 transitions. [2025-03-09 07:34:07,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states and 258 transitions. [2025-03-09 07:34:07,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 176. [2025-03-09 07:34:07,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 176 states, 176 states have (on average 1.4659090909090908) internal successors, (258), 175 states have internal predecessors, (258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:07,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 258 transitions. [2025-03-09 07:34:07,168 INFO L240 hiAutomatonCegarLoop]: Abstraction has 176 states and 258 transitions. [2025-03-09 07:34:07,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:34:07,171 INFO L432 stractBuchiCegarLoop]: Abstraction has 176 states and 258 transitions. [2025-03-09 07:34:07,172 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-09 07:34:07,172 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 176 states and 258 transitions. [2025-03-09 07:34:07,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 143 [2025-03-09 07:34:07,173 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:07,173 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:07,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:07,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:07,174 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:34:07,174 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-09 07:34:07,175 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:07,175 INFO L85 PathProgramCache]: Analyzing trace with hash 947857823, now seen corresponding path program 1 times [2025-03-09 07:34:07,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:07,175 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123980018] [2025-03-09 07:34:07,175 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:07,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:07,181 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-09 07:34:07,188 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-09 07:34:07,188 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:07,188 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:07,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:07,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:07,228 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [123980018] [2025-03-09 07:34:07,228 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [123980018] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:07,228 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:07,228 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:34:07,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [553448416] [2025-03-09 07:34:07,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:07,229 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:34:07,229 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:07,230 INFO L85 PathProgramCache]: Analyzing trace with hash -102624950, now seen corresponding path program 1 times [2025-03-09 07:34:07,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:07,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2137759450] [2025-03-09 07:34:07,230 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:07,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:07,240 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-09 07:34:07,256 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 07:34:07,257 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:07,257 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:07,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:07,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:07,313 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2137759450] [2025-03-09 07:34:07,314 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2137759450] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:07,314 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:07,314 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:34:07,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [268250094] [2025-03-09 07:34:07,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:07,314 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:34:07,314 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:34:07,315 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:34:07,315 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:34:07,315 INFO L87 Difference]: Start difference. First operand 176 states and 258 transitions. cyclomatic complexity: 83 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:07,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:34:07,326 INFO L93 Difference]: Finished difference Result 176 states and 257 transitions. [2025-03-09 07:34:07,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 176 states and 257 transitions. [2025-03-09 07:34:07,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 143 [2025-03-09 07:34:07,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 176 states to 176 states and 257 transitions. [2025-03-09 07:34:07,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 176 [2025-03-09 07:34:07,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 176 [2025-03-09 07:34:07,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176 states and 257 transitions. [2025-03-09 07:34:07,330 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:34:07,330 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176 states and 257 transitions. [2025-03-09 07:34:07,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states and 257 transitions. [2025-03-09 07:34:07,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 176. [2025-03-09 07:34:07,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 176 states, 176 states have (on average 1.4602272727272727) internal successors, (257), 175 states have internal predecessors, (257), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:07,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 257 transitions. [2025-03-09 07:34:07,339 INFO L240 hiAutomatonCegarLoop]: Abstraction has 176 states and 257 transitions. [2025-03-09 07:34:07,340 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:34:07,341 INFO L432 stractBuchiCegarLoop]: Abstraction has 176 states and 257 transitions. [2025-03-09 07:34:07,341 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-09 07:34:07,341 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 176 states and 257 transitions. [2025-03-09 07:34:07,343 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 143 [2025-03-09 07:34:07,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:07,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:07,345 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:07,346 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:07,346 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:34:07,346 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-09 07:34:07,346 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:07,348 INFO L85 PathProgramCache]: Analyzing trace with hash -1309053184, now seen corresponding path program 1 times [2025-03-09 07:34:07,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:07,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697819983] [2025-03-09 07:34:07,348 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:07,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:07,354 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-09 07:34:07,363 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-09 07:34:07,363 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:07,363 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:07,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:07,411 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:07,411 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697819983] [2025-03-09 07:34:07,411 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697819983] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:07,411 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:07,411 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:34:07,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [100190414] [2025-03-09 07:34:07,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:07,411 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:34:07,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:07,412 INFO L85 PathProgramCache]: Analyzing trace with hash -102624950, now seen corresponding path program 2 times [2025-03-09 07:34:07,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:07,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1874089614] [2025-03-09 07:34:07,412 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:34:07,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:07,420 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 40 statements into 1 equivalence classes. [2025-03-09 07:34:07,427 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 07:34:07,430 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:34:07,430 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:07,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:07,472 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:07,472 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1874089614] [2025-03-09 07:34:07,472 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1874089614] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:07,472 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:07,472 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:34:07,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1924002865] [2025-03-09 07:34:07,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:07,472 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:34:07,473 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:34:07,473 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:34:07,473 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:34:07,473 INFO L87 Difference]: Start difference. First operand 176 states and 257 transitions. cyclomatic complexity: 82 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:07,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:34:07,520 INFO L93 Difference]: Finished difference Result 314 states and 454 transitions. [2025-03-09 07:34:07,520 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 314 states and 454 transitions. [2025-03-09 07:34:07,522 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 282 [2025-03-09 07:34:07,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 314 states to 314 states and 454 transitions. [2025-03-09 07:34:07,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 314 [2025-03-09 07:34:07,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 314 [2025-03-09 07:34:07,525 INFO L73 IsDeterministic]: Start isDeterministic. Operand 314 states and 454 transitions. [2025-03-09 07:34:07,526 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:34:07,526 INFO L218 hiAutomatonCegarLoop]: Abstraction has 314 states and 454 transitions. [2025-03-09 07:34:07,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314 states and 454 transitions. [2025-03-09 07:34:07,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314 to 310. [2025-03-09 07:34:07,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 310 states, 310 states have (on average 1.4483870967741936) internal successors, (449), 309 states have internal predecessors, (449), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:07,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 310 states to 310 states and 449 transitions. [2025-03-09 07:34:07,538 INFO L240 hiAutomatonCegarLoop]: Abstraction has 310 states and 449 transitions. [2025-03-09 07:34:07,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:34:07,539 INFO L432 stractBuchiCegarLoop]: Abstraction has 310 states and 449 transitions. [2025-03-09 07:34:07,539 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-09 07:34:07,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 310 states and 449 transitions. [2025-03-09 07:34:07,541 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 278 [2025-03-09 07:34:07,541 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:07,542 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:07,542 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:07,543 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:07,543 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:34:07,543 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-09 07:34:07,544 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:07,544 INFO L85 PathProgramCache]: Analyzing trace with hash -159380349, now seen corresponding path program 1 times [2025-03-09 07:34:07,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:07,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744210462] [2025-03-09 07:34:07,544 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:07,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:07,550 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-09 07:34:07,556 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-09 07:34:07,557 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:07,557 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:07,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:07,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:07,607 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744210462] [2025-03-09 07:34:07,607 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744210462] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:07,607 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:07,607 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-09 07:34:07,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1075486521] [2025-03-09 07:34:07,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:07,608 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:34:07,608 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:07,608 INFO L85 PathProgramCache]: Analyzing trace with hash 225542733, now seen corresponding path program 1 times [2025-03-09 07:34:07,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:07,609 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70566628] [2025-03-09 07:34:07,609 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:07,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:07,615 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-09 07:34:07,621 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 07:34:07,622 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:07,622 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:07,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:07,663 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:07,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [70566628] [2025-03-09 07:34:07,663 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [70566628] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:07,664 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:07,664 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:34:07,664 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1987698380] [2025-03-09 07:34:07,664 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:07,665 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:34:07,665 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:34:07,665 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-09 07:34:07,665 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-09 07:34:07,665 INFO L87 Difference]: Start difference. First operand 310 states and 449 transitions. cyclomatic complexity: 140 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:07,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:34:07,759 INFO L93 Difference]: Finished difference Result 717 states and 1023 transitions. [2025-03-09 07:34:07,759 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 717 states and 1023 transitions. [2025-03-09 07:34:07,763 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 654 [2025-03-09 07:34:07,766 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 717 states to 717 states and 1023 transitions. [2025-03-09 07:34:07,767 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 717 [2025-03-09 07:34:07,768 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 717 [2025-03-09 07:34:07,768 INFO L73 IsDeterministic]: Start isDeterministic. Operand 717 states and 1023 transitions. [2025-03-09 07:34:07,769 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:34:07,769 INFO L218 hiAutomatonCegarLoop]: Abstraction has 717 states and 1023 transitions. [2025-03-09 07:34:07,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 717 states and 1023 transitions. [2025-03-09 07:34:07,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 717 to 549. [2025-03-09 07:34:07,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 549 states, 549 states have (on average 1.4371584699453552) internal successors, (789), 548 states have internal predecessors, (789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:07,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 549 states and 789 transitions. [2025-03-09 07:34:07,813 INFO L240 hiAutomatonCegarLoop]: Abstraction has 549 states and 789 transitions. [2025-03-09 07:34:07,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-09 07:34:07,814 INFO L432 stractBuchiCegarLoop]: Abstraction has 549 states and 789 transitions. [2025-03-09 07:34:07,814 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-09 07:34:07,814 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 549 states and 789 transitions. [2025-03-09 07:34:07,816 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 518 [2025-03-09 07:34:07,816 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:07,816 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:07,818 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:07,818 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:07,819 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:34:07,819 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-09 07:34:07,819 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:07,820 INFO L85 PathProgramCache]: Analyzing trace with hash -710948794, now seen corresponding path program 1 times [2025-03-09 07:34:07,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:07,820 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1669599697] [2025-03-09 07:34:07,820 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:07,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:07,825 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-09 07:34:07,827 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-09 07:34:07,827 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:07,827 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:07,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:07,859 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:07,859 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1669599697] [2025-03-09 07:34:07,859 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1669599697] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:07,859 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:07,859 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-09 07:34:07,859 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1532952764] [2025-03-09 07:34:07,859 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:07,860 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:34:07,860 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:07,860 INFO L85 PathProgramCache]: Analyzing trace with hash -1717653104, now seen corresponding path program 1 times [2025-03-09 07:34:07,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:07,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040827420] [2025-03-09 07:34:07,861 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:07,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:07,866 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-09 07:34:07,870 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 07:34:07,870 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:07,870 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:07,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:07,898 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:07,898 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040827420] [2025-03-09 07:34:07,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040827420] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:07,898 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:07,898 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:34:07,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [720385302] [2025-03-09 07:34:07,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:07,898 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:34:07,898 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:34:07,899 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-09 07:34:07,899 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-09 07:34:07,899 INFO L87 Difference]: Start difference. First operand 549 states and 789 transitions. cyclomatic complexity: 241 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:07,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:34:07,988 INFO L93 Difference]: Finished difference Result 1284 states and 1805 transitions. [2025-03-09 07:34:07,988 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1284 states and 1805 transitions. [2025-03-09 07:34:07,994 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1230 [2025-03-09 07:34:07,999 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1284 states to 1284 states and 1805 transitions. [2025-03-09 07:34:07,999 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1284 [2025-03-09 07:34:08,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1284 [2025-03-09 07:34:08,001 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1284 states and 1805 transitions. [2025-03-09 07:34:08,002 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:34:08,002 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1284 states and 1805 transitions. [2025-03-09 07:34:08,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1284 states and 1805 transitions. [2025-03-09 07:34:08,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1284 to 1002. [2025-03-09 07:34:08,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002 states, 1002 states have (on average 1.4191616766467066) internal successors, (1422), 1001 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:08,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002 states to 1002 states and 1422 transitions. [2025-03-09 07:34:08,030 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002 states and 1422 transitions. [2025-03-09 07:34:08,032 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-09 07:34:08,033 INFO L432 stractBuchiCegarLoop]: Abstraction has 1002 states and 1422 transitions. [2025-03-09 07:34:08,033 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-09 07:34:08,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002 states and 1422 transitions. [2025-03-09 07:34:08,037 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 972 [2025-03-09 07:34:08,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:08,037 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:08,039 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:08,039 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:08,039 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume 2 == ~C_1_pc~0;" "assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:34:08,040 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume 2 == ~C_1_pc~0;" "assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-09 07:34:08,041 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:08,041 INFO L85 PathProgramCache]: Analyzing trace with hash -1396480466, now seen corresponding path program 1 times [2025-03-09 07:34:08,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:08,041 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [97605143] [2025-03-09 07:34:08,041 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:08,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:08,049 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-09 07:34:08,055 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-09 07:34:08,055 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:08,055 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:08,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:08,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:08,086 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [97605143] [2025-03-09 07:34:08,086 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [97605143] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:08,086 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:08,086 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:34:08,086 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [745801554] [2025-03-09 07:34:08,086 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:08,086 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:34:08,087 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:08,087 INFO L85 PathProgramCache]: Analyzing trace with hash 1776207109, now seen corresponding path program 1 times [2025-03-09 07:34:08,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:08,087 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073575389] [2025-03-09 07:34:08,087 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:08,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:08,092 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-09 07:34:08,096 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-09 07:34:08,098 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:08,099 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:08,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:08,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:08,131 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2073575389] [2025-03-09 07:34:08,131 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2073575389] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:08,132 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:08,132 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:34:08,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [463900538] [2025-03-09 07:34:08,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:08,132 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:34:08,132 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:34:08,132 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:34:08,132 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:34:08,133 INFO L87 Difference]: Start difference. First operand 1002 states and 1422 transitions. cyclomatic complexity: 421 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:08,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:34:08,172 INFO L93 Difference]: Finished difference Result 1491 states and 2089 transitions. [2025-03-09 07:34:08,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1491 states and 2089 transitions. [2025-03-09 07:34:08,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1462 [2025-03-09 07:34:08,199 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1491 states to 1491 states and 2089 transitions. [2025-03-09 07:34:08,200 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1491 [2025-03-09 07:34:08,201 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1491 [2025-03-09 07:34:08,201 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1491 states and 2089 transitions. [2025-03-09 07:34:08,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:34:08,202 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1491 states and 2089 transitions. [2025-03-09 07:34:08,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1491 states and 2089 transitions. [2025-03-09 07:34:08,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1491 to 1459. [2025-03-09 07:34:08,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1459 states, 1459 states have (on average 1.4043865661411925) internal successors, (2049), 1458 states have internal predecessors, (2049), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:08,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1459 states to 1459 states and 2049 transitions. [2025-03-09 07:34:08,219 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1459 states and 2049 transitions. [2025-03-09 07:34:08,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:34:08,220 INFO L432 stractBuchiCegarLoop]: Abstraction has 1459 states and 2049 transitions. [2025-03-09 07:34:08,220 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-09 07:34:08,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1459 states and 2049 transitions. [2025-03-09 07:34:08,224 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1430 [2025-03-09 07:34:08,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:08,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:08,225 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:08,225 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:08,225 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:34:08,226 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-09 07:34:08,226 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:08,226 INFO L85 PathProgramCache]: Analyzing trace with hash -566235087, now seen corresponding path program 1 times [2025-03-09 07:34:08,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:08,226 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338135798] [2025-03-09 07:34:08,226 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:08,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:08,230 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-09 07:34:08,231 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-09 07:34:08,231 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:08,231 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:08,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:08,263 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:08,263 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338135798] [2025-03-09 07:34:08,263 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [338135798] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:08,263 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:08,263 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:34:08,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1317465917] [2025-03-09 07:34:08,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:08,264 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:34:08,264 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:08,264 INFO L85 PathProgramCache]: Analyzing trace with hash -1369087352, now seen corresponding path program 1 times [2025-03-09 07:34:08,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:08,264 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507900414] [2025-03-09 07:34:08,264 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:08,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:08,267 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-09 07:34:08,269 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-09 07:34:08,269 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:08,269 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:08,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:08,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:08,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1507900414] [2025-03-09 07:34:08,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1507900414] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:08,290 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:08,290 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:34:08,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1120637893] [2025-03-09 07:34:08,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:08,291 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:34:08,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:34:08,291 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-09 07:34:08,291 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-09 07:34:08,291 INFO L87 Difference]: Start difference. First operand 1459 states and 2049 transitions. cyclomatic complexity: 591 Second operand has 5 states, 5 states have (on average 5.8) internal successors, (29), 5 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:08,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:34:08,347 INFO L93 Difference]: Finished difference Result 1519 states and 2098 transitions. [2025-03-09 07:34:08,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1519 states and 2098 transitions. [2025-03-09 07:34:08,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1490 [2025-03-09 07:34:08,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1519 states to 1519 states and 2098 transitions. [2025-03-09 07:34:08,359 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1519 [2025-03-09 07:34:08,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1519 [2025-03-09 07:34:08,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1519 states and 2098 transitions. [2025-03-09 07:34:08,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:34:08,362 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1519 states and 2098 transitions. [2025-03-09 07:34:08,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1519 states and 2098 transitions. [2025-03-09 07:34:08,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1519 to 1519. [2025-03-09 07:34:08,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1519 states, 1519 states have (on average 1.381171823568137) internal successors, (2098), 1518 states have internal predecessors, (2098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:08,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1519 states to 1519 states and 2098 transitions. [2025-03-09 07:34:08,379 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1519 states and 2098 transitions. [2025-03-09 07:34:08,380 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-09 07:34:08,380 INFO L432 stractBuchiCegarLoop]: Abstraction has 1519 states and 2098 transitions. [2025-03-09 07:34:08,380 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-09 07:34:08,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1519 states and 2098 transitions. [2025-03-09 07:34:08,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1490 [2025-03-09 07:34:08,385 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:08,385 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:08,386 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:08,386 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:08,386 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:34:08,386 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-09 07:34:08,387 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:08,387 INFO L85 PathProgramCache]: Analyzing trace with hash -566234126, now seen corresponding path program 1 times [2025-03-09 07:34:08,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:08,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988919646] [2025-03-09 07:34:08,387 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:08,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:08,390 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-09 07:34:08,392 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-09 07:34:08,392 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:08,392 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:08,392 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:34:08,394 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-09 07:34:08,398 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-09 07:34:08,399 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:08,399 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:08,416 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:34:08,418 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:08,418 INFO L85 PathProgramCache]: Analyzing trace with hash 138464457, now seen corresponding path program 1 times [2025-03-09 07:34:08,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:08,418 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126417628] [2025-03-09 07:34:08,418 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:08,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:08,427 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-09 07:34:08,429 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-09 07:34:08,429 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:08,429 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:08,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:08,472 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:08,472 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2126417628] [2025-03-09 07:34:08,472 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2126417628] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:08,472 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:08,473 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:34:08,473 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1395018647] [2025-03-09 07:34:08,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:08,474 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:34:08,474 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:34:08,474 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-09 07:34:08,475 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-09 07:34:08,475 INFO L87 Difference]: Start difference. First operand 1519 states and 2098 transitions. cyclomatic complexity: 580 Second operand has 5 states, 5 states have (on average 8.2) internal successors, (41), 5 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:08,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:34:08,517 INFO L93 Difference]: Finished difference Result 1603 states and 2182 transitions. [2025-03-09 07:34:08,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1603 states and 2182 transitions. [2025-03-09 07:34:08,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1574 [2025-03-09 07:34:08,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1603 states to 1603 states and 2182 transitions. [2025-03-09 07:34:08,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1603 [2025-03-09 07:34:08,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1603 [2025-03-09 07:34:08,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1603 states and 2182 transitions. [2025-03-09 07:34:08,549 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:34:08,550 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1603 states and 2182 transitions. [2025-03-09 07:34:08,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1603 states and 2182 transitions. [2025-03-09 07:34:08,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1603 to 1555. [2025-03-09 07:34:08,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1555 states, 1555 states have (on average 1.372347266881029) internal successors, (2134), 1554 states have internal predecessors, (2134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:08,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1555 states to 1555 states and 2134 transitions. [2025-03-09 07:34:08,566 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1555 states and 2134 transitions. [2025-03-09 07:34:08,566 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-09 07:34:08,568 INFO L432 stractBuchiCegarLoop]: Abstraction has 1555 states and 2134 transitions. [2025-03-09 07:34:08,568 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-09 07:34:08,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1555 states and 2134 transitions. [2025-03-09 07:34:08,573 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1526 [2025-03-09 07:34:08,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:08,574 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:08,574 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:08,574 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:08,574 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:34:08,574 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume !(0 == ~P_1_st~0);" "assume !(0 == ~P_2_st~0);" "assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-09 07:34:08,575 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:08,575 INFO L85 PathProgramCache]: Analyzing trace with hash -566234126, now seen corresponding path program 2 times [2025-03-09 07:34:08,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:08,575 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282698216] [2025-03-09 07:34:08,575 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:34:08,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:08,580 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 29 statements into 1 equivalence classes. [2025-03-09 07:34:08,585 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-09 07:34:08,585 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:34:08,585 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:08,585 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:34:08,586 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-09 07:34:08,587 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-09 07:34:08,587 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:08,588 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:08,593 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:34:08,594 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:08,594 INFO L85 PathProgramCache]: Analyzing trace with hash 485043986, now seen corresponding path program 1 times [2025-03-09 07:34:08,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:08,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747169853] [2025-03-09 07:34:08,594 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:08,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:08,597 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-09 07:34:08,599 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-09 07:34:08,599 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:08,599 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:08,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:08,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:08,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [747169853] [2025-03-09 07:34:08,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [747169853] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:08,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:08,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:34:08,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [781006119] [2025-03-09 07:34:08,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:08,634 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:34:08,634 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:34:08,634 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-09 07:34:08,634 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-09 07:34:08,634 INFO L87 Difference]: Start difference. First operand 1555 states and 2134 transitions. cyclomatic complexity: 580 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:08,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:34:08,689 INFO L93 Difference]: Finished difference Result 1609 states and 2169 transitions. [2025-03-09 07:34:08,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1609 states and 2169 transitions. [2025-03-09 07:34:08,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1580 [2025-03-09 07:34:08,699 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1609 states to 1609 states and 2169 transitions. [2025-03-09 07:34:08,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1609 [2025-03-09 07:34:08,700 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1609 [2025-03-09 07:34:08,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1609 states and 2169 transitions. [2025-03-09 07:34:08,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:34:08,702 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1609 states and 2169 transitions. [2025-03-09 07:34:08,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1609 states and 2169 transitions. [2025-03-09 07:34:08,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1609 to 1609. [2025-03-09 07:34:08,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1609 states, 1609 states have (on average 1.3480422622747048) internal successors, (2169), 1608 states have internal predecessors, (2169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:08,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1609 states to 1609 states and 2169 transitions. [2025-03-09 07:34:08,718 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1609 states and 2169 transitions. [2025-03-09 07:34:08,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-09 07:34:08,719 INFO L432 stractBuchiCegarLoop]: Abstraction has 1609 states and 2169 transitions. [2025-03-09 07:34:08,719 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-09 07:34:08,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1609 states and 2169 transitions. [2025-03-09 07:34:08,724 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1580 [2025-03-09 07:34:08,724 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:08,724 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:08,724 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:08,725 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:08,725 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:34:08,725 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume !(0 == ~P_1_st~0);" "assume !(0 == ~P_2_st~0);" "assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-09 07:34:08,725 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:08,726 INFO L85 PathProgramCache]: Analyzing trace with hash -566234126, now seen corresponding path program 3 times [2025-03-09 07:34:08,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:08,726 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143937461] [2025-03-09 07:34:08,726 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 07:34:08,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:08,729 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 29 statements into 1 equivalence classes. [2025-03-09 07:34:08,731 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-09 07:34:08,731 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 07:34:08,731 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:08,731 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:34:08,732 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-09 07:34:08,735 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-09 07:34:08,735 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:08,735 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:08,739 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:34:08,739 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:08,739 INFO L85 PathProgramCache]: Analyzing trace with hash 230307441, now seen corresponding path program 1 times [2025-03-09 07:34:08,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:08,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [237001961] [2025-03-09 07:34:08,740 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:08,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:08,743 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-09 07:34:08,744 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-09 07:34:08,744 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:08,744 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:08,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:08,756 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:08,756 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [237001961] [2025-03-09 07:34:08,756 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [237001961] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:08,756 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:08,756 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:34:08,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [195449373] [2025-03-09 07:34:08,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:08,756 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:34:08,756 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:34:08,758 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:34:08,759 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:34:08,759 INFO L87 Difference]: Start difference. First operand 1609 states and 2169 transitions. cyclomatic complexity: 561 Second operand has 3 states, 3 states have (on average 14.333333333333334) internal successors, (43), 3 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:08,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:34:08,801 INFO L93 Difference]: Finished difference Result 2546 states and 3379 transitions. [2025-03-09 07:34:08,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2546 states and 3379 transitions. [2025-03-09 07:34:08,810 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2474 [2025-03-09 07:34:08,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2546 states to 2546 states and 3379 transitions. [2025-03-09 07:34:08,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2546 [2025-03-09 07:34:08,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2546 [2025-03-09 07:34:08,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2546 states and 3379 transitions. [2025-03-09 07:34:08,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:34:08,822 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2546 states and 3379 transitions. [2025-03-09 07:34:08,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2546 states and 3379 transitions. [2025-03-09 07:34:08,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2546 to 2546. [2025-03-09 07:34:08,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2546 states, 2546 states have (on average 1.3271798900235663) internal successors, (3379), 2545 states have internal predecessors, (3379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:08,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2546 states to 2546 states and 3379 transitions. [2025-03-09 07:34:08,852 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2546 states and 3379 transitions. [2025-03-09 07:34:08,852 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:34:08,853 INFO L432 stractBuchiCegarLoop]: Abstraction has 2546 states and 3379 transitions. [2025-03-09 07:34:08,853 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-09 07:34:08,853 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2546 states and 3379 transitions. [2025-03-09 07:34:08,861 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2474 [2025-03-09 07:34:08,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:08,861 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:08,862 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:08,862 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:08,862 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~P_1_i~0);~P_1_st~0 := 2;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:34:08,863 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume !(0 == ~P_1_st~0);" "assume !(0 == ~P_2_st~0);" "assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume !(0 == ~P_1_st~0);" "assume 0 == ~P_2_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume !(0 == ~P_1_st~0);" "assume 0 == ~P_2_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-09 07:34:08,863 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:08,863 INFO L85 PathProgramCache]: Analyzing trace with hash 1651523827, now seen corresponding path program 1 times [2025-03-09 07:34:08,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:08,863 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814627562] [2025-03-09 07:34:08,863 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:08,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:08,868 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-09 07:34:08,869 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-09 07:34:08,869 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:08,869 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:08,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:08,880 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:08,880 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814627562] [2025-03-09 07:34:08,880 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [814627562] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:08,880 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:08,880 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:34:08,880 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661823163] [2025-03-09 07:34:08,880 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:08,881 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:34:08,881 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:08,881 INFO L85 PathProgramCache]: Analyzing trace with hash 1237990588, now seen corresponding path program 1 times [2025-03-09 07:34:08,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:08,881 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117959550] [2025-03-09 07:34:08,881 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:08,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:08,885 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 45 statements into 1 equivalence classes. [2025-03-09 07:34:08,888 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 45 of 45 statements. [2025-03-09 07:34:08,888 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:08,888 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:08,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:08,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:08,924 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [117959550] [2025-03-09 07:34:08,924 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [117959550] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:08,924 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:08,924 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:34:08,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240417695] [2025-03-09 07:34:08,925 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:08,925 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:34:08,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:34:08,925 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:34:08,925 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:34:08,925 INFO L87 Difference]: Start difference. First operand 2546 states and 3379 transitions. cyclomatic complexity: 836 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:08,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:34:08,937 INFO L93 Difference]: Finished difference Result 2522 states and 3353 transitions. [2025-03-09 07:34:08,937 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2522 states and 3353 transitions. [2025-03-09 07:34:08,946 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2474 [2025-03-09 07:34:08,955 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2522 states to 2522 states and 3353 transitions. [2025-03-09 07:34:08,955 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2522 [2025-03-09 07:34:08,957 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2522 [2025-03-09 07:34:08,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2522 states and 3353 transitions. [2025-03-09 07:34:08,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:34:08,959 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2522 states and 3353 transitions. [2025-03-09 07:34:08,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2522 states and 3353 transitions. [2025-03-09 07:34:08,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2522 to 2522. [2025-03-09 07:34:08,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2522 states, 2522 states have (on average 1.3295003965107057) internal successors, (3353), 2521 states have internal predecessors, (3353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:08,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2522 states to 2522 states and 3353 transitions. [2025-03-09 07:34:08,993 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2522 states and 3353 transitions. [2025-03-09 07:34:08,993 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:34:08,994 INFO L432 stractBuchiCegarLoop]: Abstraction has 2522 states and 3353 transitions. [2025-03-09 07:34:08,994 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-09 07:34:08,994 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2522 states and 3353 transitions. [2025-03-09 07:34:09,001 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2474 [2025-03-09 07:34:09,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:09,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:09,002 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:09,002 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:09,002 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" [2025-03-09 07:34:09,002 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume !(0 == ~P_2_st~0);" "assume !(0 == ~C_1_st~0);" [2025-03-09 07:34:09,003 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:09,003 INFO L85 PathProgramCache]: Analyzing trace with hash -373388409, now seen corresponding path program 1 times [2025-03-09 07:34:09,003 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:09,003 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908655297] [2025-03-09 07:34:09,003 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:09,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:09,007 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-09 07:34:09,009 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-09 07:34:09,009 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,009 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,009 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:34:09,010 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-09 07:34:09,012 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-09 07:34:09,012 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,012 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,016 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:34:09,017 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:09,017 INFO L85 PathProgramCache]: Analyzing trace with hash 1938552614, now seen corresponding path program 1 times [2025-03-09 07:34:09,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:09,017 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1836671691] [2025-03-09 07:34:09,017 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:09,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:09,019 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-09 07:34:09,020 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-09 07:34:09,020 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,020 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,020 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:34:09,021 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-09 07:34:09,021 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-09 07:34:09,021 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,021 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,023 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:34:09,023 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:09,023 INFO L85 PathProgramCache]: Analyzing trace with hash 1584071264, now seen corresponding path program 1 times [2025-03-09 07:34:09,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:09,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788924084] [2025-03-09 07:34:09,023 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:09,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:09,027 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-09 07:34:09,029 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-09 07:34:09,029 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,030 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:09,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:09,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:09,046 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788924084] [2025-03-09 07:34:09,046 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [788924084] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:09,046 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:09,046 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:34:09,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025154015] [2025-03-09 07:34:09,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:09,097 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:34:09,098 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:34:09,098 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:34:09,098 INFO L87 Difference]: Start difference. First operand 2522 states and 3353 transitions. cyclomatic complexity: 834 Second operand has 3 states, 3 states have (on average 13.0) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:09,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:34:09,151 INFO L93 Difference]: Finished difference Result 4165 states and 5460 transitions. [2025-03-09 07:34:09,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4165 states and 5460 transitions. [2025-03-09 07:34:09,171 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4099 [2025-03-09 07:34:09,186 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4165 states to 4165 states and 5460 transitions. [2025-03-09 07:34:09,186 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4165 [2025-03-09 07:34:09,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4165 [2025-03-09 07:34:09,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4165 states and 5460 transitions. [2025-03-09 07:34:09,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:34:09,194 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4165 states and 5460 transitions. [2025-03-09 07:34:09,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4165 states and 5460 transitions. [2025-03-09 07:34:09,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4165 to 4013. [2025-03-09 07:34:09,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4013 states, 4013 states have (on average 1.3157238973336656) internal successors, (5280), 4012 states have internal predecessors, (5280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:09,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4013 states to 4013 states and 5280 transitions. [2025-03-09 07:34:09,247 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4013 states and 5280 transitions. [2025-03-09 07:34:09,247 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:34:09,249 INFO L432 stractBuchiCegarLoop]: Abstraction has 4013 states and 5280 transitions. [2025-03-09 07:34:09,249 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-09 07:34:09,249 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4013 states and 5280 transitions. [2025-03-09 07:34:09,262 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3947 [2025-03-09 07:34:09,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:09,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:09,262 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:09,262 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:09,263 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" [2025-03-09 07:34:09,263 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume !(0 == ~C_1_st~0);" [2025-03-09 07:34:09,263 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:09,264 INFO L85 PathProgramCache]: Analyzing trace with hash -373388409, now seen corresponding path program 2 times [2025-03-09 07:34:09,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:09,264 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [279735970] [2025-03-09 07:34:09,264 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:34:09,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:09,269 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 30 statements into 1 equivalence classes. [2025-03-09 07:34:09,271 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-09 07:34:09,271 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:34:09,271 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,271 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:34:09,273 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-09 07:34:09,274 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-09 07:34:09,274 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,274 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,279 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:34:09,282 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:09,282 INFO L85 PathProgramCache]: Analyzing trace with hash -34409647, now seen corresponding path program 1 times [2025-03-09 07:34:09,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:09,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068196071] [2025-03-09 07:34:09,282 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:09,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:09,284 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-09 07:34:09,286 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-09 07:34:09,286 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,286 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,286 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:34:09,287 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-09 07:34:09,288 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-09 07:34:09,288 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,288 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,289 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:34:09,290 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:09,290 INFO L85 PathProgramCache]: Analyzing trace with hash 1861570391, now seen corresponding path program 1 times [2025-03-09 07:34:09,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:09,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987476103] [2025-03-09 07:34:09,290 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:09,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:09,294 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-09 07:34:09,296 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 07:34:09,296 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,296 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:34:09,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:34:09,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:34:09,313 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1987476103] [2025-03-09 07:34:09,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1987476103] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:34:09,313 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:34:09,313 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 07:34:09,313 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204992214] [2025-03-09 07:34:09,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:34:09,358 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:34:09,358 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:34:09,358 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:34:09,358 INFO L87 Difference]: Start difference. First operand 4013 states and 5280 transitions. cyclomatic complexity: 1270 Second operand has 3 states, 2 states have (on average 20.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:09,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:34:09,401 INFO L93 Difference]: Finished difference Result 6772 states and 8849 transitions. [2025-03-09 07:34:09,401 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6772 states and 8849 transitions. [2025-03-09 07:34:09,448 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6670 [2025-03-09 07:34:09,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6772 states to 6772 states and 8849 transitions. [2025-03-09 07:34:09,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6772 [2025-03-09 07:34:09,473 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6772 [2025-03-09 07:34:09,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6772 states and 8849 transitions. [2025-03-09 07:34:09,480 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:34:09,480 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6772 states and 8849 transitions. [2025-03-09 07:34:09,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6772 states and 8849 transitions. [2025-03-09 07:34:09,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6772 to 6772. [2025-03-09 07:34:09,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6772 states, 6772 states have (on average 1.3067040756054342) internal successors, (8849), 6771 states have internal predecessors, (8849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:34:09,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6772 states to 6772 states and 8849 transitions. [2025-03-09 07:34:09,557 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6772 states and 8849 transitions. [2025-03-09 07:34:09,558 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:34:09,558 INFO L432 stractBuchiCegarLoop]: Abstraction has 6772 states and 8849 transitions. [2025-03-09 07:34:09,558 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-09 07:34:09,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6772 states and 8849 transitions. [2025-03-09 07:34:09,576 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6670 [2025-03-09 07:34:09,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:34:09,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:34:09,577 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:09,577 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:34:09,577 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" [2025-03-09 07:34:09,578 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume 0 == ~C_1_st~0;havoc eval_#t~nondet8#1;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp___1~0#1);" [2025-03-09 07:34:09,578 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:09,578 INFO L85 PathProgramCache]: Analyzing trace with hash -373388409, now seen corresponding path program 3 times [2025-03-09 07:34:09,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:09,578 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106897807] [2025-03-09 07:34:09,578 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 07:34:09,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:09,581 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 30 statements into 1 equivalence classes. [2025-03-09 07:34:09,583 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-09 07:34:09,583 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 07:34:09,583 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,583 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:34:09,585 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-09 07:34:09,586 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-09 07:34:09,586 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,586 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,589 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:34:09,589 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:09,589 INFO L85 PathProgramCache]: Analyzing trace with hash -1066698898, now seen corresponding path program 1 times [2025-03-09 07:34:09,589 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:09,589 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082761049] [2025-03-09 07:34:09,589 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:09,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:09,591 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-03-09 07:34:09,592 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-03-09 07:34:09,592 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,592 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,592 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:34:09,592 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-03-09 07:34:09,593 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-03-09 07:34:09,593 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,593 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,594 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:34:09,594 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:34:09,594 INFO L85 PathProgramCache]: Analyzing trace with hash 1874107432, now seen corresponding path program 1 times [2025-03-09 07:34:09,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:34:09,595 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [813329017] [2025-03-09 07:34:09,595 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:34:09,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:34:09,598 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-09 07:34:09,600 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-09 07:34:09,600 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,600 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,600 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:34:09,601 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-09 07:34:09,603 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-09 07:34:09,603 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:09,603 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:09,606 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:34:10,215 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-09 07:34:10,219 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-09 07:34:10,219 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:10,219 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:10,219 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:34:10,226 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-09 07:34:10,229 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-09 07:34:10,230 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:34:10,230 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:34:10,305 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 09.03 07:34:10 BoogieIcfgContainer [2025-03-09 07:34:10,305 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-09 07:34:10,306 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-09 07:34:10,306 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-09 07:34:10,306 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-09 07:34:10,306 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:34:06" (3/4) ... [2025-03-09 07:34:10,308 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-03-09 07:34:10,360 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-09 07:34:10,360 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-09 07:34:10,362 INFO L158 Benchmark]: Toolchain (without parser) took 4502.19ms. Allocated memory was 142.6MB in the beginning and 285.2MB in the end (delta: 142.6MB). Free memory was 109.5MB in the beginning and 199.8MB in the end (delta: -90.3MB). Peak memory consumption was 55.3MB. Max. memory is 16.1GB. [2025-03-09 07:34:10,362 INFO L158 Benchmark]: CDTParser took 0.23ms. Allocated memory is still 201.3MB. Free memory is still 125.1MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-09 07:34:10,362 INFO L158 Benchmark]: CACSL2BoogieTranslator took 217.77ms. Allocated memory is still 142.6MB. Free memory was 109.5MB in the beginning and 95.2MB in the end (delta: 14.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-09 07:34:10,362 INFO L158 Benchmark]: Boogie Procedure Inliner took 38.87ms. Allocated memory is still 142.6MB. Free memory was 95.2MB in the beginning and 92.9MB in the end (delta: 2.3MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-09 07:34:10,363 INFO L158 Benchmark]: Boogie Preprocessor took 52.33ms. Allocated memory is still 142.6MB. Free memory was 92.9MB in the beginning and 90.6MB in the end (delta: 2.3MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-09 07:34:10,363 INFO L158 Benchmark]: IcfgBuilder took 562.10ms. Allocated memory is still 142.6MB. Free memory was 90.6MB in the beginning and 60.2MB in the end (delta: 30.4MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2025-03-09 07:34:10,363 INFO L158 Benchmark]: BuchiAutomizer took 3572.10ms. Allocated memory was 142.6MB in the beginning and 285.2MB in the end (delta: 142.6MB). Free memory was 60.2MB in the beginning and 205.3MB in the end (delta: -145.1MB). Peak memory consumption was 5.0MB. Max. memory is 16.1GB. [2025-03-09 07:34:10,363 INFO L158 Benchmark]: Witness Printer took 54.40ms. Allocated memory is still 285.2MB. Free memory was 205.3MB in the beginning and 199.8MB in the end (delta: 5.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-09 07:34:10,365 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.23ms. Allocated memory is still 201.3MB. Free memory is still 125.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 217.77ms. Allocated memory is still 142.6MB. Free memory was 109.5MB in the beginning and 95.2MB in the end (delta: 14.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 38.87ms. Allocated memory is still 142.6MB. Free memory was 95.2MB in the beginning and 92.9MB in the end (delta: 2.3MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 52.33ms. Allocated memory is still 142.6MB. Free memory was 92.9MB in the beginning and 90.6MB in the end (delta: 2.3MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 562.10ms. Allocated memory is still 142.6MB. Free memory was 90.6MB in the beginning and 60.2MB in the end (delta: 30.4MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 3572.10ms. Allocated memory was 142.6MB in the beginning and 285.2MB in the end (delta: 142.6MB). Free memory was 60.2MB in the beginning and 205.3MB in the end (delta: -145.1MB). Peak memory consumption was 5.0MB. Max. memory is 16.1GB. * Witness Printer took 54.40ms. Allocated memory is still 285.2MB. Free memory was 205.3MB in the beginning and 199.8MB in the end (delta: 5.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 13 terminating modules (13 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.13 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6772 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.4s and 14 iterations. TraceHistogramMax:1. Analysis of lassos took 1.9s. Construction of modules took 0.3s. Büchi inclusion checks took 1.0s. Highest rank in rank-based complementation 0. Minimization of det autom 13. Minimization of nondet autom 0. Automata minimization 0.4s AutomataMinimizationTime, 13 MinimizatonAttempts, 686 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2919 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2919 mSDsluCounter, 7010 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3862 mSDsCounter, 119 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 373 IncrementalHoareTripleChecker+Invalid, 492 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 119 mSolverCounterUnsat, 3148 mSDtfsCounter, 373 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc2 concLT0 SILN0 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 359]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L195] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L197] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L287] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L289] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 359]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L195] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L197] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L287] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L289] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-03-09 07:34:10,383 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)