./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/seq-mthreaded/pals_lcr.6.ufo.UNBOUNDED.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e2fb8bed Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/seq-mthreaded/pals_lcr.6.ufo.UNBOUNDED.pals.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 71881827e42af7e93d8d7789f21cf70c42c80b5b7128690239afcf02ba9daf37 --- Real Ultimate output --- This is Ultimate 0.3.0-?-e2fb8be-m [2025-03-09 07:41:58,776 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-09 07:41:58,825 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-09 07:41:58,828 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-09 07:41:58,829 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-09 07:41:58,829 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-09 07:41:58,848 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-09 07:41:58,849 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-09 07:41:58,849 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-09 07:41:58,849 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-09 07:41:58,849 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-09 07:41:58,850 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-09 07:41:58,850 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-09 07:41:58,850 INFO L153 SettingsManager]: * Use SBE=true [2025-03-09 07:41:58,850 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-09 07:41:58,850 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-09 07:41:58,850 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-09 07:41:58,850 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-09 07:41:58,850 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-09 07:41:58,850 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-09 07:41:58,851 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-09 07:41:58,851 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-09 07:41:58,851 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-09 07:41:58,852 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-09 07:41:58,852 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-09 07:41:58,852 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-09 07:41:58,852 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-09 07:41:58,852 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 71881827e42af7e93d8d7789f21cf70c42c80b5b7128690239afcf02ba9daf37 [2025-03-09 07:41:59,187 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-09 07:41:59,195 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-09 07:41:59,197 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-09 07:41:59,198 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-09 07:41:59,198 INFO L274 PluginConnector]: CDTParser initialized [2025-03-09 07:41:59,199 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/seq-mthreaded/pals_lcr.6.ufo.UNBOUNDED.pals.c [2025-03-09 07:42:00,316 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5e79fb373/da76886f298c46069f46b92a80c569ab/FLAGcdf623531 [2025-03-09 07:42:00,599 INFO L384 CDTParser]: Found 1 translation units. [2025-03-09 07:42:00,599 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_lcr.6.ufo.UNBOUNDED.pals.c [2025-03-09 07:42:00,609 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5e79fb373/da76886f298c46069f46b92a80c569ab/FLAGcdf623531 [2025-03-09 07:42:00,879 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5e79fb373/da76886f298c46069f46b92a80c569ab [2025-03-09 07:42:00,881 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-09 07:42:00,882 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-09 07:42:00,883 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-09 07:42:00,883 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-09 07:42:00,886 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-09 07:42:00,886 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 07:42:00" (1/1) ... [2025-03-09 07:42:00,887 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7b88f9b0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:00, skipping insertion in model container [2025-03-09 07:42:00,887 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 07:42:00" (1/1) ... [2025-03-09 07:42:00,907 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-09 07:42:01,078 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 07:42:01,089 INFO L200 MainTranslator]: Completed pre-run [2025-03-09 07:42:01,134 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 07:42:01,147 INFO L204 MainTranslator]: Completed translation [2025-03-09 07:42:01,148 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01 WrapperNode [2025-03-09 07:42:01,148 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-09 07:42:01,149 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-09 07:42:01,150 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-09 07:42:01,150 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-09 07:42:01,156 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01" (1/1) ... [2025-03-09 07:42:01,167 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01" (1/1) ... [2025-03-09 07:42:01,203 INFO L138 Inliner]: procedures = 26, calls = 18, calls flagged for inlining = 13, calls inlined = 13, statements flattened = 374 [2025-03-09 07:42:01,204 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-09 07:42:01,204 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-09 07:42:01,204 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-09 07:42:01,204 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-09 07:42:01,210 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01" (1/1) ... [2025-03-09 07:42:01,211 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01" (1/1) ... [2025-03-09 07:42:01,216 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01" (1/1) ... [2025-03-09 07:42:01,228 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-09 07:42:01,228 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01" (1/1) ... [2025-03-09 07:42:01,228 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01" (1/1) ... [2025-03-09 07:42:01,235 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01" (1/1) ... [2025-03-09 07:42:01,238 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01" (1/1) ... [2025-03-09 07:42:01,239 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01" (1/1) ... [2025-03-09 07:42:01,240 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01" (1/1) ... [2025-03-09 07:42:01,243 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-09 07:42:01,244 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-09 07:42:01,244 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-09 07:42:01,244 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-09 07:42:01,245 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01" (1/1) ... [2025-03-09 07:42:01,249 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 07:42:01,257 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 07:42:01,271 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 07:42:01,276 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-09 07:42:01,292 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-09 07:42:01,292 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-09 07:42:01,292 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-09 07:42:01,292 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-09 07:42:01,372 INFO L256 CfgBuilder]: Building ICFG [2025-03-09 07:42:01,374 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-09 07:42:01,760 INFO L? ?]: Removed 45 outVars from TransFormulas that were not future-live. [2025-03-09 07:42:01,760 INFO L307 CfgBuilder]: Performing block encoding [2025-03-09 07:42:01,770 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-09 07:42:01,772 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-09 07:42:01,772 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:42:01 BoogieIcfgContainer [2025-03-09 07:42:01,772 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-09 07:42:01,773 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-09 07:42:01,773 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-09 07:42:01,777 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-09 07:42:01,778 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:42:01,778 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.03 07:42:00" (1/3) ... [2025-03-09 07:42:01,779 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@64737edf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 07:42:01, skipping insertion in model container [2025-03-09 07:42:01,779 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:42:01,779 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:42:01" (2/3) ... [2025-03-09 07:42:01,779 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@64737edf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 07:42:01, skipping insertion in model container [2025-03-09 07:42:01,779 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:42:01,779 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:42:01" (3/3) ... [2025-03-09 07:42:01,781 INFO L363 chiAutomizerObserver]: Analyzing ICFG pals_lcr.6.ufo.UNBOUNDED.pals.c [2025-03-09 07:42:01,822 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-09 07:42:01,822 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-09 07:42:01,822 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-09 07:42:01,822 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-09 07:42:01,822 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-09 07:42:01,823 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-09 07:42:01,823 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-09 07:42:01,823 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-09 07:42:01,828 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 99 states, 98 states have (on average 1.7448979591836735) internal successors, (171), 98 states have internal predecessors, (171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:42:01,845 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 50 [2025-03-09 07:42:01,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:42:01,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:42:01,851 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:42:01,852 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:42:01,852 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-09 07:42:01,853 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 99 states, 98 states have (on average 1.7448979591836735) internal successors, (171), 98 states have internal predecessors, (171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:42:01,857 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 50 [2025-03-09 07:42:01,857 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:42:01,857 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:42:01,857 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:42:01,857 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:42:01,862 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(32, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~ret29#1, main_#t~ret30#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;~id2~0 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~st2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~send2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;assume 0 == main_#t~nondet12#1 || 1 == main_#t~nondet12#1;~mode2~0 := (if 0 == main_#t~nondet12#1 % 256 then 0 else 1);havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;~id3~0 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;~st3~0 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~send3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;assume 0 == main_#t~nondet16#1 || 1 == main_#t~nondet16#1;~mode3~0 := (if 0 == main_#t~nondet16#1 % 256 then 0 else 1);havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~id4~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;~st4~0 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;~send4~0 := main_#t~nondet19#1;havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;assume 0 == main_#t~nondet20#1 || 1 == main_#t~nondet20#1;~mode4~0 := (if 0 == main_#t~nondet20#1 % 256 then 0 else 1);havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~id5~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~st5~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;~send5~0 := main_#t~nondet23#1;havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~mode5~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id6~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st6~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send6~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode6~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1;" "assume !(0 == (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296));init_~tmp~0#1 := 0;" "init_#res#1 := init_~tmp~0#1;" "main_#t~ret29#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret29#1;havoc main_#t~ret29#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;main_~i2~0#1 := 0;" [2025-03-09 07:42:01,863 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0;" "assume !(0 != ~mode1~0 % 256);~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256);~mode1~0 := 1;" "havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0;" "assume !(0 != ~mode2~0 % 256);~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256);~mode2~0 := 1;" "havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0;" "assume !(0 != ~mode3~0 % 256);~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256);~mode3~0 := 1;" "havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0;" "assume !(0 != ~mode4~0 % 256);~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256);~mode4~0 := 1;" "havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0;" "assume !(0 != ~mode5~0 % 256);~p5_new~0 := (if (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 <= 127 then (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 else (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 - 256);~mode5~0 := 1;" "havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0;" "assume !(0 != ~mode6~0 % 256);~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256);~mode6~0 := 1;" "havoc node6_~m6~0#1;assume { :end_inline_node6 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1;" "assume !(~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 <= 1);check_~tmp~1#1 := 0;" "check_#res#1 := check_~tmp~1#1;" "main_#t~ret30#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret30#1;havoc main_#t~ret30#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1;" "assume !(0 == assert_~arg#1 % 256);" "havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true;" [2025-03-09 07:42:01,866 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:42:01,867 INFO L85 PathProgramCache]: Analyzing trace with hash -1636242708, now seen corresponding path program 1 times [2025-03-09 07:42:01,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:42:01,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482763246] [2025-03-09 07:42:01,875 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:42:01,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:42:01,926 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-03-09 07:42:01,961 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-03-09 07:42:01,962 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:42:01,962 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:42:02,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:42:02,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:42:02,175 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [482763246] [2025-03-09 07:42:02,175 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [482763246] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:42:02,175 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:42:02,175 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:42:02,176 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1295978408] [2025-03-09 07:42:02,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:42:02,179 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:42:02,179 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:42:02,179 INFO L85 PathProgramCache]: Analyzing trace with hash 604470290, now seen corresponding path program 1 times [2025-03-09 07:42:02,179 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:42:02,179 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [50301179] [2025-03-09 07:42:02,179 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:42:02,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:42:02,186 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 18 statements into 1 equivalence classes. [2025-03-09 07:42:02,240 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 18 of 18 statements. [2025-03-09 07:42:02,241 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:42:02,241 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:42:02,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:42:02,463 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:42:02,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [50301179] [2025-03-09 07:42:02,464 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [50301179] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:42:02,464 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:42:02,464 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:42:02,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1163583479] [2025-03-09 07:42:02,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:42:02,465 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:42:02,466 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:42:02,482 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-09 07:42:02,482 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-09 07:42:02,485 INFO L87 Difference]: Start difference. First operand has 99 states, 98 states have (on average 1.7448979591836735) internal successors, (171), 98 states have internal predecessors, (171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:42:02,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:42:02,580 INFO L93 Difference]: Finished difference Result 98 states and 167 transitions. [2025-03-09 07:42:02,581 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98 states and 167 transitions. [2025-03-09 07:42:02,586 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 48 [2025-03-09 07:42:02,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98 states to 94 states and 124 transitions. [2025-03-09 07:42:02,592 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 94 [2025-03-09 07:42:02,593 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 94 [2025-03-09 07:42:02,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94 states and 124 transitions. [2025-03-09 07:42:02,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:42:02,593 INFO L218 hiAutomatonCegarLoop]: Abstraction has 94 states and 124 transitions. [2025-03-09 07:42:02,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states and 124 transitions. [2025-03-09 07:42:02,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 94. [2025-03-09 07:42:02,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 94 states, 94 states have (on average 1.3191489361702127) internal successors, (124), 93 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:42:02,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 124 transitions. [2025-03-09 07:42:02,612 INFO L240 hiAutomatonCegarLoop]: Abstraction has 94 states and 124 transitions. [2025-03-09 07:42:02,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-09 07:42:02,616 INFO L432 stractBuchiCegarLoop]: Abstraction has 94 states and 124 transitions. [2025-03-09 07:42:02,616 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-09 07:42:02,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94 states and 124 transitions. [2025-03-09 07:42:02,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 48 [2025-03-09 07:42:02,620 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:42:02,620 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:42:02,621 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:42:02,621 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:42:02,622 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(32, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~ret29#1, main_#t~ret30#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;~id2~0 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~st2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~send2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;assume 0 == main_#t~nondet12#1 || 1 == main_#t~nondet12#1;~mode2~0 := (if 0 == main_#t~nondet12#1 % 256 then 0 else 1);havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;~id3~0 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;~st3~0 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~send3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;assume 0 == main_#t~nondet16#1 || 1 == main_#t~nondet16#1;~mode3~0 := (if 0 == main_#t~nondet16#1 % 256 then 0 else 1);havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~id4~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;~st4~0 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;~send4~0 := main_#t~nondet19#1;havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;assume 0 == main_#t~nondet20#1 || 1 == main_#t~nondet20#1;~mode4~0 := (if 0 == main_#t~nondet20#1 % 256 then 0 else 1);havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~id5~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~st5~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;~send5~0 := main_#t~nondet23#1;havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~mode5~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id6~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st6~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send6~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode6~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1;" "assume 0 == (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296);" "assume ~id1~0 >= 0;" "assume 0 == ~st1~0;" "assume ~send1~0 == ~id1~0;" "assume 0 == (if ~mode1~0 % 256 % 4294967296 <= 2147483647 then ~mode1~0 % 256 % 4294967296 else ~mode1~0 % 256 % 4294967296 - 4294967296);" "assume ~id2~0 >= 0;" "assume 0 == ~st2~0;" "assume ~send2~0 == ~id2~0;" "assume 0 == (if ~mode2~0 % 256 % 4294967296 <= 2147483647 then ~mode2~0 % 256 % 4294967296 else ~mode2~0 % 256 % 4294967296 - 4294967296);" "assume ~id3~0 >= 0;" "assume 0 == ~st3~0;" "assume ~send3~0 == ~id3~0;" "assume 0 == (if ~mode3~0 % 256 % 4294967296 <= 2147483647 then ~mode3~0 % 256 % 4294967296 else ~mode3~0 % 256 % 4294967296 - 4294967296);" "assume ~id4~0 >= 0;" "assume 0 == ~st4~0;" "assume ~send4~0 == ~id4~0;" "assume 0 == (if ~mode4~0 % 256 % 4294967296 <= 2147483647 then ~mode4~0 % 256 % 4294967296 else ~mode4~0 % 256 % 4294967296 - 4294967296);" "assume ~id5~0 >= 0;" "assume 0 == ~st5~0;" "assume ~send5~0 == ~id5~0;" "assume 0 == (if ~mode5~0 % 256 % 4294967296 <= 2147483647 then ~mode5~0 % 256 % 4294967296 else ~mode5~0 % 256 % 4294967296 - 4294967296);" "assume ~id6~0 >= 0;" "assume 0 == ~st6~0;" "assume ~send6~0 == ~id6~0;" "assume 0 == (if ~mode6~0 % 256 % 4294967296 <= 2147483647 then ~mode6~0 % 256 % 4294967296 else ~mode6~0 % 256 % 4294967296 - 4294967296);" "assume ~id1~0 != ~id2~0;" "assume ~id1~0 != ~id3~0;" "assume ~id1~0 != ~id4~0;" "assume ~id1~0 != ~id5~0;" "assume ~id1~0 != ~id6~0;" "assume ~id2~0 != ~id3~0;" "assume ~id2~0 != ~id4~0;" "assume ~id2~0 != ~id5~0;" "assume ~id2~0 != ~id6~0;" "assume ~id3~0 != ~id4~0;" "assume ~id3~0 != ~id5~0;" "assume ~id3~0 != ~id6~0;" "assume ~id4~0 != ~id5~0;" "assume ~id4~0 != ~id6~0;" "assume ~id5~0 != ~id6~0;init_~tmp~0#1 := 1;" "init_#res#1 := init_~tmp~0#1;" "main_#t~ret29#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret29#1;havoc main_#t~ret29#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;main_~i2~0#1 := 0;" [2025-03-09 07:42:02,622 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0;" "assume !(0 != ~mode1~0 % 256);~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256);~mode1~0 := 1;" "havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0;" "assume !(0 != ~mode2~0 % 256);~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256);~mode2~0 := 1;" "havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0;" "assume !(0 != ~mode3~0 % 256);~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256);~mode3~0 := 1;" "havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0;" "assume !(0 != ~mode4~0 % 256);~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256);~mode4~0 := 1;" "havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0;" "assume !(0 != ~mode5~0 % 256);~p5_new~0 := (if (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 <= 127 then (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 else (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 - 256);~mode5~0 := 1;" "havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0;" "assume !(0 != ~mode6~0 % 256);~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256);~mode6~0 := 1;" "havoc node6_~m6~0#1;assume { :end_inline_node6 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1;" "assume !(~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 <= 1);check_~tmp~1#1 := 0;" "check_#res#1 := check_~tmp~1#1;" "main_#t~ret30#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret30#1;havoc main_#t~ret30#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1;" "assume !(0 == assert_~arg#1 % 256);" "havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true;" [2025-03-09 07:42:02,622 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:42:02,622 INFO L85 PathProgramCache]: Analyzing trace with hash -1011627693, now seen corresponding path program 1 times [2025-03-09 07:42:02,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:42:02,622 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757063559] [2025-03-09 07:42:02,622 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:42:02,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:42:02,635 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 46 statements into 1 equivalence classes. [2025-03-09 07:42:02,663 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 46 of 46 statements. [2025-03-09 07:42:02,664 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:42:02,664 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:42:02,664 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:42:02,671 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 46 statements into 1 equivalence classes. [2025-03-09 07:42:02,685 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 46 of 46 statements. [2025-03-09 07:42:02,685 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:42:02,685 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:42:02,714 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:42:02,716 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:42:02,716 INFO L85 PathProgramCache]: Analyzing trace with hash 604470290, now seen corresponding path program 2 times [2025-03-09 07:42:02,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:42:02,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753128118] [2025-03-09 07:42:02,716 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:42:02,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:42:02,725 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 18 statements into 1 equivalence classes. [2025-03-09 07:42:02,766 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 18 of 18 statements. [2025-03-09 07:42:02,766 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:42:02,767 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:42:02,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:42:02,917 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:42:02,917 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753128118] [2025-03-09 07:42:02,918 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1753128118] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:42:02,918 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:42:02,918 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:42:02,918 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [621155666] [2025-03-09 07:42:02,918 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:42:02,918 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:42:02,918 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:42:02,918 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-09 07:42:02,918 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-09 07:42:02,919 INFO L87 Difference]: Start difference. First operand 94 states and 124 transitions. cyclomatic complexity: 31 Second operand has 5 states, 5 states have (on average 3.6) internal successors, (18), 5 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:42:02,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:42:02,946 INFO L93 Difference]: Finished difference Result 97 states and 126 transitions. [2025-03-09 07:42:02,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 126 transitions. [2025-03-09 07:42:02,947 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 48 [2025-03-09 07:42:02,950 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 94 states and 121 transitions. [2025-03-09 07:42:02,950 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 94 [2025-03-09 07:42:02,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 94 [2025-03-09 07:42:02,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94 states and 121 transitions. [2025-03-09 07:42:02,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:42:02,951 INFO L218 hiAutomatonCegarLoop]: Abstraction has 94 states and 121 transitions. [2025-03-09 07:42:02,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states and 121 transitions. [2025-03-09 07:42:02,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 94. [2025-03-09 07:42:02,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 94 states, 94 states have (on average 1.2872340425531914) internal successors, (121), 93 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:42:02,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 121 transitions. [2025-03-09 07:42:02,953 INFO L240 hiAutomatonCegarLoop]: Abstraction has 94 states and 121 transitions. [2025-03-09 07:42:02,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-09 07:42:02,954 INFO L432 stractBuchiCegarLoop]: Abstraction has 94 states and 121 transitions. [2025-03-09 07:42:02,954 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-09 07:42:02,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94 states and 121 transitions. [2025-03-09 07:42:02,955 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 48 [2025-03-09 07:42:02,955 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:42:02,955 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:42:02,956 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:42:02,957 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:42:02,957 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(32, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~ret29#1, main_#t~ret30#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;~id2~0 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~st2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~send2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;assume 0 == main_#t~nondet12#1 || 1 == main_#t~nondet12#1;~mode2~0 := (if 0 == main_#t~nondet12#1 % 256 then 0 else 1);havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;~id3~0 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;~st3~0 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~send3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;assume 0 == main_#t~nondet16#1 || 1 == main_#t~nondet16#1;~mode3~0 := (if 0 == main_#t~nondet16#1 % 256 then 0 else 1);havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~id4~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;~st4~0 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;~send4~0 := main_#t~nondet19#1;havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;assume 0 == main_#t~nondet20#1 || 1 == main_#t~nondet20#1;~mode4~0 := (if 0 == main_#t~nondet20#1 % 256 then 0 else 1);havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~id5~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~st5~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;~send5~0 := main_#t~nondet23#1;havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~mode5~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id6~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st6~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send6~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode6~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1;" "assume 0 == (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296);" "assume ~id1~0 >= 0;" "assume 0 == ~st1~0;" "assume ~send1~0 == ~id1~0;" "assume 0 == (if ~mode1~0 % 256 % 4294967296 <= 2147483647 then ~mode1~0 % 256 % 4294967296 else ~mode1~0 % 256 % 4294967296 - 4294967296);" "assume ~id2~0 >= 0;" "assume 0 == ~st2~0;" "assume ~send2~0 == ~id2~0;" "assume 0 == (if ~mode2~0 % 256 % 4294967296 <= 2147483647 then ~mode2~0 % 256 % 4294967296 else ~mode2~0 % 256 % 4294967296 - 4294967296);" "assume ~id3~0 >= 0;" "assume 0 == ~st3~0;" "assume ~send3~0 == ~id3~0;" "assume 0 == (if ~mode3~0 % 256 % 4294967296 <= 2147483647 then ~mode3~0 % 256 % 4294967296 else ~mode3~0 % 256 % 4294967296 - 4294967296);" "assume ~id4~0 >= 0;" "assume 0 == ~st4~0;" "assume ~send4~0 == ~id4~0;" "assume 0 == (if ~mode4~0 % 256 % 4294967296 <= 2147483647 then ~mode4~0 % 256 % 4294967296 else ~mode4~0 % 256 % 4294967296 - 4294967296);" "assume ~id5~0 >= 0;" "assume 0 == ~st5~0;" "assume ~send5~0 == ~id5~0;" "assume 0 == (if ~mode5~0 % 256 % 4294967296 <= 2147483647 then ~mode5~0 % 256 % 4294967296 else ~mode5~0 % 256 % 4294967296 - 4294967296);" "assume ~id6~0 >= 0;" "assume 0 == ~st6~0;" "assume ~send6~0 == ~id6~0;" "assume 0 == (if ~mode6~0 % 256 % 4294967296 <= 2147483647 then ~mode6~0 % 256 % 4294967296 else ~mode6~0 % 256 % 4294967296 - 4294967296);" "assume ~id1~0 != ~id2~0;" "assume ~id1~0 != ~id3~0;" "assume ~id1~0 != ~id4~0;" "assume ~id1~0 != ~id5~0;" "assume ~id1~0 != ~id6~0;" "assume ~id2~0 != ~id3~0;" "assume ~id2~0 != ~id4~0;" "assume ~id2~0 != ~id5~0;" "assume ~id2~0 != ~id6~0;" "assume ~id3~0 != ~id4~0;" "assume ~id3~0 != ~id5~0;" "assume ~id3~0 != ~id6~0;" "assume ~id4~0 != ~id5~0;" "assume ~id4~0 != ~id6~0;" "assume ~id5~0 != ~id6~0;init_~tmp~0#1 := 1;" "init_#res#1 := init_~tmp~0#1;" "main_#t~ret29#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret29#1;havoc main_#t~ret29#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;main_~i2~0#1 := 0;" [2025-03-09 07:42:02,957 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0;" "assume !(0 != ~mode1~0 % 256);~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256);~mode1~0 := 1;" "havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0;" "assume !(0 != ~mode2~0 % 256);~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256);~mode2~0 := 1;" "havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0;" "assume !(0 != ~mode3~0 % 256);~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256);~mode3~0 := 1;" "havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0;" "assume !(0 != ~mode4~0 % 256);~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256);~mode4~0 := 1;" "havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0;" "assume !(0 != ~mode5~0 % 256);~p5_new~0 := (if (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 <= 127 then (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 else (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 - 256);~mode5~0 := 1;" "havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0;" "assume !(0 != ~mode6~0 % 256);~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256);~mode6~0 := 1;" "havoc node6_~m6~0#1;assume { :end_inline_node6 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1;" "assume ~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 <= 1;" "assume (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296) >= 6;" "assume (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296) < 6;check_~tmp~1#1 := 1;" "check_#res#1 := check_~tmp~1#1;" "main_#t~ret30#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret30#1;havoc main_#t~ret30#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1;" "assume !(0 == assert_~arg#1 % 256);" "havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true;" [2025-03-09 07:42:02,958 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:42:02,958 INFO L85 PathProgramCache]: Analyzing trace with hash -1011627693, now seen corresponding path program 2 times [2025-03-09 07:42:02,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:42:02,959 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1413795514] [2025-03-09 07:42:02,959 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:42:02,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:42:02,966 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 46 statements into 1 equivalence classes. [2025-03-09 07:42:02,986 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 46 of 46 statements. [2025-03-09 07:42:02,989 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:42:02,989 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:42:02,989 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:42:02,992 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 46 statements into 1 equivalence classes. [2025-03-09 07:42:03,008 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 46 of 46 statements. [2025-03-09 07:42:03,008 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:42:03,008 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:42:03,018 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:42:03,019 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:42:03,019 INFO L85 PathProgramCache]: Analyzing trace with hash -2099278195, now seen corresponding path program 1 times [2025-03-09 07:42:03,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:42:03,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109317313] [2025-03-09 07:42:03,019 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:42:03,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:42:03,025 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-03-09 07:42:03,031 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-03-09 07:42:03,032 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:42:03,032 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:42:03,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:42:03,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:42:03,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [109317313] [2025-03-09 07:42:03,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [109317313] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:42:03,056 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:42:03,056 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:42:03,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953154198] [2025-03-09 07:42:03,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:42:03,056 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:42:03,056 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:42:03,057 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:42:03,057 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:42:03,057 INFO L87 Difference]: Start difference. First operand 94 states and 121 transitions. cyclomatic complexity: 28 Second operand has 3 states, 3 states have (on average 6.666666666666667) internal successors, (20), 3 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:42:03,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:42:03,088 INFO L93 Difference]: Finished difference Result 136 states and 185 transitions. [2025-03-09 07:42:03,088 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 136 states and 185 transitions. [2025-03-09 07:42:03,089 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 90 [2025-03-09 07:42:03,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 136 states to 136 states and 185 transitions. [2025-03-09 07:42:03,090 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 136 [2025-03-09 07:42:03,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 136 [2025-03-09 07:42:03,090 INFO L73 IsDeterministic]: Start isDeterministic. Operand 136 states and 185 transitions. [2025-03-09 07:42:03,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:42:03,091 INFO L218 hiAutomatonCegarLoop]: Abstraction has 136 states and 185 transitions. [2025-03-09 07:42:03,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states and 185 transitions. [2025-03-09 07:42:03,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 134. [2025-03-09 07:42:03,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134 states, 134 states have (on average 1.3582089552238805) internal successors, (182), 133 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:42:03,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 182 transitions. [2025-03-09 07:42:03,100 INFO L240 hiAutomatonCegarLoop]: Abstraction has 134 states and 182 transitions. [2025-03-09 07:42:03,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:42:03,103 INFO L432 stractBuchiCegarLoop]: Abstraction has 134 states and 182 transitions. [2025-03-09 07:42:03,103 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-09 07:42:03,103 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134 states and 182 transitions. [2025-03-09 07:42:03,104 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 88 [2025-03-09 07:42:03,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:42:03,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:42:03,105 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:42:03,105 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:42:03,105 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(32, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~ret29#1, main_#t~ret30#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;~id2~0 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~st2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~send2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;assume 0 == main_#t~nondet12#1 || 1 == main_#t~nondet12#1;~mode2~0 := (if 0 == main_#t~nondet12#1 % 256 then 0 else 1);havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;~id3~0 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;~st3~0 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~send3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;assume 0 == main_#t~nondet16#1 || 1 == main_#t~nondet16#1;~mode3~0 := (if 0 == main_#t~nondet16#1 % 256 then 0 else 1);havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~id4~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;~st4~0 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;~send4~0 := main_#t~nondet19#1;havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;assume 0 == main_#t~nondet20#1 || 1 == main_#t~nondet20#1;~mode4~0 := (if 0 == main_#t~nondet20#1 % 256 then 0 else 1);havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~id5~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~st5~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;~send5~0 := main_#t~nondet23#1;havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~mode5~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id6~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st6~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send6~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode6~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1;" "assume 0 == (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296);" "assume ~id1~0 >= 0;" "assume 0 == ~st1~0;" "assume ~send1~0 == ~id1~0;" "assume 0 == (if ~mode1~0 % 256 % 4294967296 <= 2147483647 then ~mode1~0 % 256 % 4294967296 else ~mode1~0 % 256 % 4294967296 - 4294967296);" "assume ~id2~0 >= 0;" "assume 0 == ~st2~0;" "assume ~send2~0 == ~id2~0;" "assume 0 == (if ~mode2~0 % 256 % 4294967296 <= 2147483647 then ~mode2~0 % 256 % 4294967296 else ~mode2~0 % 256 % 4294967296 - 4294967296);" "assume ~id3~0 >= 0;" "assume 0 == ~st3~0;" "assume ~send3~0 == ~id3~0;" "assume 0 == (if ~mode3~0 % 256 % 4294967296 <= 2147483647 then ~mode3~0 % 256 % 4294967296 else ~mode3~0 % 256 % 4294967296 - 4294967296);" "assume ~id4~0 >= 0;" "assume 0 == ~st4~0;" "assume ~send4~0 == ~id4~0;" "assume 0 == (if ~mode4~0 % 256 % 4294967296 <= 2147483647 then ~mode4~0 % 256 % 4294967296 else ~mode4~0 % 256 % 4294967296 - 4294967296);" "assume ~id5~0 >= 0;" "assume 0 == ~st5~0;" "assume ~send5~0 == ~id5~0;" "assume 0 == (if ~mode5~0 % 256 % 4294967296 <= 2147483647 then ~mode5~0 % 256 % 4294967296 else ~mode5~0 % 256 % 4294967296 - 4294967296);" "assume ~id6~0 >= 0;" "assume 0 == ~st6~0;" "assume ~send6~0 == ~id6~0;" "assume 0 == (if ~mode6~0 % 256 % 4294967296 <= 2147483647 then ~mode6~0 % 256 % 4294967296 else ~mode6~0 % 256 % 4294967296 - 4294967296);" "assume ~id1~0 != ~id2~0;" "assume ~id1~0 != ~id3~0;" "assume ~id1~0 != ~id4~0;" "assume ~id1~0 != ~id5~0;" "assume ~id1~0 != ~id6~0;" "assume ~id2~0 != ~id3~0;" "assume ~id2~0 != ~id4~0;" "assume ~id2~0 != ~id5~0;" "assume ~id2~0 != ~id6~0;" "assume ~id3~0 != ~id4~0;" "assume ~id3~0 != ~id5~0;" "assume ~id3~0 != ~id6~0;" "assume ~id4~0 != ~id5~0;" "assume ~id4~0 != ~id6~0;" "assume ~id5~0 != ~id6~0;init_~tmp~0#1 := 1;" "init_#res#1 := init_~tmp~0#1;" "main_#t~ret29#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret29#1;havoc main_#t~ret29#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;main_~i2~0#1 := 0;" [2025-03-09 07:42:03,105 INFO L754 eck$LassoCheckResult]: Loop: "assume true;assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0;" "assume !(0 != ~mode1~0 % 256);~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256);~mode1~0 := 1;" "havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0;" "assume !(0 != ~mode2~0 % 256);~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256);~mode2~0 := 1;" "havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0;" "assume !(0 != ~mode3~0 % 256);~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256);~mode3~0 := 1;" "havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0;" "assume !(0 != ~mode4~0 % 256);~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256);~mode4~0 := 1;" "havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0;" "assume !(0 != ~mode5~0 % 256);~p5_new~0 := (if (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 <= 127 then (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 else (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 - 256);~mode5~0 := 1;" "havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0;" "assume !(0 != ~mode6~0 % 256);~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256);~mode6~0 := 1;" "havoc node6_~m6~0#1;assume { :end_inline_node6 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1;" "assume ~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 <= 1;" "assume !((if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296) >= 6);" "assume 0 == ~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0;" "assume (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296) < 6;check_~tmp~1#1 := 1;" "check_#res#1 := check_~tmp~1#1;" "main_#t~ret30#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret30#1;havoc main_#t~ret30#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1;" "assume !(0 == assert_~arg#1 % 256);" "havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true;" [2025-03-09 07:42:03,108 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:42:03,108 INFO L85 PathProgramCache]: Analyzing trace with hash -1011627693, now seen corresponding path program 3 times [2025-03-09 07:42:03,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:42:03,108 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [130447316] [2025-03-09 07:42:03,108 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 07:42:03,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:42:03,121 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 46 statements into 1 equivalence classes. [2025-03-09 07:42:03,143 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 46 of 46 statements. [2025-03-09 07:42:03,144 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 07:42:03,144 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:42:03,144 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:42:03,147 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 46 statements into 1 equivalence classes. [2025-03-09 07:42:03,174 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 46 of 46 statements. [2025-03-09 07:42:03,175 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:42:03,175 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:42:03,182 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:42:03,183 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:42:03,183 INFO L85 PathProgramCache]: Analyzing trace with hash 379442543, now seen corresponding path program 1 times [2025-03-09 07:42:03,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:42:03,183 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901715014] [2025-03-09 07:42:03,183 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:42:03,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:42:03,192 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-09 07:42:03,208 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-09 07:42:03,208 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:42:03,208 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:42:03,208 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:42:03,210 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-09 07:42:03,226 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-09 07:42:03,227 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:42:03,227 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:42:03,230 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:42:03,234 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:42:03,235 INFO L85 PathProgramCache]: Analyzing trace with hash -953715875, now seen corresponding path program 1 times [2025-03-09 07:42:03,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:42:03,235 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552176574] [2025-03-09 07:42:03,235 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:42:03,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:42:03,249 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-03-09 07:42:03,274 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-03-09 07:42:03,274 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:42:03,274 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:42:03,274 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:42:03,279 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-03-09 07:42:03,302 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-03-09 07:42:03,302 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:42:03,302 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:42:03,316 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:42:06,254 INFO L204 LassoAnalysis]: Preferences: [2025-03-09 07:42:06,255 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-09 07:42:06,255 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-09 07:42:06,255 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-09 07:42:06,255 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2025-03-09 07:42:06,255 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 07:42:06,256 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-09 07:42:06,256 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-09 07:42:06,256 INFO L132 ssoRankerPreferences]: Filename of dumped script: pals_lcr.6.ufo.UNBOUNDED.pals.c_Iteration4_Loop [2025-03-09 07:42:06,256 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-09 07:42:06,256 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-09 07:42:06,287 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:06,296 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:06,305 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:06,306 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:06,308 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:06,310 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:06,311 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:06,313 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:06,314 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:06,318 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:06,319 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:06,321 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:07,731 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:07,736 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:07,740 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:07,744 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:07,747 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:07,749 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:07,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:07,752 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 07:42:09,202 WARN L137 XnfTransformerHelper]: expecting exponential blowup for input size 36