./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e2fb8bed Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- This is Ultimate 0.3.0-?-e2fb8be-m [2025-03-09 06:57:01,177 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-09 06:57:01,231 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-09 06:57:01,236 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-09 06:57:01,237 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-09 06:57:01,237 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-09 06:57:01,256 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-09 06:57:01,257 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-09 06:57:01,257 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-09 06:57:01,257 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-09 06:57:01,257 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-09 06:57:01,257 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-09 06:57:01,258 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-09 06:57:01,258 INFO L153 SettingsManager]: * Use SBE=true [2025-03-09 06:57:01,258 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-09 06:57:01,258 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-09 06:57:01,258 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-09 06:57:01,259 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-09 06:57:01,259 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-09 06:57:01,259 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-09 06:57:01,259 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-09 06:57:01,259 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-09 06:57:01,259 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-09 06:57:01,259 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-09 06:57:01,259 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-09 06:57:01,259 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-09 06:57:01,260 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-09 06:57:01,260 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-09 06:57:01,260 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-09 06:57:01,261 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-09 06:57:01,261 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-09 06:57:01,261 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-09 06:57:01,261 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-09 06:57:01,261 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-09 06:57:01,261 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-09 06:57:01,261 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-09 06:57:01,261 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-09 06:57:01,261 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-09 06:57:01,261 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-09 06:57:01,262 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-09 06:57:01,262 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2025-03-09 06:57:01,494 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-09 06:57:01,504 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-09 06:57:01,505 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-09 06:57:01,506 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-09 06:57:01,506 INFO L274 PluginConnector]: CDTParser initialized [2025-03-09 06:57:01,511 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2025-03-09 06:57:02,593 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/17e93ee74/f96e049647c544329f7ba69216a6c704/FLAG65c3b6d96 [2025-03-09 06:57:02,801 INFO L384 CDTParser]: Found 1 translation units. [2025-03-09 06:57:02,801 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2025-03-09 06:57:02,806 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/17e93ee74/f96e049647c544329f7ba69216a6c704/FLAG65c3b6d96 [2025-03-09 06:57:03,160 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/17e93ee74/f96e049647c544329f7ba69216a6c704 [2025-03-09 06:57:03,162 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-09 06:57:03,163 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-09 06:57:03,164 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-09 06:57:03,164 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-09 06:57:03,167 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-09 06:57:03,167 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,168 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5c6c8179 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03, skipping insertion in model container [2025-03-09 06:57:03,168 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,179 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-09 06:57:03,294 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 06:57:03,303 INFO L200 MainTranslator]: Completed pre-run [2025-03-09 06:57:03,319 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 06:57:03,332 INFO L204 MainTranslator]: Completed translation [2025-03-09 06:57:03,333 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03 WrapperNode [2025-03-09 06:57:03,333 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-09 06:57:03,334 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-09 06:57:03,334 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-09 06:57:03,334 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-09 06:57:03,338 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,347 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,362 INFO L138 Inliner]: procedures = 18, calls = 19, calls flagged for inlining = 7, calls inlined = 8, statements flattened = 69 [2025-03-09 06:57:03,363 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-09 06:57:03,364 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-09 06:57:03,364 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-09 06:57:03,364 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-09 06:57:03,370 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,370 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,372 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,385 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [2, 5]. 71 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0]. The 1 writes are split as follows [0, 1]. [2025-03-09 06:57:03,385 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,385 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,389 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,390 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,390 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,391 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,392 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-09 06:57:03,393 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-09 06:57:03,394 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-09 06:57:03,394 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-09 06:57:03,394 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03" (1/1) ... [2025-03-09 06:57:03,398 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:03,407 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:03,417 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:03,419 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-09 06:57:03,436 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-09 06:57:03,436 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-09 06:57:03,436 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-03-09 06:57:03,436 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-03-09 06:57:03,436 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-03-09 06:57:03,436 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-03-09 06:57:03,436 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-09 06:57:03,436 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-09 06:57:03,437 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-03-09 06:57:03,437 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-03-09 06:57:03,437 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-09 06:57:03,487 INFO L256 CfgBuilder]: Building ICFG [2025-03-09 06:57:03,489 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-09 06:57:03,597 INFO L1307 $ProcedureCfgBuilder]: dead code at ProgramPoint L23: call ULTIMATE.dealloc(main_~#array~0#1.base, main_~#array~0#1.offset);havoc main_~#array~0#1.base, main_~#array~0#1.offset; [2025-03-09 06:57:03,603 INFO L? ?]: Removed 16 outVars from TransFormulas that were not future-live. [2025-03-09 06:57:03,603 INFO L307 CfgBuilder]: Performing block encoding [2025-03-09 06:57:03,608 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-09 06:57:03,608 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-09 06:57:03,609 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 06:57:03 BoogieIcfgContainer [2025-03-09 06:57:03,609 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-09 06:57:03,609 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-09 06:57:03,610 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-09 06:57:03,613 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-09 06:57:03,613 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 06:57:03,614 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.03 06:57:03" (1/3) ... [2025-03-09 06:57:03,614 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2a12f504 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 06:57:03, skipping insertion in model container [2025-03-09 06:57:03,614 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 06:57:03,614 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 06:57:03" (2/3) ... [2025-03-09 06:57:03,614 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2a12f504 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 06:57:03, skipping insertion in model container [2025-03-09 06:57:03,614 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 06:57:03,614 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 06:57:03" (3/3) ... [2025-03-09 06:57:03,615 INFO L363 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2025-03-09 06:57:03,648 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-09 06:57:03,648 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-09 06:57:03,649 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-09 06:57:03,649 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-09 06:57:03,649 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-09 06:57:03,649 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-09 06:57:03,649 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-09 06:57:03,649 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-09 06:57:03,653 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:03,663 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19 [2025-03-09 06:57:03,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:03,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:03,666 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 06:57:03,666 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-03-09 06:57:03,666 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-09 06:57:03,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:03,669 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19 [2025-03-09 06:57:03,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:03,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:03,670 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 06:57:03,670 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-03-09 06:57:03,673 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" [2025-03-09 06:57:03,673 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" [2025-03-09 06:57:03,676 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:03,679 INFO L85 PathProgramCache]: Analyzing trace with hash 1984, now seen corresponding path program 1 times [2025-03-09 06:57:03,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:03,684 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2131019615] [2025-03-09 06:57:03,685 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 06:57:03,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:03,730 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 06:57:03,743 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 06:57:03,744 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:03,744 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:03,744 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:03,746 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 06:57:03,749 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 06:57:03,749 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:03,749 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:03,758 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:03,760 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:03,760 INFO L85 PathProgramCache]: Analyzing trace with hash 61, now seen corresponding path program 1 times [2025-03-09 06:57:03,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:03,760 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788798492] [2025-03-09 06:57:03,760 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 06:57:03,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:03,764 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-09 06:57:03,766 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-09 06:57:03,766 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:03,766 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:03,766 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:03,767 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-09 06:57:03,769 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-09 06:57:03,769 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:03,769 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:03,771 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:03,771 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:03,772 INFO L85 PathProgramCache]: Analyzing trace with hash 61534, now seen corresponding path program 1 times [2025-03-09 06:57:03,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:03,772 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622298078] [2025-03-09 06:57:03,772 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 06:57:03,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:03,776 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:03,784 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:03,785 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:03,785 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:03,785 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:03,787 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:03,793 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:03,793 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:03,793 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:03,795 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:04,037 INFO L204 LassoAnalysis]: Preferences: [2025-03-09 06:57:04,038 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-09 06:57:04,038 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-09 06:57:04,038 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-09 06:57:04,038 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-03-09 06:57:04,038 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,042 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-09 06:57:04,042 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-09 06:57:04,042 INFO L132 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2025-03-09 06:57:04,042 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-09 06:57:04,042 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-09 06:57:04,052 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 06:57:04,057 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 06:57:04,069 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 06:57:04,071 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 06:57:04,073 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 06:57:04,076 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 06:57:04,078 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 06:57:04,205 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 06:57:04,209 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 06:57:04,211 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 06:57:04,213 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 06:57:04,216 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-09 06:57:04,384 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-09 06:57:04,386 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-03-09 06:57:04,387 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,388 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,390 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,391 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-03-09 06:57:04,393 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,404 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,405 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-09 06:57:04,405 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,405 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,405 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,408 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-09 06:57:04,409 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-09 06:57:04,424 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,430 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2025-03-09 06:57:04,432 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,432 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,434 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,435 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-03-09 06:57:04,436 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,446 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,446 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,446 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,446 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,451 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-09 06:57:04,451 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-09 06:57:04,455 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,461 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2025-03-09 06:57:04,462 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,462 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,464 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,465 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-03-09 06:57:04,467 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,477 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,477 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,477 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,477 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,480 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-09 06:57:04,480 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-09 06:57:04,484 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,490 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2025-03-09 06:57:04,491 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,491 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,492 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,494 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-03-09 06:57:04,496 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,507 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,507 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-09 06:57:04,507 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,507 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,507 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,508 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-09 06:57:04,508 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-09 06:57:04,509 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,515 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2025-03-09 06:57:04,515 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,515 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,517 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,518 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-03-09 06:57:04,520 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,530 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,531 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-09 06:57:04,531 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,531 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,531 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,531 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-09 06:57:04,531 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-09 06:57:04,534 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,539 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2025-03-09 06:57:04,540 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,540 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,541 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,542 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-03-09 06:57:04,543 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,553 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,553 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-09 06:57:04,554 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,554 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,554 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,554 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-09 06:57:04,554 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-09 06:57:04,555 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,561 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2025-03-09 06:57:04,561 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,561 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,564 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,565 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-03-09 06:57:04,566 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,575 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,576 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-09 06:57:04,576 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,576 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,576 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,576 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-09 06:57:04,576 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-09 06:57:04,577 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,583 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2025-03-09 06:57:04,583 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,584 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,585 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,586 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-03-09 06:57:04,587 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,597 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,597 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,597 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,597 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,603 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-09 06:57:04,603 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-09 06:57:04,606 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,611 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2025-03-09 06:57:04,612 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,612 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,614 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,615 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2025-03-09 06:57:04,616 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,626 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,626 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-09 06:57:04,626 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,626 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,626 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,627 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-09 06:57:04,627 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-09 06:57:04,628 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,634 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2025-03-09 06:57:04,634 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,634 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,636 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,637 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2025-03-09 06:57:04,639 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,648 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,649 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,649 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,649 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,650 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-09 06:57:04,650 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-09 06:57:04,654 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,659 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2025-03-09 06:57:04,659 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,659 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,662 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,663 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2025-03-09 06:57:04,663 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,674 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,674 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,674 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,674 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,678 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-09 06:57:04,678 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-09 06:57:04,681 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,686 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2025-03-09 06:57:04,686 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,687 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,689 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,691 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2025-03-09 06:57:04,694 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,704 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,704 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,704 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,704 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,707 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-09 06:57:04,707 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-09 06:57:04,710 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,719 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2025-03-09 06:57:04,719 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,719 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,721 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,722 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2025-03-09 06:57:04,723 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,733 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,734 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,734 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,734 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,735 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-09 06:57:04,735 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-09 06:57:04,739 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,744 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2025-03-09 06:57:04,744 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,745 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,747 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,748 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2025-03-09 06:57:04,750 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,760 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,760 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,760 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,760 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,763 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-09 06:57:04,763 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-09 06:57:04,766 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-09 06:57:04,771 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2025-03-09 06:57:04,771 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,772 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,773 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,774 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2025-03-09 06:57:04,775 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-09 06:57:04,784 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-09 06:57:04,785 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-09 06:57:04,785 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-09 06:57:04,785 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-09 06:57:04,788 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-09 06:57:04,788 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-09 06:57:04,794 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-03-09 06:57:04,811 INFO L443 ModelExtractionUtils]: Simplification made 14 calls to the SMT solver. [2025-03-09 06:57:04,814 INFO L444 ModelExtractionUtils]: 6 out of 16 variables were initially zero. Simplification set additionally 6 variables to zero. [2025-03-09 06:57:04,815 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 06:57:04,815 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:04,817 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 06:57:04,819 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2025-03-09 06:57:04,820 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-03-09 06:57:04,831 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-03-09 06:57:04,831 INFO L474 LassoAnalysis]: Proved termination. [2025-03-09 06:57:04,831 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~#array~0#1.offset, v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1, ULTIMATE.start_main_~i~0#1) = -1*ULTIMATE.start_main_~#array~0#1.offset + 1*v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2025-03-09 06:57:04,837 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2025-03-09 06:57:04,847 INFO L156 tatePredicateManager]: 4 out of 4 supporting invariants were superfluous and have been removed [2025-03-09 06:57:04,851 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: #length [2025-03-09 06:57:04,851 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#length,GLOBAL] [2025-03-09 06:57:04,852 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: ~#array~0!offset [2025-03-09 06:57:04,869 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:04,875 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 06:57:04,880 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 06:57:04,880 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:04,880 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:04,881 INFO L256 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-03-09 06:57:04,881 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:04,891 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-09 06:57:04,893 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-09 06:57:04,893 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:04,893 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:04,893 INFO L256 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-03-09 06:57:04,894 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:04,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:04,917 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2025-03-09 06:57:04,919 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:04,943 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 2 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 26 states and 36 transitions. Complement of second has 3 states. [2025-03-09 06:57:04,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 2 states 1 stem states 0 non-accepting loop states 1 accepting loop states [2025-03-09 06:57:04,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:04,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 3 transitions. [2025-03-09 06:57:04,951 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 3 transitions. Stem has 2 letters. Loop has 1 letters. [2025-03-09 06:57:04,951 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-09 06:57:04,952 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 3 transitions. Stem has 3 letters. Loop has 1 letters. [2025-03-09 06:57:04,952 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-09 06:57:04,952 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 3 transitions. Stem has 2 letters. Loop has 2 letters. [2025-03-09 06:57:04,952 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-09 06:57:04,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 36 transitions. [2025-03-09 06:57:04,955 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2025-03-09 06:57:04,958 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 23 states and 33 transitions. [2025-03-09 06:57:04,959 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2025-03-09 06:57:04,960 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2025-03-09 06:57:04,960 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 33 transitions. [2025-03-09 06:57:04,961 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:04,961 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23 states and 33 transitions. [2025-03-09 06:57:04,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 33 transitions. [2025-03-09 06:57:04,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 22. [2025-03-09 06:57:04,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.4090909090909092) internal successors, (31), 21 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:04,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 31 transitions. [2025-03-09 06:57:04,979 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22 states and 31 transitions. [2025-03-09 06:57:04,979 INFO L432 stractBuchiCegarLoop]: Abstraction has 22 states and 31 transitions. [2025-03-09 06:57:04,979 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-09 06:57:04,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 31 transitions. [2025-03-09 06:57:04,980 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2025-03-09 06:57:04,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:04,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:04,981 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2025-03-09 06:57:04,981 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:04,981 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" [2025-03-09 06:57:04,981 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" [2025-03-09 06:57:04,982 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:04,983 INFO L85 PathProgramCache]: Analyzing trace with hash 61533, now seen corresponding path program 1 times [2025-03-09 06:57:04,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:04,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327280413] [2025-03-09 06:57:04,984 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 06:57:04,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:04,988 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:04,996 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:04,998 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:04,998 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:04,998 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:04,999 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:05,002 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:05,003 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:05,003 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:05,006 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:05,007 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:05,007 INFO L85 PathProgramCache]: Analyzing trace with hash 57553, now seen corresponding path program 1 times [2025-03-09 06:57:05,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:05,007 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726149688] [2025-03-09 06:57:05,007 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 06:57:05,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:05,009 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:05,015 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:05,015 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:05,015 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:05,015 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:05,016 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:05,022 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:05,023 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:05,024 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:05,026 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:05,026 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:05,027 INFO L85 PathProgramCache]: Analyzing trace with hash 1833157365, now seen corresponding path program 1 times [2025-03-09 06:57:05,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:05,027 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806146922] [2025-03-09 06:57:05,028 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 06:57:05,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:05,031 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-09 06:57:05,037 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-09 06:57:05,038 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:05,038 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:05,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:05,128 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:05,128 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806146922] [2025-03-09 06:57:05,128 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1806146922] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 06:57:05,129 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 06:57:05,129 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-09 06:57:05,129 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1202859473] [2025-03-09 06:57:05,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 06:57:05,166 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:05,171 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-09 06:57:05,171 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2025-03-09 06:57:05,172 INFO L87 Difference]: Start difference. First operand 22 states and 31 transitions. cyclomatic complexity: 12 Second operand has 4 states, 4 states have (on average 1.5) internal successors, (6), 4 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:05,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:05,214 INFO L93 Difference]: Finished difference Result 38 states and 45 transitions. [2025-03-09 06:57:05,214 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 45 transitions. [2025-03-09 06:57:05,214 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:05,215 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 28 states and 34 transitions. [2025-03-09 06:57:05,215 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2025-03-09 06:57:05,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2025-03-09 06:57:05,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 34 transitions. [2025-03-09 06:57:05,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:05,215 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28 states and 34 transitions. [2025-03-09 06:57:05,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 34 transitions. [2025-03-09 06:57:05,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 17. [2025-03-09 06:57:05,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.2352941176470589) internal successors, (21), 16 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:05,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 21 transitions. [2025-03-09 06:57:05,216 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17 states and 21 transitions. [2025-03-09 06:57:05,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-09 06:57:05,217 INFO L432 stractBuchiCegarLoop]: Abstraction has 17 states and 21 transitions. [2025-03-09 06:57:05,217 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-09 06:57:05,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 21 transitions. [2025-03-09 06:57:05,218 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:05,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:05,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:05,218 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2025-03-09 06:57:05,218 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:05,218 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:05,218 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:05,218 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:05,218 INFO L85 PathProgramCache]: Analyzing trace with hash 59135101, now seen corresponding path program 1 times [2025-03-09 06:57:05,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:05,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [52752651] [2025-03-09 06:57:05,218 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 06:57:05,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:05,222 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-03-09 06:57:05,227 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-03-09 06:57:05,227 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:05,227 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:05,227 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:05,229 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-03-09 06:57:05,232 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-03-09 06:57:05,233 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:05,233 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:05,234 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:05,235 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:05,235 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 2 times [2025-03-09 06:57:05,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:05,235 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975560535] [2025-03-09 06:57:05,235 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:57:05,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:05,237 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:05,240 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:05,240 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 06:57:05,240 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:05,240 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:05,242 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:05,245 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:05,245 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:05,245 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:05,250 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:05,251 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:05,251 INFO L85 PathProgramCache]: Analyzing trace with hash 757229033, now seen corresponding path program 1 times [2025-03-09 06:57:05,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:05,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1172632711] [2025-03-09 06:57:05,251 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 06:57:05,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:05,257 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-09 06:57:05,268 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-09 06:57:05,268 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:05,268 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:05,345 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:05,346 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:05,346 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1172632711] [2025-03-09 06:57:05,346 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1172632711] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:05,346 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [610459040] [2025-03-09 06:57:05,346 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 06:57:05,346 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:05,346 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:05,348 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:05,350 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2025-03-09 06:57:05,373 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-09 06:57:05,380 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-09 06:57:05,380 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:05,380 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:05,381 INFO L256 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjuncts are in the unsatisfiable core [2025-03-09 06:57:05,382 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:05,418 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:05,418 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:05,450 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:05,450 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [610459040] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:05,450 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:05,450 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 9 [2025-03-09 06:57:05,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275083734] [2025-03-09 06:57:05,450 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:05,493 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:05,493 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-09 06:57:05,493 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2025-03-09 06:57:05,494 INFO L87 Difference]: Start difference. First operand 17 states and 21 transitions. cyclomatic complexity: 7 Second operand has 10 states, 9 states have (on average 2.111111111111111) internal successors, (19), 10 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:05,539 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2025-03-09 06:57:05,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:05,596 INFO L93 Difference]: Finished difference Result 55 states and 66 transitions. [2025-03-09 06:57:05,596 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 66 transitions. [2025-03-09 06:57:05,597 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:05,598 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 41 states and 49 transitions. [2025-03-09 06:57:05,598 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2025-03-09 06:57:05,598 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2025-03-09 06:57:05,598 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41 states and 49 transitions. [2025-03-09 06:57:05,598 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:05,598 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41 states and 49 transitions. [2025-03-09 06:57:05,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states and 49 transitions. [2025-03-09 06:57:05,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 24. [2025-03-09 06:57:05,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 23 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:05,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 29 transitions. [2025-03-09 06:57:05,599 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 29 transitions. [2025-03-09 06:57:05,602 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-09 06:57:05,602 INFO L432 stractBuchiCegarLoop]: Abstraction has 24 states and 29 transitions. [2025-03-09 06:57:05,602 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-09 06:57:05,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 29 transitions. [2025-03-09 06:57:05,603 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:05,603 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:05,603 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:05,603 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1] [2025-03-09 06:57:05,603 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:05,603 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:05,603 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:05,603 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:05,603 INFO L85 PathProgramCache]: Analyzing trace with hash 2028855303, now seen corresponding path program 2 times [2025-03-09 06:57:05,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:05,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [180334429] [2025-03-09 06:57:05,604 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:57:05,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:05,611 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 9 statements into 2 equivalence classes. [2025-03-09 06:57:05,620 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 9 of 9 statements. [2025-03-09 06:57:05,620 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-09 06:57:05,620 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:05,620 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:05,624 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-09 06:57:05,634 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-09 06:57:05,634 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:05,634 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:05,636 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:05,636 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:05,636 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 3 times [2025-03-09 06:57:05,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:05,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889973223] [2025-03-09 06:57:05,637 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:05,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:05,640 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:05,642 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:05,642 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 06:57:05,642 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:05,642 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:05,644 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:05,647 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:05,647 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:05,647 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:05,648 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:05,649 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:05,649 INFO L85 PathProgramCache]: Analyzing trace with hash -1446398433, now seen corresponding path program 3 times [2025-03-09 06:57:05,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:05,649 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785741167] [2025-03-09 06:57:05,649 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:05,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:05,654 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 12 statements into 3 equivalence classes. [2025-03-09 06:57:05,662 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 12 of 12 statements. [2025-03-09 06:57:05,663 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-03-09 06:57:05,663 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:05,739 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:05,740 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:05,740 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [785741167] [2025-03-09 06:57:05,740 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [785741167] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:05,740 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [317433010] [2025-03-09 06:57:05,740 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:05,740 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:05,740 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:05,743 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:05,745 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2025-03-09 06:57:05,781 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 12 statements into 3 equivalence classes. [2025-03-09 06:57:05,792 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 12 of 12 statements. [2025-03-09 06:57:05,792 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-03-09 06:57:05,793 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:05,793 INFO L256 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 8 conjuncts are in the unsatisfiable core [2025-03-09 06:57:05,794 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:05,855 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:05,856 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:05,898 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:05,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [317433010] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:05,898 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:05,898 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 12 [2025-03-09 06:57:05,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1981470548] [2025-03-09 06:57:05,898 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:05,930 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:05,930 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-09 06:57:05,930 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=109, Unknown=0, NotChecked=0, Total=156 [2025-03-09 06:57:05,931 INFO L87 Difference]: Start difference. First operand 24 states and 29 transitions. cyclomatic complexity: 8 Second operand has 13 states, 12 states have (on average 2.1666666666666665) internal successors, (26), 13 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:06,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:06,016 INFO L93 Difference]: Finished difference Result 80 states and 95 transitions. [2025-03-09 06:57:06,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80 states and 95 transitions. [2025-03-09 06:57:06,017 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:06,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80 states to 54 states and 64 transitions. [2025-03-09 06:57:06,018 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2025-03-09 06:57:06,018 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2025-03-09 06:57:06,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54 states and 64 transitions. [2025-03-09 06:57:06,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:06,018 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54 states and 64 transitions. [2025-03-09 06:57:06,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states and 64 transitions. [2025-03-09 06:57:06,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 31. [2025-03-09 06:57:06,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.1935483870967742) internal successors, (37), 30 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:06,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 37 transitions. [2025-03-09 06:57:06,024 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31 states and 37 transitions. [2025-03-09 06:57:06,024 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-09 06:57:06,024 INFO L432 stractBuchiCegarLoop]: Abstraction has 31 states and 37 transitions. [2025-03-09 06:57:06,024 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-09 06:57:06,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 37 transitions. [2025-03-09 06:57:06,025 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:06,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:06,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:06,025 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 1, 1, 1] [2025-03-09 06:57:06,025 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:06,025 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:06,025 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:06,025 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:06,025 INFO L85 PathProgramCache]: Analyzing trace with hash -789647043, now seen corresponding path program 4 times [2025-03-09 06:57:06,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:06,026 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327575482] [2025-03-09 06:57:06,026 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:57:06,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:06,033 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 13 statements into 2 equivalence classes. [2025-03-09 06:57:06,046 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 13 of 13 statements. [2025-03-09 06:57:06,046 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:57:06,047 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:06,047 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:06,048 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-03-09 06:57:06,063 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-03-09 06:57:06,063 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:06,063 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:06,069 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:06,069 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:06,069 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 4 times [2025-03-09 06:57:06,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:06,069 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257338613] [2025-03-09 06:57:06,069 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:57:06,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:06,071 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-03-09 06:57:06,075 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:06,075 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:57:06,075 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:06,075 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:06,076 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:06,078 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:06,078 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:06,078 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:06,080 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:06,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:06,080 INFO L85 PathProgramCache]: Analyzing trace with hash -839151319, now seen corresponding path program 5 times [2025-03-09 06:57:06,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:06,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796162906] [2025-03-09 06:57:06,080 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:06,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:06,086 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 16 statements into 4 equivalence classes. [2025-03-09 06:57:06,093 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 16 of 16 statements. [2025-03-09 06:57:06,093 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-03-09 06:57:06,093 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:06,196 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:06,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:06,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [796162906] [2025-03-09 06:57:06,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [796162906] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:06,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1695002643] [2025-03-09 06:57:06,196 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:06,196 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:06,196 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:06,200 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:06,201 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2025-03-09 06:57:06,228 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 16 statements into 4 equivalence classes. [2025-03-09 06:57:06,242 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 16 of 16 statements. [2025-03-09 06:57:06,242 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-03-09 06:57:06,242 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:06,243 INFO L256 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 10 conjuncts are in the unsatisfiable core [2025-03-09 06:57:06,244 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:06,351 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:06,351 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:06,405 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:06,406 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1695002643] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:06,406 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:06,406 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 13 [2025-03-09 06:57:06,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1698292398] [2025-03-09 06:57:06,406 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:06,442 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:06,442 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2025-03-09 06:57:06,442 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2025-03-09 06:57:06,443 INFO L87 Difference]: Start difference. First operand 31 states and 37 transitions. cyclomatic complexity: 9 Second operand has 14 states, 13 states have (on average 2.076923076923077) internal successors, (27), 14 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:06,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:06,563 INFO L93 Difference]: Finished difference Result 105 states and 124 transitions. [2025-03-09 06:57:06,563 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 124 transitions. [2025-03-09 06:57:06,564 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:06,564 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 67 states and 79 transitions. [2025-03-09 06:57:06,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63 [2025-03-09 06:57:06,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63 [2025-03-09 06:57:06,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 79 transitions. [2025-03-09 06:57:06,565 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:06,565 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67 states and 79 transitions. [2025-03-09 06:57:06,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 79 transitions. [2025-03-09 06:57:06,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 38. [2025-03-09 06:57:06,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.1842105263157894) internal successors, (45), 37 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:06,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 45 transitions. [2025-03-09 06:57:06,570 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38 states and 45 transitions. [2025-03-09 06:57:06,571 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 06:57:06,571 INFO L432 stractBuchiCegarLoop]: Abstraction has 38 states and 45 transitions. [2025-03-09 06:57:06,572 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-09 06:57:06,572 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 45 transitions. [2025-03-09 06:57:06,572 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:06,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:06,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:06,573 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 1, 1, 1] [2025-03-09 06:57:06,573 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:06,573 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:06,573 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:06,573 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:06,573 INFO L85 PathProgramCache]: Analyzing trace with hash 464653639, now seen corresponding path program 6 times [2025-03-09 06:57:06,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:06,573 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259064165] [2025-03-09 06:57:06,573 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:57:06,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:06,581 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 17 statements into 4 equivalence classes. [2025-03-09 06:57:06,604 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) and asserted 17 of 17 statements. [2025-03-09 06:57:06,607 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2025-03-09 06:57:06,608 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:06,608 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:06,610 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes. [2025-03-09 06:57:06,618 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements. [2025-03-09 06:57:06,619 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:06,620 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:06,622 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:06,624 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:06,624 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 5 times [2025-03-09 06:57:06,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:06,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540256711] [2025-03-09 06:57:06,624 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:06,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:06,626 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:06,627 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:06,627 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 06:57:06,627 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:06,628 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:06,628 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:06,629 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:06,629 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:06,629 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:06,630 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:06,631 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:06,631 INFO L85 PathProgramCache]: Analyzing trace with hash -183009057, now seen corresponding path program 7 times [2025-03-09 06:57:06,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:06,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304025129] [2025-03-09 06:57:06,631 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:06,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:06,636 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-03-09 06:57:06,642 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-03-09 06:57:06,642 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:06,643 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:06,753 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 12 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:06,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:06,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1304025129] [2025-03-09 06:57:06,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1304025129] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:06,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1436346316] [2025-03-09 06:57:06,753 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:06,753 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:06,753 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:06,755 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:06,757 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2025-03-09 06:57:06,791 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-03-09 06:57:06,804 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-03-09 06:57:06,804 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:06,804 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:06,804 INFO L256 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 12 conjuncts are in the unsatisfiable core [2025-03-09 06:57:06,805 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:06,909 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 22 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:06,909 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:06,984 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 22 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:06,984 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1436346316] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:06,984 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:06,984 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 18 [2025-03-09 06:57:06,984 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1482790820] [2025-03-09 06:57:06,984 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:07,029 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:07,030 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2025-03-09 06:57:07,030 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=249, Unknown=0, NotChecked=0, Total=342 [2025-03-09 06:57:07,030 INFO L87 Difference]: Start difference. First operand 38 states and 45 transitions. cyclomatic complexity: 10 Second operand has 19 states, 18 states have (on average 2.2222222222222223) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:07,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:07,184 INFO L93 Difference]: Finished difference Result 130 states and 153 transitions. [2025-03-09 06:57:07,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130 states and 153 transitions. [2025-03-09 06:57:07,185 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:07,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130 states to 80 states and 94 transitions. [2025-03-09 06:57:07,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75 [2025-03-09 06:57:07,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75 [2025-03-09 06:57:07,186 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 94 transitions. [2025-03-09 06:57:07,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:07,186 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80 states and 94 transitions. [2025-03-09 06:57:07,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 94 transitions. [2025-03-09 06:57:07,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 45. [2025-03-09 06:57:07,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.1777777777777778) internal successors, (53), 44 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:07,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 53 transitions. [2025-03-09 06:57:07,188 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 53 transitions. [2025-03-09 06:57:07,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2025-03-09 06:57:07,189 INFO L432 stractBuchiCegarLoop]: Abstraction has 45 states and 53 transitions. [2025-03-09 06:57:07,189 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-09 06:57:07,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 53 transitions. [2025-03-09 06:57:07,190 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:07,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:07,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:07,190 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 1, 1, 1] [2025-03-09 06:57:07,190 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:07,191 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:07,191 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:07,191 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:07,191 INFO L85 PathProgramCache]: Analyzing trace with hash 1289141757, now seen corresponding path program 8 times [2025-03-09 06:57:07,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:07,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794226659] [2025-03-09 06:57:07,191 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:57:07,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:07,196 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 21 statements into 2 equivalence classes. [2025-03-09 06:57:07,208 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 21 of 21 statements. [2025-03-09 06:57:07,209 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-09 06:57:07,209 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:07,209 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:07,211 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-09 06:57:07,219 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-09 06:57:07,219 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:07,219 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:07,221 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:07,222 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:07,222 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 6 times [2025-03-09 06:57:07,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:07,222 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [797989747] [2025-03-09 06:57:07,222 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:57:07,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:07,224 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:07,225 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:07,225 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 06:57:07,225 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:07,225 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:07,226 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:07,226 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:07,226 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:07,227 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:07,227 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:07,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:07,228 INFO L85 PathProgramCache]: Analyzing trace with hash -775451543, now seen corresponding path program 9 times [2025-03-09 06:57:07,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:07,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482452915] [2025-03-09 06:57:07,228 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:07,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:07,233 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 24 statements into 6 equivalence classes. [2025-03-09 06:57:07,265 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 24 of 24 statements. [2025-03-09 06:57:07,265 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-03-09 06:57:07,265 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:07,424 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 22 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:07,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:07,425 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [482452915] [2025-03-09 06:57:07,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [482452915] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:07,425 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1451971385] [2025-03-09 06:57:07,425 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:07,425 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:07,425 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:07,427 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:07,428 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2025-03-09 06:57:07,459 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 24 statements into 6 equivalence classes. [2025-03-09 06:57:07,485 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 24 of 24 statements. [2025-03-09 06:57:07,485 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-03-09 06:57:07,485 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:07,486 INFO L256 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 14 conjuncts are in the unsatisfiable core [2025-03-09 06:57:07,487 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:07,611 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 35 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:07,611 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:07,691 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 35 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:07,691 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1451971385] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:07,691 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:07,691 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 21 [2025-03-09 06:57:07,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1676467537] [2025-03-09 06:57:07,691 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:07,728 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:07,728 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-03-09 06:57:07,728 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=340, Unknown=0, NotChecked=0, Total=462 [2025-03-09 06:57:07,728 INFO L87 Difference]: Start difference. First operand 45 states and 53 transitions. cyclomatic complexity: 11 Second operand has 22 states, 21 states have (on average 2.238095238095238) internal successors, (47), 22 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:07,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:07,933 INFO L93 Difference]: Finished difference Result 155 states and 182 transitions. [2025-03-09 06:57:07,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155 states and 182 transitions. [2025-03-09 06:57:07,935 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:07,935 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155 states to 93 states and 109 transitions. [2025-03-09 06:57:07,935 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 87 [2025-03-09 06:57:07,935 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 87 [2025-03-09 06:57:07,935 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93 states and 109 transitions. [2025-03-09 06:57:07,936 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:07,936 INFO L218 hiAutomatonCegarLoop]: Abstraction has 93 states and 109 transitions. [2025-03-09 06:57:07,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states and 109 transitions. [2025-03-09 06:57:07,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 52. [2025-03-09 06:57:07,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.1730769230769231) internal successors, (61), 51 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:07,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 61 transitions. [2025-03-09 06:57:07,940 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 61 transitions. [2025-03-09 06:57:07,941 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2025-03-09 06:57:07,941 INFO L432 stractBuchiCegarLoop]: Abstraction has 52 states and 61 transitions. [2025-03-09 06:57:07,941 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-09 06:57:07,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 61 transitions. [2025-03-09 06:57:07,942 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:07,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:07,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:07,942 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 1, 1, 1] [2025-03-09 06:57:07,942 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:07,942 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:07,942 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:07,944 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:07,944 INFO L85 PathProgramCache]: Analyzing trace with hash -1891169657, now seen corresponding path program 10 times [2025-03-09 06:57:07,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:07,944 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869764750] [2025-03-09 06:57:07,944 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:57:07,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:07,949 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 25 statements into 2 equivalence classes. [2025-03-09 06:57:07,964 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 25 of 25 statements. [2025-03-09 06:57:07,964 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:57:07,964 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:07,964 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:07,966 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 25 statements into 1 equivalence classes. [2025-03-09 06:57:07,974 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 25 of 25 statements. [2025-03-09 06:57:07,974 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:07,974 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:07,984 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:07,984 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:07,984 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 7 times [2025-03-09 06:57:07,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:07,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167557747] [2025-03-09 06:57:07,984 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:07,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:07,986 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:07,987 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:07,987 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:07,987 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:07,987 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:07,987 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:07,988 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:07,988 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:07,988 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:07,989 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:07,989 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:07,989 INFO L85 PathProgramCache]: Analyzing trace with hash 1545763743, now seen corresponding path program 11 times [2025-03-09 06:57:07,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:07,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899263857] [2025-03-09 06:57:07,989 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:07,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:07,995 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 28 statements into 7 equivalence classes. [2025-03-09 06:57:08,008 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) and asserted 28 of 28 statements. [2025-03-09 06:57:08,009 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2025-03-09 06:57:08,009 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:08,195 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 51 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:08,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:08,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1899263857] [2025-03-09 06:57:08,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1899263857] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:08,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2007407052] [2025-03-09 06:57:08,196 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:08,196 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:08,196 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:08,198 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:08,200 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2025-03-09 06:57:08,237 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 28 statements into 7 equivalence classes. [2025-03-09 06:57:08,267 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) and asserted 28 of 28 statements. [2025-03-09 06:57:08,268 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2025-03-09 06:57:08,268 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:08,269 INFO L256 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 17 conjuncts are in the unsatisfiable core [2025-03-09 06:57:08,270 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:08,503 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 45 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:08,503 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:08,683 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 45 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:08,684 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2007407052] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:08,684 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:08,684 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 16] total 38 [2025-03-09 06:57:08,684 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449908551] [2025-03-09 06:57:08,684 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:08,716 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:08,717 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2025-03-09 06:57:08,717 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=265, Invalid=1217, Unknown=0, NotChecked=0, Total=1482 [2025-03-09 06:57:08,718 INFO L87 Difference]: Start difference. First operand 52 states and 61 transitions. cyclomatic complexity: 12 Second operand has 39 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 39 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:09,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:09,103 INFO L93 Difference]: Finished difference Result 217 states and 253 transitions. [2025-03-09 06:57:09,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217 states and 253 transitions. [2025-03-09 06:57:09,104 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:09,105 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217 states to 106 states and 124 transitions. [2025-03-09 06:57:09,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99 [2025-03-09 06:57:09,105 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99 [2025-03-09 06:57:09,105 INFO L73 IsDeterministic]: Start isDeterministic. Operand 106 states and 124 transitions. [2025-03-09 06:57:09,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:09,105 INFO L218 hiAutomatonCegarLoop]: Abstraction has 106 states and 124 transitions. [2025-03-09 06:57:09,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states and 124 transitions. [2025-03-09 06:57:09,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 59. [2025-03-09 06:57:09,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.1694915254237288) internal successors, (69), 58 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:09,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 69 transitions. [2025-03-09 06:57:09,107 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59 states and 69 transitions. [2025-03-09 06:57:09,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2025-03-09 06:57:09,108 INFO L432 stractBuchiCegarLoop]: Abstraction has 59 states and 69 transitions. [2025-03-09 06:57:09,108 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-09 06:57:09,108 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 69 transitions. [2025-03-09 06:57:09,108 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:09,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:09,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:09,109 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 6, 1, 1, 1] [2025-03-09 06:57:09,109 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:09,109 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:09,109 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:09,110 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:09,110 INFO L85 PathProgramCache]: Analyzing trace with hash 861518525, now seen corresponding path program 12 times [2025-03-09 06:57:09,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:09,110 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123156845] [2025-03-09 06:57:09,110 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:57:09,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:09,116 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 29 statements into 7 equivalence classes. [2025-03-09 06:57:09,152 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) and asserted 29 of 29 statements. [2025-03-09 06:57:09,152 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2025-03-09 06:57:09,152 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:09,152 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:09,155 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-09 06:57:09,168 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-09 06:57:09,168 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:09,168 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:09,172 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:09,172 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:09,172 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 8 times [2025-03-09 06:57:09,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:09,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37730538] [2025-03-09 06:57:09,172 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:57:09,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:09,174 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:09,175 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:09,175 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 06:57:09,175 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:09,175 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:09,175 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:09,176 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:09,176 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:09,176 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:09,177 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:09,177 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:09,177 INFO L85 PathProgramCache]: Analyzing trace with hash -1226156119, now seen corresponding path program 13 times [2025-03-09 06:57:09,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:09,177 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [142177301] [2025-03-09 06:57:09,177 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:09,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:09,185 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-03-09 06:57:09,191 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-03-09 06:57:09,191 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:09,191 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:09,417 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 51 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:09,417 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:09,417 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [142177301] [2025-03-09 06:57:09,417 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [142177301] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:09,417 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1881730566] [2025-03-09 06:57:09,417 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:09,417 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:09,417 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:09,419 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:09,433 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2025-03-09 06:57:09,467 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-03-09 06:57:09,484 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-03-09 06:57:09,484 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:09,484 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:09,485 INFO L256 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 18 conjuncts are in the unsatisfiable core [2025-03-09 06:57:09,486 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:09,646 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 70 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:09,646 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:09,772 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 70 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:09,772 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1881730566] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:09,772 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:09,772 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 27 [2025-03-09 06:57:09,772 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543845890] [2025-03-09 06:57:09,772 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:09,810 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:09,811 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2025-03-09 06:57:09,811 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=564, Unknown=0, NotChecked=0, Total=756 [2025-03-09 06:57:09,811 INFO L87 Difference]: Start difference. First operand 59 states and 69 transitions. cyclomatic complexity: 13 Second operand has 28 states, 27 states have (on average 2.259259259259259) internal successors, (61), 28 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:10,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:10,030 INFO L93 Difference]: Finished difference Result 205 states and 240 transitions. [2025-03-09 06:57:10,030 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 205 states and 240 transitions. [2025-03-09 06:57:10,031 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:10,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 205 states to 119 states and 139 transitions. [2025-03-09 06:57:10,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 111 [2025-03-09 06:57:10,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 111 [2025-03-09 06:57:10,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119 states and 139 transitions. [2025-03-09 06:57:10,034 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:10,034 INFO L218 hiAutomatonCegarLoop]: Abstraction has 119 states and 139 transitions. [2025-03-09 06:57:10,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states and 139 transitions. [2025-03-09 06:57:10,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 66. [2025-03-09 06:57:10,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.1666666666666667) internal successors, (77), 65 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:10,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 77 transitions. [2025-03-09 06:57:10,036 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66 states and 77 transitions. [2025-03-09 06:57:10,040 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2025-03-09 06:57:10,040 INFO L432 stractBuchiCegarLoop]: Abstraction has 66 states and 77 transitions. [2025-03-09 06:57:10,040 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-09 06:57:10,040 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 77 transitions. [2025-03-09 06:57:10,041 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:10,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:10,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:10,041 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 7, 1, 1, 1] [2025-03-09 06:57:10,041 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:10,041 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:10,041 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:10,041 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:10,042 INFO L85 PathProgramCache]: Analyzing trace with hash -1810835513, now seen corresponding path program 14 times [2025-03-09 06:57:10,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:10,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802155354] [2025-03-09 06:57:10,042 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:57:10,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:10,048 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 33 statements into 2 equivalence classes. [2025-03-09 06:57:10,079 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 33 of 33 statements. [2025-03-09 06:57:10,079 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-09 06:57:10,079 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:10,079 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:10,081 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-09 06:57:10,098 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-09 06:57:10,099 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:10,099 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:10,105 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:10,106 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:10,106 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 9 times [2025-03-09 06:57:10,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:10,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572371435] [2025-03-09 06:57:10,106 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:10,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:10,108 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:10,109 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:10,109 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 06:57:10,110 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:10,110 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:10,110 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:10,111 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:10,111 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:10,111 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:10,112 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:10,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:10,113 INFO L85 PathProgramCache]: Analyzing trace with hash -1811503521, now seen corresponding path program 15 times [2025-03-09 06:57:10,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:10,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [923325713] [2025-03-09 06:57:10,113 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:10,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:10,122 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 36 statements into 9 equivalence classes. [2025-03-09 06:57:10,182 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) and asserted 36 of 36 statements. [2025-03-09 06:57:10,182 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2025-03-09 06:57:10,183 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:10,442 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 70 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:10,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:10,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [923325713] [2025-03-09 06:57:10,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [923325713] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:10,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1276450783] [2025-03-09 06:57:10,443 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:10,443 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:10,443 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:10,445 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:10,446 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2025-03-09 06:57:10,490 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 36 statements into 9 equivalence classes. [2025-03-09 06:57:10,532 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) and asserted 36 of 36 statements. [2025-03-09 06:57:10,533 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2025-03-09 06:57:10,533 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:10,534 INFO L256 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 20 conjuncts are in the unsatisfiable core [2025-03-09 06:57:10,535 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:10,741 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 92 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:10,742 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:10,861 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 92 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:10,861 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1276450783] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:10,861 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:10,861 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 30 [2025-03-09 06:57:10,861 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76498698] [2025-03-09 06:57:10,861 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:10,887 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:10,888 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2025-03-09 06:57:10,888 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=233, Invalid=697, Unknown=0, NotChecked=0, Total=930 [2025-03-09 06:57:10,888 INFO L87 Difference]: Start difference. First operand 66 states and 77 transitions. cyclomatic complexity: 14 Second operand has 31 states, 30 states have (on average 2.2666666666666666) internal successors, (68), 31 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:11,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:11,138 INFO L93 Difference]: Finished difference Result 230 states and 269 transitions. [2025-03-09 06:57:11,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 269 transitions. [2025-03-09 06:57:11,139 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:11,140 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 132 states and 154 transitions. [2025-03-09 06:57:11,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123 [2025-03-09 06:57:11,140 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123 [2025-03-09 06:57:11,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132 states and 154 transitions. [2025-03-09 06:57:11,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:11,141 INFO L218 hiAutomatonCegarLoop]: Abstraction has 132 states and 154 transitions. [2025-03-09 06:57:11,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states and 154 transitions. [2025-03-09 06:57:11,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 73. [2025-03-09 06:57:11,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.1643835616438356) internal successors, (85), 72 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:11,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 85 transitions. [2025-03-09 06:57:11,148 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73 states and 85 transitions. [2025-03-09 06:57:11,148 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2025-03-09 06:57:11,149 INFO L432 stractBuchiCegarLoop]: Abstraction has 73 states and 85 transitions. [2025-03-09 06:57:11,149 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-09 06:57:11,149 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 85 transitions. [2025-03-09 06:57:11,151 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:11,151 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:11,151 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:11,152 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 8, 1, 1, 1] [2025-03-09 06:57:11,152 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:11,152 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:11,152 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:11,152 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:11,152 INFO L85 PathProgramCache]: Analyzing trace with hash 2073290621, now seen corresponding path program 16 times [2025-03-09 06:57:11,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:11,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623200683] [2025-03-09 06:57:11,153 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:57:11,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:11,161 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 37 statements into 2 equivalence classes. [2025-03-09 06:57:11,186 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 37 of 37 statements. [2025-03-09 06:57:11,186 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:57:11,186 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:11,186 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:11,189 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-03-09 06:57:11,209 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-03-09 06:57:11,209 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:11,209 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:11,215 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:11,218 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:11,218 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 10 times [2025-03-09 06:57:11,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:11,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223660782] [2025-03-09 06:57:11,218 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:57:11,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:11,220 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-03-09 06:57:11,221 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:11,221 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:57:11,221 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:11,221 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:11,221 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:11,222 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:11,222 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:11,222 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:11,223 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:11,223 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:11,224 INFO L85 PathProgramCache]: Analyzing trace with hash -523767063, now seen corresponding path program 17 times [2025-03-09 06:57:11,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:11,224 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1605881285] [2025-03-09 06:57:11,224 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:11,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:11,229 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 40 statements into 10 equivalence classes. [2025-03-09 06:57:11,249 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 06:57:11,249 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2025-03-09 06:57:11,249 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:11,582 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 108 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:11,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:11,582 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1605881285] [2025-03-09 06:57:11,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1605881285] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:11,582 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [828263638] [2025-03-09 06:57:11,583 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:11,583 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:11,583 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:11,585 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:11,586 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2025-03-09 06:57:11,628 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 40 statements into 10 equivalence classes. [2025-03-09 06:57:11,675 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 06:57:11,675 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2025-03-09 06:57:11,675 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:11,676 INFO L256 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 22 conjuncts are in the unsatisfiable core [2025-03-09 06:57:11,677 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:12,042 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 117 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:12,042 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:12,274 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 117 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:12,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [828263638] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:12,274 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:12,274 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21, 21] total 42 [2025-03-09 06:57:12,275 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647621447] [2025-03-09 06:57:12,275 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:12,308 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:12,309 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2025-03-09 06:57:12,309 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=318, Invalid=1488, Unknown=0, NotChecked=0, Total=1806 [2025-03-09 06:57:12,310 INFO L87 Difference]: Start difference. First operand 73 states and 85 transitions. cyclomatic complexity: 15 Second operand has 43 states, 42 states have (on average 1.9285714285714286) internal successors, (81), 43 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:13,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:13,102 INFO L93 Difference]: Finished difference Result 310 states and 361 transitions. [2025-03-09 06:57:13,102 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 310 states and 361 transitions. [2025-03-09 06:57:13,103 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:13,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 310 states to 145 states and 169 transitions. [2025-03-09 06:57:13,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 135 [2025-03-09 06:57:13,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 135 [2025-03-09 06:57:13,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145 states and 169 transitions. [2025-03-09 06:57:13,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:13,105 INFO L218 hiAutomatonCegarLoop]: Abstraction has 145 states and 169 transitions. [2025-03-09 06:57:13,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states and 169 transitions. [2025-03-09 06:57:13,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 80. [2025-03-09 06:57:13,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.1625) internal successors, (93), 79 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:13,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 93 transitions. [2025-03-09 06:57:13,107 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 93 transitions. [2025-03-09 06:57:13,110 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2025-03-09 06:57:13,110 INFO L432 stractBuchiCegarLoop]: Abstraction has 80 states and 93 transitions. [2025-03-09 06:57:13,110 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-09 06:57:13,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 93 transitions. [2025-03-09 06:57:13,111 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:13,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:13,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:13,111 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 9, 9, 1, 1, 1] [2025-03-09 06:57:13,111 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:13,111 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:13,112 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:13,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:13,113 INFO L85 PathProgramCache]: Analyzing trace with hash -814516985, now seen corresponding path program 18 times [2025-03-09 06:57:13,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:13,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558853419] [2025-03-09 06:57:13,113 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:57:13,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:13,122 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 41 statements into 10 equivalence classes. [2025-03-09 06:57:13,176 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) and asserted 41 of 41 statements. [2025-03-09 06:57:13,176 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2025-03-09 06:57:13,176 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:13,177 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:13,180 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-09 06:57:13,204 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-09 06:57:13,204 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:13,204 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:13,208 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:13,208 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:13,209 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 11 times [2025-03-09 06:57:13,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:13,209 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636715605] [2025-03-09 06:57:13,209 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:13,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:13,214 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:13,215 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:13,215 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 06:57:13,215 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:13,215 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:13,216 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:13,217 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:13,217 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:13,217 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:13,218 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:13,219 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:13,219 INFO L85 PathProgramCache]: Analyzing trace with hash 1289748767, now seen corresponding path program 19 times [2025-03-09 06:57:13,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:13,219 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881594488] [2025-03-09 06:57:13,219 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:13,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:13,228 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-09 06:57:13,234 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-09 06:57:13,236 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:13,236 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:13,558 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 117 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:13,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:13,558 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881594488] [2025-03-09 06:57:13,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881594488] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:13,558 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [140431299] [2025-03-09 06:57:13,558 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:13,558 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:13,559 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:13,560 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:13,562 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2025-03-09 06:57:13,608 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-09 06:57:13,635 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-09 06:57:13,635 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:13,635 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:13,637 INFO L256 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 24 conjuncts are in the unsatisfiable core [2025-03-09 06:57:13,638 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:13,879 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 145 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:13,879 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:14,029 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 145 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:14,029 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [140431299] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:14,029 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:14,029 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23] total 36 [2025-03-09 06:57:14,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1987410490] [2025-03-09 06:57:14,029 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:14,056 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:14,057 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2025-03-09 06:57:14,057 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=327, Invalid=1005, Unknown=0, NotChecked=0, Total=1332 [2025-03-09 06:57:14,057 INFO L87 Difference]: Start difference. First operand 80 states and 93 transitions. cyclomatic complexity: 16 Second operand has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 37 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:14,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:14,346 INFO L93 Difference]: Finished difference Result 280 states and 327 transitions. [2025-03-09 06:57:14,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 280 states and 327 transitions. [2025-03-09 06:57:14,348 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:14,349 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 280 states to 158 states and 184 transitions. [2025-03-09 06:57:14,349 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147 [2025-03-09 06:57:14,349 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147 [2025-03-09 06:57:14,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 184 transitions. [2025-03-09 06:57:14,349 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:14,349 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158 states and 184 transitions. [2025-03-09 06:57:14,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 184 transitions. [2025-03-09 06:57:14,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 87. [2025-03-09 06:57:14,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 87 states have (on average 1.160919540229885) internal successors, (101), 86 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:14,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 101 transitions. [2025-03-09 06:57:14,351 INFO L240 hiAutomatonCegarLoop]: Abstraction has 87 states and 101 transitions. [2025-03-09 06:57:14,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2025-03-09 06:57:14,354 INFO L432 stractBuchiCegarLoop]: Abstraction has 87 states and 101 transitions. [2025-03-09 06:57:14,354 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-09 06:57:14,354 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 101 transitions. [2025-03-09 06:57:14,355 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:14,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:14,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:14,355 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 10, 1, 1, 1] [2025-03-09 06:57:14,355 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:14,355 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:14,357 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:14,358 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:14,358 INFO L85 PathProgramCache]: Analyzing trace with hash 396444733, now seen corresponding path program 20 times [2025-03-09 06:57:14,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:14,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145458144] [2025-03-09 06:57:14,358 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:57:14,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:14,364 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 45 statements into 2 equivalence classes. [2025-03-09 06:57:14,396 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 45 of 45 statements. [2025-03-09 06:57:14,396 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-09 06:57:14,397 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:14,397 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:14,400 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 45 statements into 1 equivalence classes. [2025-03-09 06:57:14,416 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 45 of 45 statements. [2025-03-09 06:57:14,416 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:14,416 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:14,421 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:14,421 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:14,421 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 12 times [2025-03-09 06:57:14,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:14,421 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562957079] [2025-03-09 06:57:14,421 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:57:14,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:14,424 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:14,425 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:14,425 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 06:57:14,425 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:14,425 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:14,425 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:14,426 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:14,426 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:14,426 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:14,428 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:14,428 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:14,428 INFO L85 PathProgramCache]: Analyzing trace with hash -674996695, now seen corresponding path program 21 times [2025-03-09 06:57:14,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:14,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680995147] [2025-03-09 06:57:14,428 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:14,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:14,436 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 48 statements into 12 equivalence classes. [2025-03-09 06:57:14,522 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) and asserted 48 of 48 statements. [2025-03-09 06:57:14,522 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2025-03-09 06:57:14,522 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:14,876 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 145 proven. 97 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:14,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:14,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [680995147] [2025-03-09 06:57:14,876 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [680995147] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:14,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1987522854] [2025-03-09 06:57:14,876 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:14,876 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:14,877 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:14,879 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:14,880 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2025-03-09 06:57:14,928 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 48 statements into 12 equivalence classes. [2025-03-09 06:57:15,104 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) and asserted 48 of 48 statements. [2025-03-09 06:57:15,104 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2025-03-09 06:57:15,104 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:15,106 INFO L256 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-03-09 06:57:15,107 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:15,400 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 176 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:15,400 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:15,583 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 176 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:15,583 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1987522854] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:15,583 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:15,583 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 39 [2025-03-09 06:57:15,583 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2093657732] [2025-03-09 06:57:15,583 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:15,608 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:15,609 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2025-03-09 06:57:15,609 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=380, Invalid=1180, Unknown=0, NotChecked=0, Total=1560 [2025-03-09 06:57:15,609 INFO L87 Difference]: Start difference. First operand 87 states and 101 transitions. cyclomatic complexity: 17 Second operand has 40 states, 39 states have (on average 2.282051282051282) internal successors, (89), 40 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:15,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:15,884 INFO L93 Difference]: Finished difference Result 305 states and 356 transitions. [2025-03-09 06:57:15,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 305 states and 356 transitions. [2025-03-09 06:57:15,885 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:15,886 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 305 states to 171 states and 199 transitions. [2025-03-09 06:57:15,886 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 159 [2025-03-09 06:57:15,886 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 159 [2025-03-09 06:57:15,886 INFO L73 IsDeterministic]: Start isDeterministic. Operand 171 states and 199 transitions. [2025-03-09 06:57:15,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:15,886 INFO L218 hiAutomatonCegarLoop]: Abstraction has 171 states and 199 transitions. [2025-03-09 06:57:15,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states and 199 transitions. [2025-03-09 06:57:15,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 94. [2025-03-09 06:57:15,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 94 states, 94 states have (on average 1.1595744680851063) internal successors, (109), 93 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:15,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 109 transitions. [2025-03-09 06:57:15,889 INFO L240 hiAutomatonCegarLoop]: Abstraction has 94 states and 109 transitions. [2025-03-09 06:57:15,892 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2025-03-09 06:57:15,893 INFO L432 stractBuchiCegarLoop]: Abstraction has 94 states and 109 transitions. [2025-03-09 06:57:15,893 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-09 06:57:15,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94 states and 109 transitions. [2025-03-09 06:57:15,893 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:15,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:15,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:15,894 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 11, 1, 1, 1] [2025-03-09 06:57:15,895 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:15,895 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:15,895 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:15,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:15,896 INFO L85 PathProgramCache]: Analyzing trace with hash 198369863, now seen corresponding path program 22 times [2025-03-09 06:57:15,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:15,896 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872107578] [2025-03-09 06:57:15,896 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:57:15,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:15,903 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 49 statements into 2 equivalence classes. [2025-03-09 06:57:15,937 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 49 of 49 statements. [2025-03-09 06:57:15,937 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:57:15,937 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:15,937 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:15,940 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-03-09 06:57:15,963 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-03-09 06:57:15,964 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:15,964 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:15,970 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:15,971 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:15,971 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 13 times [2025-03-09 06:57:15,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:15,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [191267117] [2025-03-09 06:57:15,972 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:15,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:15,974 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:15,974 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:15,975 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:15,975 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:15,975 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:15,975 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:15,976 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:15,976 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:15,976 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:15,977 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:15,977 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:15,977 INFO L85 PathProgramCache]: Analyzing trace with hash -238384161, now seen corresponding path program 23 times [2025-03-09 06:57:15,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:15,978 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815586958] [2025-03-09 06:57:15,978 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:15,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:15,984 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 52 statements into 13 equivalence classes. [2025-03-09 06:57:16,006 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) and asserted 52 of 52 statements. [2025-03-09 06:57:16,006 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2025-03-09 06:57:16,006 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:16,446 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:16,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:16,447 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815586958] [2025-03-09 06:57:16,447 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815586958] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:16,447 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1607215926] [2025-03-09 06:57:16,447 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:16,447 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:16,447 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:16,449 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:16,450 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2025-03-09 06:57:16,502 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 52 statements into 13 equivalence classes. [2025-03-09 06:57:16,590 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) and asserted 52 of 52 statements. [2025-03-09 06:57:16,590 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2025-03-09 06:57:16,590 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:16,592 INFO L256 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 28 conjuncts are in the unsatisfiable core [2025-03-09 06:57:16,593 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:16,878 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:16,878 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:17,092 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:17,093 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1607215926] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:17,093 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:17,093 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27] total 40 [2025-03-09 06:57:17,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1069857370] [2025-03-09 06:57:17,093 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:17,121 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:17,121 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2025-03-09 06:57:17,121 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=404, Invalid=1236, Unknown=0, NotChecked=0, Total=1640 [2025-03-09 06:57:17,122 INFO L87 Difference]: Start difference. First operand 94 states and 109 transitions. cyclomatic complexity: 18 Second operand has 41 states, 40 states have (on average 2.25) internal successors, (90), 41 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:17,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:17,430 INFO L93 Difference]: Finished difference Result 330 states and 385 transitions. [2025-03-09 06:57:17,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 330 states and 385 transitions. [2025-03-09 06:57:17,431 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:17,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 330 states to 184 states and 214 transitions. [2025-03-09 06:57:17,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 171 [2025-03-09 06:57:17,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 171 [2025-03-09 06:57:17,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 184 states and 214 transitions. [2025-03-09 06:57:17,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:17,433 INFO L218 hiAutomatonCegarLoop]: Abstraction has 184 states and 214 transitions. [2025-03-09 06:57:17,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states and 214 transitions. [2025-03-09 06:57:17,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 101. [2025-03-09 06:57:17,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 101 states have (on average 1.1584158415841583) internal successors, (117), 100 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:17,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 117 transitions. [2025-03-09 06:57:17,435 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101 states and 117 transitions. [2025-03-09 06:57:17,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2025-03-09 06:57:17,438 INFO L432 stractBuchiCegarLoop]: Abstraction has 101 states and 117 transitions. [2025-03-09 06:57:17,438 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-09 06:57:17,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101 states and 117 transitions. [2025-03-09 06:57:17,439 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:17,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:17,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:17,439 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 12, 12, 1, 1, 1] [2025-03-09 06:57:17,439 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:17,439 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:17,439 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:17,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:17,440 INFO L85 PathProgramCache]: Analyzing trace with hash -1264725763, now seen corresponding path program 24 times [2025-03-09 06:57:17,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:17,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [24097551] [2025-03-09 06:57:17,440 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:57:17,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:17,447 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 53 statements into 13 equivalence classes. [2025-03-09 06:57:17,504 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) and asserted 53 of 53 statements. [2025-03-09 06:57:17,504 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2025-03-09 06:57:17,504 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:17,505 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:17,508 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 53 statements into 1 equivalence classes. [2025-03-09 06:57:17,528 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 53 of 53 statements. [2025-03-09 06:57:17,529 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:17,529 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:17,534 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:17,535 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:17,535 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 14 times [2025-03-09 06:57:17,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:17,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876699972] [2025-03-09 06:57:17,535 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:57:17,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:17,537 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:17,538 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:17,538 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 06:57:17,538 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:17,538 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:17,539 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:17,539 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:17,539 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:17,540 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:17,541 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:17,541 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:17,541 INFO L85 PathProgramCache]: Analyzing trace with hash -1992058519, now seen corresponding path program 25 times [2025-03-09 06:57:17,541 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:17,541 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [156985585] [2025-03-09 06:57:17,541 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:17,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:17,551 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-03-09 06:57:17,556 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-03-09 06:57:17,557 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:17,557 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:17,994 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 210 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:17,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:17,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [156985585] [2025-03-09 06:57:17,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [156985585] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:17,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1749993850] [2025-03-09 06:57:17,995 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:17,995 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:17,995 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:17,997 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:18,000 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2025-03-09 06:57:18,057 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-03-09 06:57:18,084 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-03-09 06:57:18,084 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:18,084 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:18,086 INFO L256 TraceCheckSpWp]: Trace formula consists of 314 conjuncts, 30 conjuncts are in the unsatisfiable core [2025-03-09 06:57:18,087 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:18,433 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 247 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:18,434 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:18,715 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 247 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:18,715 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1749993850] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:18,715 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:18,716 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29] total 45 [2025-03-09 06:57:18,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385159737] [2025-03-09 06:57:18,716 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:18,745 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:18,746 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2025-03-09 06:57:18,746 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=498, Invalid=1572, Unknown=0, NotChecked=0, Total=2070 [2025-03-09 06:57:18,747 INFO L87 Difference]: Start difference. First operand 101 states and 117 transitions. cyclomatic complexity: 19 Second operand has 46 states, 45 states have (on average 2.2888888888888888) internal successors, (103), 46 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:19,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:19,194 INFO L93 Difference]: Finished difference Result 355 states and 414 transitions. [2025-03-09 06:57:19,194 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 355 states and 414 transitions. [2025-03-09 06:57:19,195 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:19,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 355 states to 197 states and 229 transitions. [2025-03-09 06:57:19,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 183 [2025-03-09 06:57:19,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 183 [2025-03-09 06:57:19,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 197 states and 229 transitions. [2025-03-09 06:57:19,197 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:19,197 INFO L218 hiAutomatonCegarLoop]: Abstraction has 197 states and 229 transitions. [2025-03-09 06:57:19,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states and 229 transitions. [2025-03-09 06:57:19,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 108. [2025-03-09 06:57:19,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.1574074074074074) internal successors, (125), 107 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:19,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 125 transitions. [2025-03-09 06:57:19,199 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 125 transitions. [2025-03-09 06:57:19,201 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2025-03-09 06:57:19,201 INFO L432 stractBuchiCegarLoop]: Abstraction has 108 states and 125 transitions. [2025-03-09 06:57:19,201 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-09 06:57:19,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 125 transitions. [2025-03-09 06:57:19,202 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:19,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:19,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:19,202 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [14, 14, 13, 13, 1, 1, 1] [2025-03-09 06:57:19,202 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:19,202 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:19,203 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:19,203 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:19,203 INFO L85 PathProgramCache]: Analyzing trace with hash 2022907783, now seen corresponding path program 26 times [2025-03-09 06:57:19,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:19,203 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276434955] [2025-03-09 06:57:19,203 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:57:19,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:19,211 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 57 statements into 2 equivalence classes. [2025-03-09 06:57:19,235 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 57 of 57 statements. [2025-03-09 06:57:19,235 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-09 06:57:19,235 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:19,235 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:19,238 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 57 statements into 1 equivalence classes. [2025-03-09 06:57:19,265 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 57 of 57 statements. [2025-03-09 06:57:19,265 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:19,265 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:19,269 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:19,271 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:19,271 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 15 times [2025-03-09 06:57:19,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:19,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209974828] [2025-03-09 06:57:19,271 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:19,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:19,273 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:19,274 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:19,274 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 06:57:19,274 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:19,274 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:19,274 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:19,275 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:19,275 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:19,275 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:19,276 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:19,276 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:19,276 INFO L85 PathProgramCache]: Analyzing trace with hash 1759659679, now seen corresponding path program 27 times [2025-03-09 06:57:19,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:19,276 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892351740] [2025-03-09 06:57:19,276 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:19,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:19,285 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 60 statements into 15 equivalence classes. [2025-03-09 06:57:19,393 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) and asserted 60 of 60 statements. [2025-03-09 06:57:19,393 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2025-03-09 06:57:19,393 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:19,875 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 247 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:19,875 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:19,875 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [892351740] [2025-03-09 06:57:19,875 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [892351740] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:19,875 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1089640371] [2025-03-09 06:57:19,875 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:19,875 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:19,875 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:19,877 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:19,879 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2025-03-09 06:57:19,944 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 60 statements into 15 equivalence classes. [2025-03-09 06:57:20,371 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) and asserted 60 of 60 statements. [2025-03-09 06:57:20,372 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2025-03-09 06:57:20,372 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:20,377 INFO L256 TraceCheckSpWp]: Trace formula consists of 335 conjuncts, 32 conjuncts are in the unsatisfiable core [2025-03-09 06:57:20,378 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:20,802 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 287 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:20,802 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:21,098 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 287 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:21,099 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1089640371] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:21,099 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:21,099 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31] total 48 [2025-03-09 06:57:21,099 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285327496] [2025-03-09 06:57:21,099 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:21,130 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:21,130 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2025-03-09 06:57:21,131 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=563, Invalid=1789, Unknown=0, NotChecked=0, Total=2352 [2025-03-09 06:57:21,131 INFO L87 Difference]: Start difference. First operand 108 states and 125 transitions. cyclomatic complexity: 20 Second operand has 49 states, 48 states have (on average 2.2916666666666665) internal successors, (110), 49 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:21,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:21,518 INFO L93 Difference]: Finished difference Result 380 states and 443 transitions. [2025-03-09 06:57:21,518 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 380 states and 443 transitions. [2025-03-09 06:57:21,519 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:21,520 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 380 states to 210 states and 244 transitions. [2025-03-09 06:57:21,520 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-03-09 06:57:21,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2025-03-09 06:57:21,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 210 states and 244 transitions. [2025-03-09 06:57:21,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:21,521 INFO L218 hiAutomatonCegarLoop]: Abstraction has 210 states and 244 transitions. [2025-03-09 06:57:21,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states and 244 transitions. [2025-03-09 06:57:21,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 115. [2025-03-09 06:57:21,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 115 states have (on average 1.1565217391304348) internal successors, (133), 114 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:21,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 133 transitions. [2025-03-09 06:57:21,523 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115 states and 133 transitions. [2025-03-09 06:57:21,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2025-03-09 06:57:21,524 INFO L432 stractBuchiCegarLoop]: Abstraction has 115 states and 133 transitions. [2025-03-09 06:57:21,524 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-09 06:57:21,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115 states and 133 transitions. [2025-03-09 06:57:21,525 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:21,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:21,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:21,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 14, 14, 1, 1, 1] [2025-03-09 06:57:21,525 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:21,525 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:21,526 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:21,526 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:21,526 INFO L85 PathProgramCache]: Analyzing trace with hash 2057670077, now seen corresponding path program 28 times [2025-03-09 06:57:21,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:21,526 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1167757844] [2025-03-09 06:57:21,526 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:57:21,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:21,538 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 61 statements into 2 equivalence classes. [2025-03-09 06:57:21,565 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 61 of 61 statements. [2025-03-09 06:57:21,565 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:57:21,565 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:21,565 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:21,568 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 61 statements into 1 equivalence classes. [2025-03-09 06:57:21,587 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 61 of 61 statements. [2025-03-09 06:57:21,588 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:21,588 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:21,592 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:21,593 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:21,593 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 16 times [2025-03-09 06:57:21,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:21,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742578997] [2025-03-09 06:57:21,593 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:57:21,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:21,595 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-03-09 06:57:21,596 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:21,596 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:57:21,596 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:21,596 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:21,596 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:21,597 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:21,597 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:21,597 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:21,598 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:21,598 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:21,598 INFO L85 PathProgramCache]: Analyzing trace with hash -2018925399, now seen corresponding path program 29 times [2025-03-09 06:57:21,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:21,599 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [292938990] [2025-03-09 06:57:21,599 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:21,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:21,606 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 64 statements into 16 equivalence classes. [2025-03-09 06:57:21,650 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) and asserted 64 of 64 statements. [2025-03-09 06:57:21,650 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2025-03-09 06:57:21,650 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:22,190 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:22,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:22,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [292938990] [2025-03-09 06:57:22,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [292938990] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:22,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [551793431] [2025-03-09 06:57:22,190 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:22,191 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:22,191 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:22,193 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:22,194 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2025-03-09 06:57:22,263 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 64 statements into 16 equivalence classes. [2025-03-09 06:57:22,410 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) and asserted 64 of 64 statements. [2025-03-09 06:57:22,410 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2025-03-09 06:57:22,410 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:22,413 INFO L256 TraceCheckSpWp]: Trace formula consists of 356 conjuncts, 34 conjuncts are in the unsatisfiable core [2025-03-09 06:57:22,414 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:22,855 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:22,855 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:23,181 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:23,181 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [551793431] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:23,181 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:23,181 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33] total 49 [2025-03-09 06:57:23,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2132409442] [2025-03-09 06:57:23,181 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:23,206 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:23,206 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2025-03-09 06:57:23,206 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=593, Invalid=1857, Unknown=0, NotChecked=0, Total=2450 [2025-03-09 06:57:23,207 INFO L87 Difference]: Start difference. First operand 115 states and 133 transitions. cyclomatic complexity: 21 Second operand has 50 states, 49 states have (on average 2.2653061224489797) internal successors, (111), 50 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:23,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:23,625 INFO L93 Difference]: Finished difference Result 405 states and 472 transitions. [2025-03-09 06:57:23,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 405 states and 472 transitions. [2025-03-09 06:57:23,626 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:23,627 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 405 states to 223 states and 259 transitions. [2025-03-09 06:57:23,627 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 207 [2025-03-09 06:57:23,627 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 207 [2025-03-09 06:57:23,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223 states and 259 transitions. [2025-03-09 06:57:23,628 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:23,628 INFO L218 hiAutomatonCegarLoop]: Abstraction has 223 states and 259 transitions. [2025-03-09 06:57:23,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states and 259 transitions. [2025-03-09 06:57:23,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 122. [2025-03-09 06:57:23,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122 states, 122 states have (on average 1.1557377049180328) internal successors, (141), 121 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:23,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 141 transitions. [2025-03-09 06:57:23,630 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122 states and 141 transitions. [2025-03-09 06:57:23,630 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2025-03-09 06:57:23,630 INFO L432 stractBuchiCegarLoop]: Abstraction has 122 states and 141 transitions. [2025-03-09 06:57:23,630 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-09 06:57:23,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122 states and 141 transitions. [2025-03-09 06:57:23,631 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:23,631 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:23,631 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:23,631 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [16, 16, 15, 15, 1, 1, 1] [2025-03-09 06:57:23,632 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:23,632 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:23,632 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:23,632 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:23,632 INFO L85 PathProgramCache]: Analyzing trace with hash -367514425, now seen corresponding path program 30 times [2025-03-09 06:57:23,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:23,632 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121944477] [2025-03-09 06:57:23,632 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:57:23,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:23,641 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 65 statements into 16 equivalence classes. [2025-03-09 06:57:23,737 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) and asserted 65 of 65 statements. [2025-03-09 06:57:23,737 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2025-03-09 06:57:23,737 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:23,737 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:23,741 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 65 statements into 1 equivalence classes. [2025-03-09 06:57:23,775 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 65 of 65 statements. [2025-03-09 06:57:23,775 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:23,775 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:23,779 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:23,780 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:23,780 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 17 times [2025-03-09 06:57:23,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:23,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484825364] [2025-03-09 06:57:23,780 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:23,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:23,782 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:23,782 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:23,782 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 06:57:23,782 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:23,782 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:23,783 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:23,783 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:23,783 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:23,783 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:23,784 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:23,785 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:23,785 INFO L85 PathProgramCache]: Analyzing trace with hash -750571169, now seen corresponding path program 31 times [2025-03-09 06:57:23,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:23,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082948758] [2025-03-09 06:57:23,785 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:23,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:23,793 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 68 statements into 1 equivalence classes. [2025-03-09 06:57:23,800 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 68 of 68 statements. [2025-03-09 06:57:23,800 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:23,800 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:24,378 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 330 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:24,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:24,379 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2082948758] [2025-03-09 06:57:24,379 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2082948758] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:24,380 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [529220583] [2025-03-09 06:57:24,380 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:24,380 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:24,380 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:24,382 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:24,384 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2025-03-09 06:57:24,459 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 68 statements into 1 equivalence classes. [2025-03-09 06:57:24,491 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 68 of 68 statements. [2025-03-09 06:57:24,491 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:24,491 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:24,492 INFO L256 TraceCheckSpWp]: Trace formula consists of 377 conjuncts, 36 conjuncts are in the unsatisfiable core [2025-03-09 06:57:24,494 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:24,915 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 376 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:24,915 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:25,234 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 376 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:25,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [529220583] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:25,234 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:25,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35] total 54 [2025-03-09 06:57:25,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2145650629] [2025-03-09 06:57:25,234 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:25,258 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:25,259 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2025-03-09 06:57:25,260 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=705, Invalid=2265, Unknown=0, NotChecked=0, Total=2970 [2025-03-09 06:57:25,260 INFO L87 Difference]: Start difference. First operand 122 states and 141 transitions. cyclomatic complexity: 22 Second operand has 55 states, 54 states have (on average 2.2962962962962963) internal successors, (124), 55 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:25,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:25,716 INFO L93 Difference]: Finished difference Result 430 states and 501 transitions. [2025-03-09 06:57:25,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 501 transitions. [2025-03-09 06:57:25,718 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:25,719 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 236 states and 274 transitions. [2025-03-09 06:57:25,719 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 219 [2025-03-09 06:57:25,719 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 219 [2025-03-09 06:57:25,719 INFO L73 IsDeterministic]: Start isDeterministic. Operand 236 states and 274 transitions. [2025-03-09 06:57:25,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:25,719 INFO L218 hiAutomatonCegarLoop]: Abstraction has 236 states and 274 transitions. [2025-03-09 06:57:25,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states and 274 transitions. [2025-03-09 06:57:25,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 129. [2025-03-09 06:57:25,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 129 states, 129 states have (on average 1.1550387596899225) internal successors, (149), 128 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:25,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 149 transitions. [2025-03-09 06:57:25,723 INFO L240 hiAutomatonCegarLoop]: Abstraction has 129 states and 149 transitions. [2025-03-09 06:57:25,726 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2025-03-09 06:57:25,726 INFO L432 stractBuchiCegarLoop]: Abstraction has 129 states and 149 transitions. [2025-03-09 06:57:25,726 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-09 06:57:25,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 129 states and 149 transitions. [2025-03-09 06:57:25,727 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:25,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:25,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:25,727 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [17, 17, 16, 16, 1, 1, 1] [2025-03-09 06:57:25,727 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:25,727 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:25,728 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:25,728 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:25,728 INFO L85 PathProgramCache]: Analyzing trace with hash -858490243, now seen corresponding path program 32 times [2025-03-09 06:57:25,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:25,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [985003941] [2025-03-09 06:57:25,728 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:57:25,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:25,738 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 69 statements into 2 equivalence classes. [2025-03-09 06:57:25,792 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 69 of 69 statements. [2025-03-09 06:57:25,792 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-09 06:57:25,792 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:25,792 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:25,795 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 69 statements into 1 equivalence classes. [2025-03-09 06:57:25,821 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 69 of 69 statements. [2025-03-09 06:57:25,821 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:25,821 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:25,826 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:25,826 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:25,827 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 18 times [2025-03-09 06:57:25,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:25,827 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [921326837] [2025-03-09 06:57:25,827 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:57:25,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:25,829 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:25,829 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:25,829 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 06:57:25,830 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:25,830 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:25,830 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:25,830 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:25,830 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:25,830 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:25,832 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:25,832 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:25,832 INFO L85 PathProgramCache]: Analyzing trace with hash 1247444969, now seen corresponding path program 33 times [2025-03-09 06:57:25,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:25,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001252192] [2025-03-09 06:57:25,832 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:25,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:25,841 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 72 statements into 18 equivalence classes. [2025-03-09 06:57:25,966 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) and asserted 72 of 72 statements. [2025-03-09 06:57:25,966 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2025-03-09 06:57:25,966 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:26,657 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 376 proven. 202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:26,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:26,658 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2001252192] [2025-03-09 06:57:26,658 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2001252192] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:26,658 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1802888856] [2025-03-09 06:57:26,658 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:26,658 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:26,658 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:26,660 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:26,661 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2025-03-09 06:57:26,734 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 72 statements into 18 equivalence classes. [2025-03-09 06:57:27,148 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) and asserted 72 of 72 statements. [2025-03-09 06:57:27,148 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2025-03-09 06:57:27,148 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:27,152 INFO L256 TraceCheckSpWp]: Trace formula consists of 398 conjuncts, 38 conjuncts are in the unsatisfiable core [2025-03-09 06:57:27,153 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:27,599 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 425 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:27,599 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:27,968 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 425 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:27,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1802888856] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:27,968 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:27,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37] total 57 [2025-03-09 06:57:27,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [962045776] [2025-03-09 06:57:27,968 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:28,000 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:28,001 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2025-03-09 06:57:28,002 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=782, Invalid=2524, Unknown=0, NotChecked=0, Total=3306 [2025-03-09 06:57:28,002 INFO L87 Difference]: Start difference. First operand 129 states and 149 transitions. cyclomatic complexity: 23 Second operand has 58 states, 57 states have (on average 2.2982456140350878) internal successors, (131), 58 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:28,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:28,509 INFO L93 Difference]: Finished difference Result 455 states and 530 transitions. [2025-03-09 06:57:28,509 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 455 states and 530 transitions. [2025-03-09 06:57:28,511 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:28,511 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 455 states to 249 states and 289 transitions. [2025-03-09 06:57:28,511 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 231 [2025-03-09 06:57:28,512 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 231 [2025-03-09 06:57:28,512 INFO L73 IsDeterministic]: Start isDeterministic. Operand 249 states and 289 transitions. [2025-03-09 06:57:28,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:28,512 INFO L218 hiAutomatonCegarLoop]: Abstraction has 249 states and 289 transitions. [2025-03-09 06:57:28,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states and 289 transitions. [2025-03-09 06:57:28,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 136. [2025-03-09 06:57:28,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 136 states, 136 states have (on average 1.1544117647058822) internal successors, (157), 135 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:28,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 157 transitions. [2025-03-09 06:57:28,514 INFO L240 hiAutomatonCegarLoop]: Abstraction has 136 states and 157 transitions. [2025-03-09 06:57:28,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2025-03-09 06:57:28,515 INFO L432 stractBuchiCegarLoop]: Abstraction has 136 states and 157 transitions. [2025-03-09 06:57:28,515 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-09 06:57:28,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 136 states and 157 transitions. [2025-03-09 06:57:28,515 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:28,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:28,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:28,516 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [18, 18, 17, 17, 1, 1, 1] [2025-03-09 06:57:28,516 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:28,516 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:28,516 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:28,516 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:28,516 INFO L85 PathProgramCache]: Analyzing trace with hash 432409095, now seen corresponding path program 34 times [2025-03-09 06:57:28,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:28,517 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2110965700] [2025-03-09 06:57:28,517 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:57:28,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:28,526 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 73 statements into 2 equivalence classes. [2025-03-09 06:57:28,564 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 73 of 73 statements. [2025-03-09 06:57:28,564 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:57:28,564 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:28,565 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:28,568 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 73 statements into 1 equivalence classes. [2025-03-09 06:57:28,597 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 73 of 73 statements. [2025-03-09 06:57:28,597 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:28,597 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:28,602 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:28,603 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:28,603 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 19 times [2025-03-09 06:57:28,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:28,603 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949105659] [2025-03-09 06:57:28,603 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:28,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:28,605 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:28,605 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:28,606 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:28,606 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:28,606 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:28,606 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:28,606 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:28,606 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:28,606 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:28,608 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:28,608 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:28,608 INFO L85 PathProgramCache]: Analyzing trace with hash 1292454943, now seen corresponding path program 35 times [2025-03-09 06:57:28,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:28,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [237197166] [2025-03-09 06:57:28,608 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:28,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:28,617 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 76 statements into 19 equivalence classes. [2025-03-09 06:57:28,641 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) and asserted 76 of 76 statements. [2025-03-09 06:57:28,642 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2025-03-09 06:57:28,642 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:29,217 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:29,217 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:29,218 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [237197166] [2025-03-09 06:57:29,218 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [237197166] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:29,218 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1801435116] [2025-03-09 06:57:29,218 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:29,218 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:29,218 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:29,220 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:29,221 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2025-03-09 06:57:29,338 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 76 statements into 19 equivalence classes. [2025-03-09 06:57:29,639 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) and asserted 76 of 76 statements. [2025-03-09 06:57:29,639 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2025-03-09 06:57:29,639 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:29,643 INFO L256 TraceCheckSpWp]: Trace formula consists of 419 conjuncts, 40 conjuncts are in the unsatisfiable core [2025-03-09 06:57:29,644 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:30,254 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:30,254 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:30,653 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:30,653 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1801435116] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:30,653 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:30,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39] total 58 [2025-03-09 06:57:30,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [968612940] [2025-03-09 06:57:30,654 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:30,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:30,689 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2025-03-09 06:57:30,690 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=818, Invalid=2604, Unknown=0, NotChecked=0, Total=3422 [2025-03-09 06:57:30,690 INFO L87 Difference]: Start difference. First operand 136 states and 157 transitions. cyclomatic complexity: 24 Second operand has 59 states, 58 states have (on average 2.2758620689655173) internal successors, (132), 59 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:31,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:31,279 INFO L93 Difference]: Finished difference Result 480 states and 559 transitions. [2025-03-09 06:57:31,279 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 559 transitions. [2025-03-09 06:57:31,281 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:31,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 262 states and 304 transitions. [2025-03-09 06:57:31,282 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 243 [2025-03-09 06:57:31,282 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 243 [2025-03-09 06:57:31,282 INFO L73 IsDeterministic]: Start isDeterministic. Operand 262 states and 304 transitions. [2025-03-09 06:57:31,282 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:31,282 INFO L218 hiAutomatonCegarLoop]: Abstraction has 262 states and 304 transitions. [2025-03-09 06:57:31,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 262 states and 304 transitions. [2025-03-09 06:57:31,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 262 to 143. [2025-03-09 06:57:31,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 143 states, 143 states have (on average 1.1538461538461537) internal successors, (165), 142 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:31,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 165 transitions. [2025-03-09 06:57:31,284 INFO L240 hiAutomatonCegarLoop]: Abstraction has 143 states and 165 transitions. [2025-03-09 06:57:31,285 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2025-03-09 06:57:31,285 INFO L432 stractBuchiCegarLoop]: Abstraction has 143 states and 165 transitions. [2025-03-09 06:57:31,285 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-03-09 06:57:31,285 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 143 states and 165 transitions. [2025-03-09 06:57:31,286 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:31,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:31,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:31,286 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [19, 19, 18, 18, 1, 1, 1] [2025-03-09 06:57:31,286 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:31,286 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:31,286 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:31,287 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:31,287 INFO L85 PathProgramCache]: Analyzing trace with hash 155621181, now seen corresponding path program 36 times [2025-03-09 06:57:31,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:31,287 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [802024512] [2025-03-09 06:57:31,287 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:57:31,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:31,297 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 77 statements into 19 equivalence classes. [2025-03-09 06:57:31,389 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) and asserted 77 of 77 statements. [2025-03-09 06:57:31,389 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2025-03-09 06:57:31,389 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:31,389 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:31,394 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-09 06:57:31,425 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-09 06:57:31,426 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:31,426 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:31,431 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:31,432 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:31,432 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 20 times [2025-03-09 06:57:31,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:31,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1258516394] [2025-03-09 06:57:31,432 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:57:31,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:31,434 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:31,435 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:31,435 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 06:57:31,435 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:31,435 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:31,435 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:31,435 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:31,435 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:31,436 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:31,437 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:31,437 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:31,438 INFO L85 PathProgramCache]: Analyzing trace with hash 1840917289, now seen corresponding path program 37 times [2025-03-09 06:57:31,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:31,438 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [324655891] [2025-03-09 06:57:31,438 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:31,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:31,447 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 06:57:31,455 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 06:57:31,455 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:31,455 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:32,092 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 477 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:32,092 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:32,092 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [324655891] [2025-03-09 06:57:32,092 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [324655891] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:32,092 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1840644658] [2025-03-09 06:57:32,092 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:32,092 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:32,092 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:32,094 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:32,095 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2025-03-09 06:57:32,178 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 06:57:32,215 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 06:57:32,215 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:32,216 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:32,218 INFO L256 TraceCheckSpWp]: Trace formula consists of 440 conjuncts, 42 conjuncts are in the unsatisfiable core [2025-03-09 06:57:32,219 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:32,784 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 532 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:32,784 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:33,175 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 532 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:33,175 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1840644658] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:33,175 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:33,175 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41, 41] total 63 [2025-03-09 06:57:33,175 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1475157042] [2025-03-09 06:57:33,175 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:33,205 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:33,205 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2025-03-09 06:57:33,206 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=948, Invalid=3084, Unknown=0, NotChecked=0, Total=4032 [2025-03-09 06:57:33,206 INFO L87 Difference]: Start difference. First operand 143 states and 165 transitions. cyclomatic complexity: 25 Second operand has 64 states, 63 states have (on average 2.3015873015873014) internal successors, (145), 64 states have internal predecessors, (145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:33,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:33,752 INFO L93 Difference]: Finished difference Result 505 states and 588 transitions. [2025-03-09 06:57:33,752 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 505 states and 588 transitions. [2025-03-09 06:57:33,753 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:33,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 505 states to 275 states and 319 transitions. [2025-03-09 06:57:33,754 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 255 [2025-03-09 06:57:33,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 255 [2025-03-09 06:57:33,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 275 states and 319 transitions. [2025-03-09 06:57:33,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:33,755 INFO L218 hiAutomatonCegarLoop]: Abstraction has 275 states and 319 transitions. [2025-03-09 06:57:33,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 275 states and 319 transitions. [2025-03-09 06:57:33,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 275 to 150. [2025-03-09 06:57:33,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 150 states, 150 states have (on average 1.1533333333333333) internal successors, (173), 149 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:33,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 173 transitions. [2025-03-09 06:57:33,757 INFO L240 hiAutomatonCegarLoop]: Abstraction has 150 states and 173 transitions. [2025-03-09 06:57:33,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2025-03-09 06:57:33,759 INFO L432 stractBuchiCegarLoop]: Abstraction has 150 states and 173 transitions. [2025-03-09 06:57:33,759 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-03-09 06:57:33,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 150 states and 173 transitions. [2025-03-09 06:57:33,760 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:33,760 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:33,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:33,761 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [20, 20, 19, 19, 1, 1, 1] [2025-03-09 06:57:33,761 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:33,761 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:33,761 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:33,761 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:33,762 INFO L85 PathProgramCache]: Analyzing trace with hash -436160697, now seen corresponding path program 38 times [2025-03-09 06:57:33,762 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:33,762 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177681263] [2025-03-09 06:57:33,762 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:57:33,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:33,774 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 81 statements into 2 equivalence classes. [2025-03-09 06:57:33,804 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 81 of 81 statements. [2025-03-09 06:57:33,804 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-09 06:57:33,804 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:33,805 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:33,809 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-09 06:57:33,846 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-09 06:57:33,846 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:33,846 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:33,853 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:33,854 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:33,854 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 21 times [2025-03-09 06:57:33,854 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:33,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [532834474] [2025-03-09 06:57:33,854 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:33,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:33,856 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:33,857 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:33,857 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 06:57:33,857 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:33,857 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:33,857 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:33,858 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:33,858 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:33,858 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:33,859 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:33,859 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:33,859 INFO L85 PathProgramCache]: Analyzing trace with hash -1387227425, now seen corresponding path program 39 times [2025-03-09 06:57:33,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:33,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320829263] [2025-03-09 06:57:33,860 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:33,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:33,870 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 84 statements into 21 equivalence classes. [2025-03-09 06:57:34,193 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) and asserted 84 of 84 statements. [2025-03-09 06:57:34,194 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2025-03-09 06:57:34,194 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:34,923 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 532 proven. 268 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:34,923 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:34,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320829263] [2025-03-09 06:57:34,923 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320829263] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:34,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [98890879] [2025-03-09 06:57:34,923 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:34,923 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:34,923 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:34,925 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:34,926 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2025-03-09 06:57:35,019 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 84 statements into 21 equivalence classes. [2025-03-09 06:57:35,866 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) and asserted 84 of 84 statements. [2025-03-09 06:57:35,866 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2025-03-09 06:57:35,866 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:35,870 INFO L256 TraceCheckSpWp]: Trace formula consists of 461 conjuncts, 44 conjuncts are in the unsatisfiable core [2025-03-09 06:57:35,872 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:36,444 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 590 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:36,444 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:36,886 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 590 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:36,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [98890879] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:36,886 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:36,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43, 43] total 66 [2025-03-09 06:57:36,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1964407170] [2025-03-09 06:57:36,886 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:36,911 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:36,911 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2025-03-09 06:57:36,912 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1037, Invalid=3385, Unknown=0, NotChecked=0, Total=4422 [2025-03-09 06:57:36,912 INFO L87 Difference]: Start difference. First operand 150 states and 173 transitions. cyclomatic complexity: 26 Second operand has 67 states, 66 states have (on average 2.303030303030303) internal successors, (152), 67 states have internal predecessors, (152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:37,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:37,574 INFO L93 Difference]: Finished difference Result 530 states and 617 transitions. [2025-03-09 06:57:37,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 530 states and 617 transitions. [2025-03-09 06:57:37,575 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:37,576 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 530 states to 288 states and 334 transitions. [2025-03-09 06:57:37,576 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 267 [2025-03-09 06:57:37,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 267 [2025-03-09 06:57:37,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 334 transitions. [2025-03-09 06:57:37,577 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:37,577 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 334 transitions. [2025-03-09 06:57:37,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 334 transitions. [2025-03-09 06:57:37,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 157. [2025-03-09 06:57:37,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 157 states, 157 states have (on average 1.1528662420382165) internal successors, (181), 156 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:37,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 181 transitions. [2025-03-09 06:57:37,579 INFO L240 hiAutomatonCegarLoop]: Abstraction has 157 states and 181 transitions. [2025-03-09 06:57:37,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2025-03-09 06:57:37,580 INFO L432 stractBuchiCegarLoop]: Abstraction has 157 states and 181 transitions. [2025-03-09 06:57:37,580 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-03-09 06:57:37,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 157 states and 181 transitions. [2025-03-09 06:57:37,580 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:37,580 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:37,580 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:37,580 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [21, 21, 20, 20, 1, 1, 1] [2025-03-09 06:57:37,581 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:37,581 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:37,581 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:37,581 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:37,581 INFO L85 PathProgramCache]: Analyzing trace with hash 1226302461, now seen corresponding path program 40 times [2025-03-09 06:57:37,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:37,581 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467165779] [2025-03-09 06:57:37,581 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:57:37,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:37,591 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 85 statements into 2 equivalence classes. [2025-03-09 06:57:37,636 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 85 of 85 statements. [2025-03-09 06:57:37,636 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:57:37,636 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:37,636 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:37,642 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 85 statements into 1 equivalence classes. [2025-03-09 06:57:37,679 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 85 of 85 statements. [2025-03-09 06:57:37,679 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:37,679 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:37,687 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:37,688 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:37,688 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 22 times [2025-03-09 06:57:37,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:37,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675705084] [2025-03-09 06:57:37,688 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:57:37,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:37,690 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-03-09 06:57:37,691 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:37,691 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:57:37,691 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:37,691 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:37,691 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:37,691 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:37,692 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:37,692 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:37,693 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:37,694 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:37,694 INFO L85 PathProgramCache]: Analyzing trace with hash -215177623, now seen corresponding path program 41 times [2025-03-09 06:57:37,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:37,694 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1537371436] [2025-03-09 06:57:37,694 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:37,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:37,705 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 88 statements into 22 equivalence classes. [2025-03-09 06:57:37,743 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) and asserted 88 of 88 statements. [2025-03-09 06:57:37,744 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2025-03-09 06:57:37,744 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:38,496 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:38,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:38,496 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1537371436] [2025-03-09 06:57:38,496 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1537371436] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:38,496 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1141669158] [2025-03-09 06:57:38,496 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:38,496 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:38,496 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:38,498 INFO L229 MonitoredProcess]: Starting monitored process 38 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:38,499 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2025-03-09 06:57:38,598 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 88 statements into 22 equivalence classes. [2025-03-09 06:57:39,608 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) and asserted 88 of 88 statements. [2025-03-09 06:57:39,609 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2025-03-09 06:57:39,609 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:39,613 INFO L256 TraceCheckSpWp]: Trace formula consists of 482 conjuncts, 46 conjuncts are in the unsatisfiable core [2025-03-09 06:57:39,615 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:40,261 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:40,261 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:40,726 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:40,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1141669158] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:40,726 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:40,726 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45, 45] total 67 [2025-03-09 06:57:40,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [466063139] [2025-03-09 06:57:40,726 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:40,751 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:40,751 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2025-03-09 06:57:40,752 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1079, Invalid=3477, Unknown=0, NotChecked=0, Total=4556 [2025-03-09 06:57:40,752 INFO L87 Difference]: Start difference. First operand 157 states and 181 transitions. cyclomatic complexity: 27 Second operand has 68 states, 67 states have (on average 2.283582089552239) internal successors, (153), 68 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:41,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:41,421 INFO L93 Difference]: Finished difference Result 555 states and 646 transitions. [2025-03-09 06:57:41,421 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 555 states and 646 transitions. [2025-03-09 06:57:41,423 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:41,423 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 555 states to 301 states and 349 transitions. [2025-03-09 06:57:41,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 279 [2025-03-09 06:57:41,424 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 279 [2025-03-09 06:57:41,424 INFO L73 IsDeterministic]: Start isDeterministic. Operand 301 states and 349 transitions. [2025-03-09 06:57:41,424 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:41,424 INFO L218 hiAutomatonCegarLoop]: Abstraction has 301 states and 349 transitions. [2025-03-09 06:57:41,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 301 states and 349 transitions. [2025-03-09 06:57:41,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 301 to 164. [2025-03-09 06:57:41,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 164 states, 164 states have (on average 1.1524390243902438) internal successors, (189), 163 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:41,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 189 transitions. [2025-03-09 06:57:41,426 INFO L240 hiAutomatonCegarLoop]: Abstraction has 164 states and 189 transitions. [2025-03-09 06:57:41,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2025-03-09 06:57:41,427 INFO L432 stractBuchiCegarLoop]: Abstraction has 164 states and 189 transitions. [2025-03-09 06:57:41,427 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-03-09 06:57:41,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 164 states and 189 transitions. [2025-03-09 06:57:41,427 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:41,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:41,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:41,428 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 21, 21, 1, 1, 1] [2025-03-09 06:57:41,428 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:41,428 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:41,428 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:41,428 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:41,428 INFO L85 PathProgramCache]: Analyzing trace with hash -1842596729, now seen corresponding path program 42 times [2025-03-09 06:57:41,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:41,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1006969904] [2025-03-09 06:57:41,429 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:57:41,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:41,439 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 89 statements into 22 equivalence classes. [2025-03-09 06:57:41,604 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) and asserted 89 of 89 statements. [2025-03-09 06:57:41,604 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2025-03-09 06:57:41,604 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:41,604 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:41,610 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-09 06:57:41,661 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-09 06:57:41,662 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:41,662 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:41,678 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:41,679 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:41,679 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 23 times [2025-03-09 06:57:41,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:41,679 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588652536] [2025-03-09 06:57:41,679 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:41,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:41,682 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:41,682 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:41,682 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 06:57:41,682 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:41,682 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:41,682 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:41,683 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:41,683 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:41,683 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:41,685 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:41,685 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:41,685 INFO L85 PathProgramCache]: Analyzing trace with hash 1177883039, now seen corresponding path program 43 times [2025-03-09 06:57:41,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:41,685 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1032388953] [2025-03-09 06:57:41,685 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:41,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:41,697 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes. [2025-03-09 06:57:41,705 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements. [2025-03-09 06:57:41,706 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:41,706 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:42,570 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 651 proven. 317 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:42,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:42,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1032388953] [2025-03-09 06:57:42,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1032388953] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:42,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2009706991] [2025-03-09 06:57:42,571 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:42,571 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:42,571 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:42,573 INFO L229 MonitoredProcess]: Starting monitored process 39 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:42,573 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2025-03-09 06:57:42,678 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes. [2025-03-09 06:57:42,715 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements. [2025-03-09 06:57:42,716 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:42,716 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:42,718 INFO L256 TraceCheckSpWp]: Trace formula consists of 503 conjuncts, 48 conjuncts are in the unsatisfiable core [2025-03-09 06:57:42,719 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:43,444 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 715 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:43,445 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:43,990 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 715 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:43,990 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2009706991] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:43,990 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:43,990 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47, 47] total 72 [2025-03-09 06:57:43,990 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767079261] [2025-03-09 06:57:43,990 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:44,017 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:44,018 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2025-03-09 06:57:44,019 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1227, Invalid=4029, Unknown=0, NotChecked=0, Total=5256 [2025-03-09 06:57:44,019 INFO L87 Difference]: Start difference. First operand 164 states and 189 transitions. cyclomatic complexity: 28 Second operand has 73 states, 72 states have (on average 2.3055555555555554) internal successors, (166), 73 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:44,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:44,711 INFO L93 Difference]: Finished difference Result 580 states and 675 transitions. [2025-03-09 06:57:44,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 580 states and 675 transitions. [2025-03-09 06:57:44,712 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:44,713 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 580 states to 314 states and 364 transitions. [2025-03-09 06:57:44,713 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291 [2025-03-09 06:57:44,713 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291 [2025-03-09 06:57:44,713 INFO L73 IsDeterministic]: Start isDeterministic. Operand 314 states and 364 transitions. [2025-03-09 06:57:44,714 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:44,714 INFO L218 hiAutomatonCegarLoop]: Abstraction has 314 states and 364 transitions. [2025-03-09 06:57:44,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314 states and 364 transitions. [2025-03-09 06:57:44,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314 to 171. [2025-03-09 06:57:44,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 171 states, 171 states have (on average 1.152046783625731) internal successors, (197), 170 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:44,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 197 transitions. [2025-03-09 06:57:44,716 INFO L240 hiAutomatonCegarLoop]: Abstraction has 171 states and 197 transitions. [2025-03-09 06:57:44,717 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2025-03-09 06:57:44,717 INFO L432 stractBuchiCegarLoop]: Abstraction has 171 states and 197 transitions. [2025-03-09 06:57:44,717 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-03-09 06:57:44,717 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 171 states and 197 transitions. [2025-03-09 06:57:44,718 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:44,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:44,718 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:44,718 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 23, 22, 22, 1, 1, 1] [2025-03-09 06:57:44,718 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:44,718 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:44,718 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:44,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:44,719 INFO L85 PathProgramCache]: Analyzing trace with hash 543449277, now seen corresponding path program 44 times [2025-03-09 06:57:44,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:44,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395654481] [2025-03-09 06:57:44,719 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:57:44,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:44,732 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 93 statements into 2 equivalence classes. [2025-03-09 06:57:44,775 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 93 of 93 statements. [2025-03-09 06:57:44,775 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-09 06:57:44,775 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:44,775 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:44,779 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 93 statements into 1 equivalence classes. [2025-03-09 06:57:44,834 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 93 of 93 statements. [2025-03-09 06:57:44,834 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:44,834 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:44,844 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:44,845 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:44,845 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 24 times [2025-03-09 06:57:44,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:44,845 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1656774870] [2025-03-09 06:57:44,845 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:57:44,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:44,848 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:44,848 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:44,848 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 06:57:44,848 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:44,848 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:44,849 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:44,849 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:44,849 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:44,849 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:44,851 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:44,851 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:44,851 INFO L85 PathProgramCache]: Analyzing trace with hash -2129268311, now seen corresponding path program 45 times [2025-03-09 06:57:44,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:44,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761254200] [2025-03-09 06:57:44,852 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:44,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:44,862 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 96 statements into 24 equivalence classes. [2025-03-09 06:57:45,153 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) and asserted 96 of 96 statements. [2025-03-09 06:57:45,154 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2025-03-09 06:57:45,154 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:46,125 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 715 proven. 343 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:46,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:46,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [761254200] [2025-03-09 06:57:46,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [761254200] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:46,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [194732299] [2025-03-09 06:57:46,125 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:57:46,125 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:46,126 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:46,128 INFO L229 MonitoredProcess]: Starting monitored process 40 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:46,129 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2025-03-09 06:57:46,241 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 96 statements into 24 equivalence classes. [2025-03-09 06:57:48,407 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) and asserted 96 of 96 statements. [2025-03-09 06:57:48,408 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2025-03-09 06:57:48,408 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:48,413 INFO L256 TraceCheckSpWp]: Trace formula consists of 524 conjuncts, 50 conjuncts are in the unsatisfiable core [2025-03-09 06:57:48,415 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:49,135 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 782 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:49,135 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:49,682 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 782 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:49,682 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [194732299] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:49,683 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:49,683 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49] total 75 [2025-03-09 06:57:49,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [240114172] [2025-03-09 06:57:49,683 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:49,707 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:49,708 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2025-03-09 06:57:49,709 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1328, Invalid=4372, Unknown=0, NotChecked=0, Total=5700 [2025-03-09 06:57:49,709 INFO L87 Difference]: Start difference. First operand 171 states and 197 transitions. cyclomatic complexity: 29 Second operand has 76 states, 75 states have (on average 2.3066666666666666) internal successors, (173), 76 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:50,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:50,417 INFO L93 Difference]: Finished difference Result 605 states and 704 transitions. [2025-03-09 06:57:50,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 605 states and 704 transitions. [2025-03-09 06:57:50,419 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:50,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 605 states to 327 states and 379 transitions. [2025-03-09 06:57:50,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2025-03-09 06:57:50,420 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2025-03-09 06:57:50,420 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 379 transitions. [2025-03-09 06:57:50,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:50,420 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 379 transitions. [2025-03-09 06:57:50,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 379 transitions. [2025-03-09 06:57:50,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 178. [2025-03-09 06:57:50,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.151685393258427) internal successors, (205), 177 states have internal predecessors, (205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:50,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 205 transitions. [2025-03-09 06:57:50,423 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 205 transitions. [2025-03-09 06:57:50,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2025-03-09 06:57:50,423 INFO L432 stractBuchiCegarLoop]: Abstraction has 178 states and 205 transitions. [2025-03-09 06:57:50,423 INFO L338 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2025-03-09 06:57:50,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 205 transitions. [2025-03-09 06:57:50,424 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:50,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:50,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:50,424 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 24, 23, 23, 1, 1, 1] [2025-03-09 06:57:50,424 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:50,424 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:50,425 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:50,425 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:50,425 INFO L85 PathProgramCache]: Analyzing trace with hash 111968711, now seen corresponding path program 46 times [2025-03-09 06:57:50,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:50,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1586258439] [2025-03-09 06:57:50,425 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:57:50,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:50,437 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 97 statements into 2 equivalence classes. [2025-03-09 06:57:50,518 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 97 of 97 statements. [2025-03-09 06:57:50,519 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:57:50,519 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:50,519 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:50,522 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 97 statements into 1 equivalence classes. [2025-03-09 06:57:50,570 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 97 of 97 statements. [2025-03-09 06:57:50,570 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:50,570 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:50,578 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:50,578 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:50,578 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 25 times [2025-03-09 06:57:50,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:50,578 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081689417] [2025-03-09 06:57:50,578 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:50,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:50,581 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:50,581 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:50,581 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:50,582 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:50,582 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:50,582 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:50,583 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:50,583 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:50,583 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:50,587 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:50,587 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:50,587 INFO L85 PathProgramCache]: Analyzing trace with hash -1529693089, now seen corresponding path program 47 times [2025-03-09 06:57:50,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:50,587 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775202112] [2025-03-09 06:57:50,587 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:50,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:50,599 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 100 statements into 25 equivalence classes. [2025-03-09 06:57:50,640 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) and asserted 100 of 100 statements. [2025-03-09 06:57:50,641 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2025-03-09 06:57:50,641 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:51,576 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:51,576 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:51,576 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775202112] [2025-03-09 06:57:51,576 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775202112] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:51,576 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [253457469] [2025-03-09 06:57:51,576 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:57:51,576 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:51,577 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:51,579 INFO L229 MonitoredProcess]: Starting monitored process 41 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:51,579 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2025-03-09 06:57:51,695 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 100 statements into 25 equivalence classes. [2025-03-09 06:57:54,670 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) and asserted 100 of 100 statements. [2025-03-09 06:57:54,671 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2025-03-09 06:57:54,671 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:54,676 INFO L256 TraceCheckSpWp]: Trace formula consists of 545 conjuncts, 52 conjuncts are in the unsatisfiable core [2025-03-09 06:57:54,678 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:55,455 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:55,456 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:56,047 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:56,048 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [253457469] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:56,048 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:56,048 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51, 51] total 76 [2025-03-09 06:57:56,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [306271630] [2025-03-09 06:57:56,048 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:56,073 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:56,073 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2025-03-09 06:57:56,075 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1376, Invalid=4476, Unknown=0, NotChecked=0, Total=5852 [2025-03-09 06:57:56,075 INFO L87 Difference]: Start difference. First operand 178 states and 205 transitions. cyclomatic complexity: 30 Second operand has 77 states, 76 states have (on average 2.289473684210526) internal successors, (174), 77 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:56,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:57:56,825 INFO L93 Difference]: Finished difference Result 630 states and 733 transitions. [2025-03-09 06:57:56,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 630 states and 733 transitions. [2025-03-09 06:57:56,827 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:56,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 630 states to 340 states and 394 transitions. [2025-03-09 06:57:56,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 315 [2025-03-09 06:57:56,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 315 [2025-03-09 06:57:56,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 340 states and 394 transitions. [2025-03-09 06:57:56,828 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:57:56,828 INFO L218 hiAutomatonCegarLoop]: Abstraction has 340 states and 394 transitions. [2025-03-09 06:57:56,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states and 394 transitions. [2025-03-09 06:57:56,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 185. [2025-03-09 06:57:56,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 185 states, 185 states have (on average 1.1513513513513514) internal successors, (213), 184 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:57:56,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 213 transitions. [2025-03-09 06:57:56,830 INFO L240 hiAutomatonCegarLoop]: Abstraction has 185 states and 213 transitions. [2025-03-09 06:57:56,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2025-03-09 06:57:56,831 INFO L432 stractBuchiCegarLoop]: Abstraction has 185 states and 213 transitions. [2025-03-09 06:57:56,831 INFO L338 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2025-03-09 06:57:56,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 185 states and 213 transitions. [2025-03-09 06:57:56,831 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:57:56,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:57:56,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:57:56,832 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [25, 25, 24, 24, 1, 1, 1] [2025-03-09 06:57:56,832 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:57:56,832 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:56,832 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:57:56,832 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:56,832 INFO L85 PathProgramCache]: Analyzing trace with hash 1581780349, now seen corresponding path program 48 times [2025-03-09 06:57:56,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:56,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177510247] [2025-03-09 06:57:56,832 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:57:56,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:56,845 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 101 statements into 25 equivalence classes. [2025-03-09 06:57:57,121 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) and asserted 101 of 101 statements. [2025-03-09 06:57:57,121 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2025-03-09 06:57:57,121 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:57,121 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:57,127 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 101 statements into 1 equivalence classes. [2025-03-09 06:57:57,210 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 101 of 101 statements. [2025-03-09 06:57:57,210 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:57,210 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:57,217 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:57,218 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:57,218 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 26 times [2025-03-09 06:57:57,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:57,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236371103] [2025-03-09 06:57:57,218 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:57:57,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:57,220 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:57,221 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:57,221 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 06:57:57,221 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:57,221 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:57:57,221 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:57:57,221 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:57:57,222 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:57,222 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:57:57,223 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:57:57,223 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:57:57,223 INFO L85 PathProgramCache]: Analyzing trace with hash -1562768151, now seen corresponding path program 49 times [2025-03-09 06:57:57,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:57:57,223 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585824738] [2025-03-09 06:57:57,223 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:57,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:57:57,235 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 104 statements into 1 equivalence classes. [2025-03-09 06:57:57,244 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 104 of 104 statements. [2025-03-09 06:57:57,245 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:57,245 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:58,258 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 852 proven. 398 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:58,258 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:57:58,258 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1585824738] [2025-03-09 06:57:58,258 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1585824738] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:57:58,258 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [596893738] [2025-03-09 06:57:58,258 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:57:58,258 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:57:58,258 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:57:58,260 INFO L229 MonitoredProcess]: Starting monitored process 42 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:57:58,261 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2025-03-09 06:57:58,382 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 104 statements into 1 equivalence classes. [2025-03-09 06:57:58,423 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 104 of 104 statements. [2025-03-09 06:57:58,423 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:57:58,423 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:57:58,425 INFO L256 TraceCheckSpWp]: Trace formula consists of 566 conjuncts, 54 conjuncts are in the unsatisfiable core [2025-03-09 06:57:58,427 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:57:59,267 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 925 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:59,267 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:57:59,915 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 925 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:57:59,915 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [596893738] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:57:59,915 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:57:59,916 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53, 53] total 81 [2025-03-09 06:57:59,916 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1954742162] [2025-03-09 06:57:59,916 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:57:59,941 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:57:59,942 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2025-03-09 06:57:59,943 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1542, Invalid=5100, Unknown=0, NotChecked=0, Total=6642 [2025-03-09 06:57:59,943 INFO L87 Difference]: Start difference. First operand 185 states and 213 transitions. cyclomatic complexity: 31 Second operand has 82 states, 81 states have (on average 2.308641975308642) internal successors, (187), 82 states have internal predecessors, (187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:58:00,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:58:00,790 INFO L93 Difference]: Finished difference Result 655 states and 762 transitions. [2025-03-09 06:58:00,790 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 655 states and 762 transitions. [2025-03-09 06:58:00,792 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:58:00,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 655 states to 353 states and 409 transitions. [2025-03-09 06:58:00,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2025-03-09 06:58:00,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2025-03-09 06:58:00,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 353 states and 409 transitions. [2025-03-09 06:58:00,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:58:00,793 INFO L218 hiAutomatonCegarLoop]: Abstraction has 353 states and 409 transitions. [2025-03-09 06:58:00,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353 states and 409 transitions. [2025-03-09 06:58:00,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353 to 192. [2025-03-09 06:58:00,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 192 states, 192 states have (on average 1.1510416666666667) internal successors, (221), 191 states have internal predecessors, (221), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:58:00,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 221 transitions. [2025-03-09 06:58:00,796 INFO L240 hiAutomatonCegarLoop]: Abstraction has 192 states and 221 transitions. [2025-03-09 06:58:00,796 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2025-03-09 06:58:00,796 INFO L432 stractBuchiCegarLoop]: Abstraction has 192 states and 221 transitions. [2025-03-09 06:58:00,796 INFO L338 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2025-03-09 06:58:00,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 192 states and 221 transitions. [2025-03-09 06:58:00,797 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:58:00,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:58:00,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:58:00,797 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [26, 26, 25, 25, 1, 1, 1] [2025-03-09 06:58:00,797 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:58:00,797 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:58:00,798 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:58:00,798 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:58:00,798 INFO L85 PathProgramCache]: Analyzing trace with hash 283483911, now seen corresponding path program 50 times [2025-03-09 06:58:00,798 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:58:00,798 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219281816] [2025-03-09 06:58:00,798 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:58:00,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:58:00,809 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 105 statements into 2 equivalence classes. [2025-03-09 06:58:00,857 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 105 of 105 statements. [2025-03-09 06:58:00,857 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-09 06:58:00,857 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:00,857 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:58:00,861 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 105 statements into 1 equivalence classes. [2025-03-09 06:58:00,941 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 105 of 105 statements. [2025-03-09 06:58:00,941 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:58:00,941 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:00,946 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:58:00,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:58:00,947 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 27 times [2025-03-09 06:58:00,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:58:00,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709628539] [2025-03-09 06:58:00,947 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:58:00,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:58:00,949 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:58:00,950 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:58:00,950 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 06:58:00,950 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:00,950 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:58:00,950 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:58:00,951 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:58:00,951 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:58:00,951 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:00,952 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:58:00,952 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:58:00,952 INFO L85 PathProgramCache]: Analyzing trace with hash 1363515167, now seen corresponding path program 51 times [2025-03-09 06:58:00,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:58:00,953 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389444233] [2025-03-09 06:58:00,953 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:58:00,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:58:00,964 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 108 statements into 27 equivalence classes. [2025-03-09 06:58:01,489 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) and asserted 108 of 108 statements. [2025-03-09 06:58:01,489 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2025-03-09 06:58:01,490 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:58:02,518 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 925 proven. 427 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:58:02,519 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:58:02,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [389444233] [2025-03-09 06:58:02,519 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [389444233] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:58:02,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1505389751] [2025-03-09 06:58:02,519 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:58:02,519 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:58:02,519 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:58:02,521 INFO L229 MonitoredProcess]: Starting monitored process 43 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:58:02,522 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2025-03-09 06:58:02,652 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 108 statements into 27 equivalence classes. [2025-03-09 06:58:05,372 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) and asserted 108 of 108 statements. [2025-03-09 06:58:05,372 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2025-03-09 06:58:05,372 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:58:05,379 INFO L256 TraceCheckSpWp]: Trace formula consists of 587 conjuncts, 56 conjuncts are in the unsatisfiable core [2025-03-09 06:58:05,381 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:58:06,282 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 1001 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:58:06,282 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:58:06,975 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 1001 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:58:06,975 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1505389751] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:58:06,975 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:58:06,975 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55, 55] total 84 [2025-03-09 06:58:06,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596518828] [2025-03-09 06:58:06,975 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:58:07,000 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:58:07,000 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2025-03-09 06:58:07,001 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1655, Invalid=5485, Unknown=0, NotChecked=0, Total=7140 [2025-03-09 06:58:07,001 INFO L87 Difference]: Start difference. First operand 192 states and 221 transitions. cyclomatic complexity: 32 Second operand has 85 states, 84 states have (on average 2.3095238095238093) internal successors, (194), 85 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:58:07,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:58:07,906 INFO L93 Difference]: Finished difference Result 680 states and 791 transitions. [2025-03-09 06:58:07,906 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 680 states and 791 transitions. [2025-03-09 06:58:07,907 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:58:07,908 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 680 states to 366 states and 424 transitions. [2025-03-09 06:58:07,908 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 339 [2025-03-09 06:58:07,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 339 [2025-03-09 06:58:07,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 366 states and 424 transitions. [2025-03-09 06:58:07,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:58:07,909 INFO L218 hiAutomatonCegarLoop]: Abstraction has 366 states and 424 transitions. [2025-03-09 06:58:07,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states and 424 transitions. [2025-03-09 06:58:07,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 199. [2025-03-09 06:58:07,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 199 states, 199 states have (on average 1.150753768844221) internal successors, (229), 198 states have internal predecessors, (229), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:58:07,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 229 transitions. [2025-03-09 06:58:07,911 INFO L240 hiAutomatonCegarLoop]: Abstraction has 199 states and 229 transitions. [2025-03-09 06:58:07,911 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2025-03-09 06:58:07,912 INFO L432 stractBuchiCegarLoop]: Abstraction has 199 states and 229 transitions. [2025-03-09 06:58:07,912 INFO L338 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2025-03-09 06:58:07,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 199 states and 229 transitions. [2025-03-09 06:58:07,912 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:58:07,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:58:07,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:58:07,913 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [27, 27, 26, 26, 1, 1, 1] [2025-03-09 06:58:07,913 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:58:07,913 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:58:07,913 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:58:07,913 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:58:07,913 INFO L85 PathProgramCache]: Analyzing trace with hash -857806275, now seen corresponding path program 52 times [2025-03-09 06:58:07,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:58:07,914 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702228670] [2025-03-09 06:58:07,914 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:58:07,914 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:58:07,926 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 109 statements into 2 equivalence classes. [2025-03-09 06:58:08,000 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 109 of 109 statements. [2025-03-09 06:58:08,001 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:58:08,001 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:08,001 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:58:08,006 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 109 statements into 1 equivalence classes. [2025-03-09 06:58:08,070 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 109 of 109 statements. [2025-03-09 06:58:08,071 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:58:08,071 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:08,078 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:58:08,079 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:58:08,079 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 28 times [2025-03-09 06:58:08,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:58:08,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247627704] [2025-03-09 06:58:08,079 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 06:58:08,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:58:08,083 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-03-09 06:58:08,084 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:58:08,084 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 06:58:08,084 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:08,084 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:58:08,085 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:58:08,085 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:58:08,085 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:58:08,085 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:08,087 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:58:08,087 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:58:08,087 INFO L85 PathProgramCache]: Analyzing trace with hash 148699177, now seen corresponding path program 53 times [2025-03-09 06:58:08,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:58:08,087 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1908614472] [2025-03-09 06:58:08,087 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:58:08,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:58:08,100 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 112 statements into 28 equivalence classes. [2025-03-09 06:58:08,157 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) and asserted 112 of 112 statements. [2025-03-09 06:58:08,157 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2025-03-09 06:58:08,157 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:58:09,272 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1080 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:58:09,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:58:09,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1908614472] [2025-03-09 06:58:09,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1908614472] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:58:09,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2060080966] [2025-03-09 06:58:09,272 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:58:09,272 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:58:09,272 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:58:09,274 INFO L229 MonitoredProcess]: Starting monitored process 44 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:58:09,275 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2025-03-09 06:58:09,412 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 112 statements into 28 equivalence classes. [2025-03-09 06:58:10,336 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) and asserted 112 of 112 statements. [2025-03-09 06:58:10,336 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2025-03-09 06:58:10,336 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:58:10,343 INFO L256 TraceCheckSpWp]: Trace formula consists of 608 conjuncts, 58 conjuncts are in the unsatisfiable core [2025-03-09 06:58:10,345 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:58:11,366 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1080 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:58:11,366 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:58:12,090 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1080 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:58:12,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2060080966] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:58:12,090 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:58:12,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57, 57] total 85 [2025-03-09 06:58:12,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1761902002] [2025-03-09 06:58:12,090 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:58:12,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:58:12,115 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2025-03-09 06:58:12,116 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1709, Invalid=5601, Unknown=0, NotChecked=0, Total=7310 [2025-03-09 06:58:12,116 INFO L87 Difference]: Start difference. First operand 199 states and 229 transitions. cyclomatic complexity: 33 Second operand has 86 states, 85 states have (on average 2.2941176470588234) internal successors, (195), 86 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:58:13,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:58:13,130 INFO L93 Difference]: Finished difference Result 705 states and 820 transitions. [2025-03-09 06:58:13,130 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 705 states and 820 transitions. [2025-03-09 06:58:13,131 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:58:13,132 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 705 states to 379 states and 439 transitions. [2025-03-09 06:58:13,132 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 351 [2025-03-09 06:58:13,133 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 351 [2025-03-09 06:58:13,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 379 states and 439 transitions. [2025-03-09 06:58:13,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:58:13,133 INFO L218 hiAutomatonCegarLoop]: Abstraction has 379 states and 439 transitions. [2025-03-09 06:58:13,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 379 states and 439 transitions. [2025-03-09 06:58:13,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 379 to 206. [2025-03-09 06:58:13,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 206 states, 206 states have (on average 1.1504854368932038) internal successors, (237), 205 states have internal predecessors, (237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:58:13,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 237 transitions. [2025-03-09 06:58:13,135 INFO L240 hiAutomatonCegarLoop]: Abstraction has 206 states and 237 transitions. [2025-03-09 06:58:13,136 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2025-03-09 06:58:13,136 INFO L432 stractBuchiCegarLoop]: Abstraction has 206 states and 237 transitions. [2025-03-09 06:58:13,136 INFO L338 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2025-03-09 06:58:13,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 206 states and 237 transitions. [2025-03-09 06:58:13,137 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:58:13,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:58:13,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:58:13,137 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [28, 28, 27, 27, 1, 1, 1] [2025-03-09 06:58:13,137 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:58:13,137 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:58:13,138 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:58:13,138 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:58:13,138 INFO L85 PathProgramCache]: Analyzing trace with hash -1556378553, now seen corresponding path program 54 times [2025-03-09 06:58:13,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:58:13,138 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1104963507] [2025-03-09 06:58:13,138 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:58:13,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:58:13,150 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 113 statements into 28 equivalence classes. [2025-03-09 06:58:13,472 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) and asserted 113 of 113 statements. [2025-03-09 06:58:13,473 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) [2025-03-09 06:58:13,473 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:13,473 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:58:13,477 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 113 statements into 1 equivalence classes. [2025-03-09 06:58:13,540 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 113 of 113 statements. [2025-03-09 06:58:13,540 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:58:13,540 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:13,548 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:58:13,549 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:58:13,549 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 29 times [2025-03-09 06:58:13,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:58:13,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488751739] [2025-03-09 06:58:13,549 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 06:58:13,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:58:13,552 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:58:13,552 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:58:13,552 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 06:58:13,552 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:13,552 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:58:13,553 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:58:13,553 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:58:13,553 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:58:13,553 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:13,554 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:58:13,555 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:58:13,555 INFO L85 PathProgramCache]: Analyzing trace with hash -1901485601, now seen corresponding path program 55 times [2025-03-09 06:58:13,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:58:13,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552594128] [2025-03-09 06:58:13,555 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:58:13,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:58:13,566 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 116 statements into 1 equivalence classes. [2025-03-09 06:58:13,578 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 116 of 116 statements. [2025-03-09 06:58:13,578 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:58:13,578 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:58:14,753 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1080 proven. 488 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:58:14,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:58:14,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1552594128] [2025-03-09 06:58:14,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1552594128] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:58:14,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1105112624] [2025-03-09 06:58:14,753 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 06:58:14,753 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:58:14,753 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:58:14,755 INFO L229 MonitoredProcess]: Starting monitored process 45 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:58:14,756 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2025-03-09 06:58:14,901 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 116 statements into 1 equivalence classes. [2025-03-09 06:58:14,946 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 116 of 116 statements. [2025-03-09 06:58:14,947 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:58:14,947 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:58:14,949 INFO L256 TraceCheckSpWp]: Trace formula consists of 629 conjuncts, 60 conjuncts are in the unsatisfiable core [2025-03-09 06:58:14,951 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:58:15,953 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1162 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:58:15,953 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:58:16,741 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1162 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:58:16,742 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1105112624] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:58:16,742 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:58:16,742 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59] total 90 [2025-03-09 06:58:16,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1702253120] [2025-03-09 06:58:16,742 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:58:16,772 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:58:16,777 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2025-03-09 06:58:16,778 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1893, Invalid=6297, Unknown=0, NotChecked=0, Total=8190 [2025-03-09 06:58:16,778 INFO L87 Difference]: Start difference. First operand 206 states and 237 transitions. cyclomatic complexity: 34 Second operand has 91 states, 90 states have (on average 2.311111111111111) internal successors, (208), 91 states have internal predecessors, (208), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:58:17,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 06:58:17,734 INFO L93 Difference]: Finished difference Result 730 states and 849 transitions. [2025-03-09 06:58:17,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 730 states and 849 transitions. [2025-03-09 06:58:17,736 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:58:17,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 730 states to 392 states and 454 transitions. [2025-03-09 06:58:17,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 363 [2025-03-09 06:58:17,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 363 [2025-03-09 06:58:17,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 392 states and 454 transitions. [2025-03-09 06:58:17,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 06:58:17,737 INFO L218 hiAutomatonCegarLoop]: Abstraction has 392 states and 454 transitions. [2025-03-09 06:58:17,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states and 454 transitions. [2025-03-09 06:58:17,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 213. [2025-03-09 06:58:17,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 213 states, 213 states have (on average 1.1502347417840375) internal successors, (245), 212 states have internal predecessors, (245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 06:58:17,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 245 transitions. [2025-03-09 06:58:17,740 INFO L240 hiAutomatonCegarLoop]: Abstraction has 213 states and 245 transitions. [2025-03-09 06:58:17,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2025-03-09 06:58:17,741 INFO L432 stractBuchiCegarLoop]: Abstraction has 213 states and 245 transitions. [2025-03-09 06:58:17,741 INFO L338 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2025-03-09 06:58:17,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 213 states and 245 transitions. [2025-03-09 06:58:17,741 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-09 06:58:17,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 06:58:17,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 06:58:17,742 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [29, 29, 28, 28, 1, 1, 1] [2025-03-09 06:58:17,742 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-09 06:58:17,742 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:58:17,742 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-09 06:58:17,742 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:58:17,742 INFO L85 PathProgramCache]: Analyzing trace with hash -247138563, now seen corresponding path program 56 times [2025-03-09 06:58:17,742 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:58:17,743 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1374543856] [2025-03-09 06:58:17,743 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 06:58:17,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:58:17,779 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 117 statements into 2 equivalence classes. [2025-03-09 06:58:17,896 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 117 of 117 statements. [2025-03-09 06:58:17,896 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-09 06:58:17,896 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:17,896 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:58:17,902 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 117 statements into 1 equivalence classes. [2025-03-09 06:58:18,050 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 117 of 117 statements. [2025-03-09 06:58:18,050 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:58:18,050 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:18,060 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:58:18,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:58:18,060 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 30 times [2025-03-09 06:58:18,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:58:18,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132154296] [2025-03-09 06:58:18,060 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 06:58:18,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:58:18,065 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:58:18,065 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:58:18,065 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 06:58:18,065 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:18,065 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 06:58:18,066 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-09 06:58:18,066 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-09 06:58:18,066 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 06:58:18,066 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 06:58:18,068 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 06:58:18,068 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 06:58:18,068 INFO L85 PathProgramCache]: Analyzing trace with hash -930958487, now seen corresponding path program 57 times [2025-03-09 06:58:18,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 06:58:18,068 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1216747371] [2025-03-09 06:58:18,068 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:58:18,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 06:58:18,087 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 120 statements into 30 equivalence classes. [2025-03-09 06:58:18,774 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) and asserted 120 of 120 statements. [2025-03-09 06:58:18,774 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2025-03-09 06:58:18,775 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:58:20,045 INFO L134 CoverageAnalysis]: Checked inductivity of 1682 backedges. 1162 proven. 520 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:58:20,045 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 06:58:20,046 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1216747371] [2025-03-09 06:58:20,046 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1216747371] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-09 06:58:20,046 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [648365975] [2025-03-09 06:58:20,046 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 06:58:20,046 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-09 06:58:20,046 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 06:58:20,048 INFO L229 MonitoredProcess]: Starting monitored process 46 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-09 06:58:20,049 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2025-03-09 06:58:20,200 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 120 statements into 30 equivalence classes. [2025-03-09 06:58:24,139 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) and asserted 120 of 120 statements. [2025-03-09 06:58:24,139 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2025-03-09 06:58:24,139 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 06:58:24,146 INFO L256 TraceCheckSpWp]: Trace formula consists of 650 conjuncts, 62 conjuncts are in the unsatisfiable core [2025-03-09 06:58:24,147 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-09 06:58:25,222 INFO L134 CoverageAnalysis]: Checked inductivity of 1682 backedges. 1247 proven. 435 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:58:25,222 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-09 06:58:26,116 INFO L134 CoverageAnalysis]: Checked inductivity of 1682 backedges. 1247 proven. 435 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 06:58:26,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [648365975] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-09 06:58:26,116 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-09 06:58:26,116 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61, 61] total 93 [2025-03-09 06:58:26,117 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1409682284] [2025-03-09 06:58:26,117 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-09 06:58:26,158 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 06:58:26,158 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2025-03-09 06:58:26,159 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=2018, Invalid=6724, Unknown=0, NotChecked=0, Total=8742 [2025-03-09 06:58:26,160 INFO L87 Difference]: Start difference. First operand 213 states and 245 transitions. cyclomatic complexity: 35 Second operand has 94 states, 93 states have (on average 2.3118279569892475) internal successors, (215), 94 states have internal predecessors, (215), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)