./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.01.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e2fb8bed Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.01.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe --- Real Ultimate output --- This is Ultimate 0.3.0-?-e2fb8be-m [2025-03-09 07:36:01,897 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-09 07:36:01,949 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-09 07:36:01,955 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-09 07:36:01,955 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-09 07:36:01,955 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-09 07:36:01,971 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-09 07:36:01,972 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-09 07:36:01,972 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-09 07:36:01,972 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-09 07:36:01,972 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-09 07:36:01,973 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-09 07:36:01,973 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-09 07:36:01,973 INFO L153 SettingsManager]: * Use SBE=true [2025-03-09 07:36:01,973 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-09 07:36:01,973 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-09 07:36:01,973 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-09 07:36:01,973 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-09 07:36:01,973 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-09 07:36:01,973 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-09 07:36:01,974 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-09 07:36:01,974 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-09 07:36:01,975 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-09 07:36:01,975 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-09 07:36:01,975 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-09 07:36:01,975 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-09 07:36:01,975 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-09 07:36:01,975 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe [2025-03-09 07:36:02,202 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-09 07:36:02,211 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-09 07:36:02,213 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-09 07:36:02,214 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-09 07:36:02,214 INFO L274 PluginConnector]: CDTParser initialized [2025-03-09 07:36:02,215 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.01.cil.c [2025-03-09 07:36:03,391 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6178b8dda/09af1ec9f28d457c88b944b191c659ba/FLAGe9c739647 [2025-03-09 07:36:03,622 INFO L384 CDTParser]: Found 1 translation units. [2025-03-09 07:36:03,623 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.01.cil.c [2025-03-09 07:36:03,634 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6178b8dda/09af1ec9f28d457c88b944b191c659ba/FLAGe9c739647 [2025-03-09 07:36:03,687 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6178b8dda/09af1ec9f28d457c88b944b191c659ba [2025-03-09 07:36:03,689 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-09 07:36:03,693 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-09 07:36:03,695 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-09 07:36:03,696 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-09 07:36:03,699 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-09 07:36:03,699 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,701 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@26840f17 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03, skipping insertion in model container [2025-03-09 07:36:03,701 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,717 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-09 07:36:03,829 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 07:36:03,838 INFO L200 MainTranslator]: Completed pre-run [2025-03-09 07:36:03,856 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 07:36:03,869 INFO L204 MainTranslator]: Completed translation [2025-03-09 07:36:03,869 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03 WrapperNode [2025-03-09 07:36:03,870 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-09 07:36:03,871 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-09 07:36:03,871 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-09 07:36:03,871 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-09 07:36:03,875 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,881 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,897 INFO L138 Inliner]: procedures = 30, calls = 34, calls flagged for inlining = 29, calls inlined = 35, statements flattened = 346 [2025-03-09 07:36:03,898 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-09 07:36:03,899 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-09 07:36:03,899 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-09 07:36:03,899 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-09 07:36:03,904 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,904 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,905 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,913 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-09 07:36:03,914 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,914 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,917 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,919 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,920 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,921 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,922 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-09 07:36:03,923 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-09 07:36:03,923 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-09 07:36:03,923 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-09 07:36:03,924 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03" (1/1) ... [2025-03-09 07:36:03,928 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 07:36:03,945 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 07:36:03,959 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 07:36:03,961 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-09 07:36:03,980 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-09 07:36:03,980 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-09 07:36:03,980 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-09 07:36:03,980 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-09 07:36:04,033 INFO L256 CfgBuilder]: Building ICFG [2025-03-09 07:36:04,034 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-09 07:36:04,318 INFO L? ?]: Removed 60 outVars from TransFormulas that were not future-live. [2025-03-09 07:36:04,318 INFO L307 CfgBuilder]: Performing block encoding [2025-03-09 07:36:04,326 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-09 07:36:04,327 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-09 07:36:04,328 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:36:04 BoogieIcfgContainer [2025-03-09 07:36:04,328 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-09 07:36:04,328 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-09 07:36:04,328 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-09 07:36:04,332 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-09 07:36:04,332 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:36:04,332 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.03 07:36:03" (1/3) ... [2025-03-09 07:36:04,333 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@603c7e4d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 07:36:04, skipping insertion in model container [2025-03-09 07:36:04,333 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:36:04,333 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:03" (2/3) ... [2025-03-09 07:36:04,333 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@603c7e4d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 07:36:04, skipping insertion in model container [2025-03-09 07:36:04,333 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:36:04,333 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:36:04" (3/3) ... [2025-03-09 07:36:04,334 INFO L363 chiAutomizerObserver]: Analyzing ICFG transmitter.01.cil.c [2025-03-09 07:36:04,364 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-09 07:36:04,364 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-09 07:36:04,364 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-09 07:36:04,364 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-09 07:36:04,364 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-09 07:36:04,364 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-09 07:36:04,364 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-09 07:36:04,365 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-09 07:36:04,369 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 131 states, 130 states have (on average 1.4923076923076923) internal successors, (194), 130 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:04,389 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2025-03-09 07:36:04,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:04,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:04,396 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:04,396 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:04,396 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-09 07:36:04,397 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 131 states, 130 states have (on average 1.4923076923076923) internal successors, (194), 130 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:04,402 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2025-03-09 07:36:04,404 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:04,404 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:04,405 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:04,406 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:04,411 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:04,411 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:04,415 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:04,415 INFO L85 PathProgramCache]: Analyzing trace with hash 379205120, now seen corresponding path program 1 times [2025-03-09 07:36:04,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:04,421 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [21226204] [2025-03-09 07:36:04,421 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:04,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:04,468 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-09 07:36:04,479 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:04,479 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:04,479 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:04,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:04,555 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:04,555 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [21226204] [2025-03-09 07:36:04,555 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [21226204] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:04,555 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:04,556 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:04,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [704138971] [2025-03-09 07:36:04,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:04,559 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:04,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:04,560 INFO L85 PathProgramCache]: Analyzing trace with hash -1024269287, now seen corresponding path program 1 times [2025-03-09 07:36:04,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:04,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733496593] [2025-03-09 07:36:04,560 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:04,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:04,570 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-03-09 07:36:04,572 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-03-09 07:36:04,572 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:04,572 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:04,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:04,585 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:04,586 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [733496593] [2025-03-09 07:36:04,586 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [733496593] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:04,586 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:04,586 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 07:36:04,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1482984616] [2025-03-09 07:36:04,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:04,587 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:04,587 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:04,605 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:04,606 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:04,607 INFO L87 Difference]: Start difference. First operand has 131 states, 130 states have (on average 1.4923076923076923) internal successors, (194), 130 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:04,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:04,624 INFO L93 Difference]: Finished difference Result 129 states and 185 transitions. [2025-03-09 07:36:04,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 129 states and 185 transitions. [2025-03-09 07:36:04,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2025-03-09 07:36:04,631 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 129 states to 123 states and 179 transitions. [2025-03-09 07:36:04,632 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123 [2025-03-09 07:36:04,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123 [2025-03-09 07:36:04,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 179 transitions. [2025-03-09 07:36:04,633 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:04,633 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123 states and 179 transitions. [2025-03-09 07:36:04,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 179 transitions. [2025-03-09 07:36:04,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 123. [2025-03-09 07:36:04,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123 states, 123 states have (on average 1.4552845528455285) internal successors, (179), 122 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:04,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 179 transitions. [2025-03-09 07:36:04,663 INFO L240 hiAutomatonCegarLoop]: Abstraction has 123 states and 179 transitions. [2025-03-09 07:36:04,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:04,667 INFO L432 stractBuchiCegarLoop]: Abstraction has 123 states and 179 transitions. [2025-03-09 07:36:04,667 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-09 07:36:04,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123 states and 179 transitions. [2025-03-09 07:36:04,672 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2025-03-09 07:36:04,672 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:04,672 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:04,673 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:04,673 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:04,673 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:04,673 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:04,674 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:04,674 INFO L85 PathProgramCache]: Analyzing trace with hash -865559361, now seen corresponding path program 1 times [2025-03-09 07:36:04,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:04,674 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338081074] [2025-03-09 07:36:04,674 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:04,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:04,679 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-09 07:36:04,682 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:04,682 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:04,682 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:04,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:04,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:04,703 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1338081074] [2025-03-09 07:36:04,703 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1338081074] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:04,703 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:04,703 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:04,703 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84482832] [2025-03-09 07:36:04,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:04,704 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:04,704 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:04,704 INFO L85 PathProgramCache]: Analyzing trace with hash -826837865, now seen corresponding path program 1 times [2025-03-09 07:36:04,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:04,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982242642] [2025-03-09 07:36:04,705 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:04,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:04,715 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-09 07:36:04,723 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 07:36:04,725 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:04,725 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:04,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:04,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:04,772 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982242642] [2025-03-09 07:36:04,772 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982242642] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:04,772 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:04,772 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:04,772 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1682277258] [2025-03-09 07:36:04,772 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:04,773 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:04,773 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:04,773 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:04,773 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:04,773 INFO L87 Difference]: Start difference. First operand 123 states and 179 transitions. cyclomatic complexity: 57 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:04,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:04,783 INFO L93 Difference]: Finished difference Result 123 states and 178 transitions. [2025-03-09 07:36:04,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123 states and 178 transitions. [2025-03-09 07:36:04,785 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2025-03-09 07:36:04,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123 states to 123 states and 178 transitions. [2025-03-09 07:36:04,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123 [2025-03-09 07:36:04,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123 [2025-03-09 07:36:04,786 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 178 transitions. [2025-03-09 07:36:04,786 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:04,786 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123 states and 178 transitions. [2025-03-09 07:36:04,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 178 transitions. [2025-03-09 07:36:04,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 123. [2025-03-09 07:36:04,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123 states, 123 states have (on average 1.4471544715447155) internal successors, (178), 122 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:04,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 178 transitions. [2025-03-09 07:36:04,807 INFO L240 hiAutomatonCegarLoop]: Abstraction has 123 states and 178 transitions. [2025-03-09 07:36:04,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:04,809 INFO L432 stractBuchiCegarLoop]: Abstraction has 123 states and 178 transitions. [2025-03-09 07:36:04,809 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-09 07:36:04,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123 states and 178 transitions. [2025-03-09 07:36:04,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2025-03-09 07:36:04,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:04,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:04,810 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:04,811 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:04,811 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:04,811 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:04,814 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:04,814 INFO L85 PathProgramCache]: Analyzing trace with hash 1172496928, now seen corresponding path program 1 times [2025-03-09 07:36:04,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:04,814 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094904628] [2025-03-09 07:36:04,814 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:04,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:04,822 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-09 07:36:04,828 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:04,831 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:04,831 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:04,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:04,880 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:04,880 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1094904628] [2025-03-09 07:36:04,880 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1094904628] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:04,880 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:04,880 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:04,880 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [662823620] [2025-03-09 07:36:04,880 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:04,880 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:04,880 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:04,880 INFO L85 PathProgramCache]: Analyzing trace with hash -826837865, now seen corresponding path program 2 times [2025-03-09 07:36:04,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:04,881 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140397369] [2025-03-09 07:36:04,881 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:36:04,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:04,891 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 40 statements into 1 equivalence classes. [2025-03-09 07:36:04,898 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 07:36:04,899 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:36:04,899 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:04,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:04,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:04,936 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140397369] [2025-03-09 07:36:04,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [140397369] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:04,936 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:04,936 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:04,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881955467] [2025-03-09 07:36:04,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:04,936 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:04,936 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:04,936 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-09 07:36:04,936 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-09 07:36:04,937 INFO L87 Difference]: Start difference. First operand 123 states and 178 transitions. cyclomatic complexity: 56 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:05,036 INFO L93 Difference]: Finished difference Result 186 states and 266 transitions. [2025-03-09 07:36:05,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 266 transitions. [2025-03-09 07:36:05,037 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 153 [2025-03-09 07:36:05,038 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 186 states and 266 transitions. [2025-03-09 07:36:05,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186 [2025-03-09 07:36:05,039 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186 [2025-03-09 07:36:05,039 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 266 transitions. [2025-03-09 07:36:05,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:05,039 INFO L218 hiAutomatonCegarLoop]: Abstraction has 186 states and 266 transitions. [2025-03-09 07:36:05,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 266 transitions. [2025-03-09 07:36:05,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 185. [2025-03-09 07:36:05,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 185 states, 185 states have (on average 1.4324324324324325) internal successors, (265), 184 states have internal predecessors, (265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 265 transitions. [2025-03-09 07:36:05,045 INFO L240 hiAutomatonCegarLoop]: Abstraction has 185 states and 265 transitions. [2025-03-09 07:36:05,045 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-09 07:36:05,046 INFO L432 stractBuchiCegarLoop]: Abstraction has 185 states and 265 transitions. [2025-03-09 07:36:05,046 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-09 07:36:05,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 185 states and 265 transitions. [2025-03-09 07:36:05,047 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 153 [2025-03-09 07:36:05,047 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:05,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:05,047 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,047 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,047 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:05,048 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:05,048 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,048 INFO L85 PathProgramCache]: Analyzing trace with hash 175394784, now seen corresponding path program 1 times [2025-03-09 07:36:05,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,048 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136484037] [2025-03-09 07:36:05,049 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,055 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-09 07:36:05,058 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:05,058 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,058 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:05,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:05,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:05,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136484037] [2025-03-09 07:36:05,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2136484037] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:05,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:05,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 07:36:05,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652932139] [2025-03-09 07:36:05,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:05,090 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:05,090 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,092 INFO L85 PathProgramCache]: Analyzing trace with hash 1301480979, now seen corresponding path program 1 times [2025-03-09 07:36:05,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [580997799] [2025-03-09 07:36:05,092 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,097 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-09 07:36:05,102 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 07:36:05,102 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,102 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:05,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:05,128 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:05,128 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [580997799] [2025-03-09 07:36:05,128 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [580997799] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:05,128 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:05,128 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:05,129 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [624834491] [2025-03-09 07:36:05,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:05,129 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:05,132 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:05,133 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:05,133 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:05,133 INFO L87 Difference]: Start difference. First operand 185 states and 265 transitions. cyclomatic complexity: 82 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:05,160 INFO L93 Difference]: Finished difference Result 269 states and 377 transitions. [2025-03-09 07:36:05,160 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 269 states and 377 transitions. [2025-03-09 07:36:05,162 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 236 [2025-03-09 07:36:05,164 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 269 states to 269 states and 377 transitions. [2025-03-09 07:36:05,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 269 [2025-03-09 07:36:05,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 269 [2025-03-09 07:36:05,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 269 states and 377 transitions. [2025-03-09 07:36:05,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:05,167 INFO L218 hiAutomatonCegarLoop]: Abstraction has 269 states and 377 transitions. [2025-03-09 07:36:05,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states and 377 transitions. [2025-03-09 07:36:05,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 254. [2025-03-09 07:36:05,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 254 states, 254 states have (on average 1.4094488188976377) internal successors, (358), 253 states have internal predecessors, (358), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254 states to 254 states and 358 transitions. [2025-03-09 07:36:05,178 INFO L240 hiAutomatonCegarLoop]: Abstraction has 254 states and 358 transitions. [2025-03-09 07:36:05,180 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:05,181 INFO L432 stractBuchiCegarLoop]: Abstraction has 254 states and 358 transitions. [2025-03-09 07:36:05,181 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-09 07:36:05,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 254 states and 358 transitions. [2025-03-09 07:36:05,182 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 222 [2025-03-09 07:36:05,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:05,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:05,182 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,183 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,183 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:05,183 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:05,184 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,184 INFO L85 PathProgramCache]: Analyzing trace with hash 944724285, now seen corresponding path program 1 times [2025-03-09 07:36:05,184 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,184 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412329874] [2025-03-09 07:36:05,184 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,187 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-09 07:36:05,191 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:05,191 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,191 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:05,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:05,222 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:05,222 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412329874] [2025-03-09 07:36:05,222 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412329874] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:05,222 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:05,222 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 07:36:05,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1279921243] [2025-03-09 07:36:05,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:05,222 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:05,223 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,223 INFO L85 PathProgramCache]: Analyzing trace with hash 1301480979, now seen corresponding path program 2 times [2025-03-09 07:36:05,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,223 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [266709164] [2025-03-09 07:36:05,223 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:36:05,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,231 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 40 statements into 1 equivalence classes. [2025-03-09 07:36:05,235 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 07:36:05,235 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:36:05,235 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:05,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:05,252 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:05,254 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [266709164] [2025-03-09 07:36:05,254 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [266709164] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:05,254 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:05,254 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:05,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1316594172] [2025-03-09 07:36:05,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:05,255 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:05,255 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:05,255 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:05,255 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:05,255 INFO L87 Difference]: Start difference. First operand 254 states and 358 transitions. cyclomatic complexity: 107 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:05,283 INFO L93 Difference]: Finished difference Result 390 states and 544 transitions. [2025-03-09 07:36:05,283 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 390 states and 544 transitions. [2025-03-09 07:36:05,285 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 359 [2025-03-09 07:36:05,286 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 390 states to 390 states and 544 transitions. [2025-03-09 07:36:05,286 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 390 [2025-03-09 07:36:05,286 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 390 [2025-03-09 07:36:05,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 390 states and 544 transitions. [2025-03-09 07:36:05,287 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:05,287 INFO L218 hiAutomatonCegarLoop]: Abstraction has 390 states and 544 transitions. [2025-03-09 07:36:05,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 390 states and 544 transitions. [2025-03-09 07:36:05,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 390 to 335. [2025-03-09 07:36:05,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 335 states, 335 states have (on average 1.3970149253731343) internal successors, (468), 334 states have internal predecessors, (468), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 335 states to 335 states and 468 transitions. [2025-03-09 07:36:05,300 INFO L240 hiAutomatonCegarLoop]: Abstraction has 335 states and 468 transitions. [2025-03-09 07:36:05,300 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:05,301 INFO L432 stractBuchiCegarLoop]: Abstraction has 335 states and 468 transitions. [2025-03-09 07:36:05,301 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-09 07:36:05,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 335 states and 468 transitions. [2025-03-09 07:36:05,302 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 305 [2025-03-09 07:36:05,302 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:05,302 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:05,303 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,303 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,303 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:05,303 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:05,303 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,304 INFO L85 PathProgramCache]: Analyzing trace with hash 944754076, now seen corresponding path program 1 times [2025-03-09 07:36:05,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,304 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083170185] [2025-03-09 07:36:05,304 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,307 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-09 07:36:05,309 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:05,309 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,309 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:05,309 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:05,311 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-09 07:36:05,312 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:05,312 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,312 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:05,330 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:05,331 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,331 INFO L85 PathProgramCache]: Analyzing trace with hash 615052142, now seen corresponding path program 1 times [2025-03-09 07:36:05,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847196778] [2025-03-09 07:36:05,331 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,336 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-09 07:36:05,341 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 07:36:05,341 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,341 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:05,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:05,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:05,356 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847196778] [2025-03-09 07:36:05,356 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1847196778] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:05,356 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:05,356 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:05,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [699309350] [2025-03-09 07:36:05,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:05,357 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:05,357 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:05,357 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:05,357 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:05,357 INFO L87 Difference]: Start difference. First operand 335 states and 468 transitions. cyclomatic complexity: 135 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:05,374 INFO L93 Difference]: Finished difference Result 422 states and 580 transitions. [2025-03-09 07:36:05,374 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 422 states and 580 transitions. [2025-03-09 07:36:05,377 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 375 [2025-03-09 07:36:05,379 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 422 states to 422 states and 580 transitions. [2025-03-09 07:36:05,379 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 422 [2025-03-09 07:36:05,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 422 [2025-03-09 07:36:05,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 422 states and 580 transitions. [2025-03-09 07:36:05,379 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:05,380 INFO L218 hiAutomatonCegarLoop]: Abstraction has 422 states and 580 transitions. [2025-03-09 07:36:05,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 422 states and 580 transitions. [2025-03-09 07:36:05,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 422 to 422. [2025-03-09 07:36:05,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 422 states, 422 states have (on average 1.3744075829383886) internal successors, (580), 421 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 422 states to 422 states and 580 transitions. [2025-03-09 07:36:05,388 INFO L240 hiAutomatonCegarLoop]: Abstraction has 422 states and 580 transitions. [2025-03-09 07:36:05,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:05,390 INFO L432 stractBuchiCegarLoop]: Abstraction has 422 states and 580 transitions. [2025-03-09 07:36:05,390 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-09 07:36:05,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 422 states and 580 transitions. [2025-03-09 07:36:05,392 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 375 [2025-03-09 07:36:05,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:05,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:05,394 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,394 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,395 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:05,395 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:05,395 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,395 INFO L85 PathProgramCache]: Analyzing trace with hash 1789224986, now seen corresponding path program 1 times [2025-03-09 07:36:05,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,396 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [750107886] [2025-03-09 07:36:05,396 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,400 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-09 07:36:05,402 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:05,402 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,402 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:05,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:05,452 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:05,452 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [750107886] [2025-03-09 07:36:05,454 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [750107886] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:05,454 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:05,454 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:05,454 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1917412010] [2025-03-09 07:36:05,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:05,454 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:05,454 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,455 INFO L85 PathProgramCache]: Analyzing trace with hash -892499667, now seen corresponding path program 1 times [2025-03-09 07:36:05,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1164366452] [2025-03-09 07:36:05,455 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,459 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-09 07:36:05,463 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 07:36:05,464 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,464 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:05,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:05,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:05,497 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1164366452] [2025-03-09 07:36:05,497 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1164366452] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:05,497 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:05,498 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:36:05,498 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753703728] [2025-03-09 07:36:05,498 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:05,498 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:05,498 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:05,498 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-09 07:36:05,498 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-09 07:36:05,499 INFO L87 Difference]: Start difference. First operand 422 states and 580 transitions. cyclomatic complexity: 160 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:05,538 INFO L93 Difference]: Finished difference Result 469 states and 646 transitions. [2025-03-09 07:36:05,538 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 469 states and 646 transitions. [2025-03-09 07:36:05,541 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 436 [2025-03-09 07:36:05,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 469 states to 469 states and 646 transitions. [2025-03-09 07:36:05,542 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 469 [2025-03-09 07:36:05,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 469 [2025-03-09 07:36:05,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 469 states and 646 transitions. [2025-03-09 07:36:05,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:05,543 INFO L218 hiAutomatonCegarLoop]: Abstraction has 469 states and 646 transitions. [2025-03-09 07:36:05,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states and 646 transitions. [2025-03-09 07:36:05,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 335. [2025-03-09 07:36:05,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 335 states, 335 states have (on average 1.382089552238806) internal successors, (463), 334 states have internal predecessors, (463), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 335 states to 335 states and 463 transitions. [2025-03-09 07:36:05,548 INFO L240 hiAutomatonCegarLoop]: Abstraction has 335 states and 463 transitions. [2025-03-09 07:36:05,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-09 07:36:05,549 INFO L432 stractBuchiCegarLoop]: Abstraction has 335 states and 463 transitions. [2025-03-09 07:36:05,549 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-09 07:36:05,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 335 states and 463 transitions. [2025-03-09 07:36:05,550 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 305 [2025-03-09 07:36:05,550 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:05,550 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:05,551 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,551 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,551 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:05,551 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:05,552 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,552 INFO L85 PathProgramCache]: Analyzing trace with hash 944754076, now seen corresponding path program 2 times [2025-03-09 07:36:05,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,552 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345416456] [2025-03-09 07:36:05,552 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:36:05,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,555 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 27 statements into 1 equivalence classes. [2025-03-09 07:36:05,557 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:05,557 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:36:05,557 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:05,557 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:05,558 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-09 07:36:05,559 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:05,559 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,559 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:05,561 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:05,562 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,562 INFO L85 PathProgramCache]: Analyzing trace with hash 965852079, now seen corresponding path program 1 times [2025-03-09 07:36:05,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165348750] [2025-03-09 07:36:05,562 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,565 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-09 07:36:05,567 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-09 07:36:05,567 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,567 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:05,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:05,595 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:05,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1165348750] [2025-03-09 07:36:05,595 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1165348750] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:05,595 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:05,596 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:36:05,597 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164154061] [2025-03-09 07:36:05,597 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:05,597 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:05,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:05,597 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-09 07:36:05,597 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-09 07:36:05,597 INFO L87 Difference]: Start difference. First operand 335 states and 463 transitions. cyclomatic complexity: 130 Second operand has 5 states, 5 states have (on average 8.0) internal successors, (40), 5 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:05,632 INFO L93 Difference]: Finished difference Result 363 states and 491 transitions. [2025-03-09 07:36:05,632 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 363 states and 491 transitions. [2025-03-09 07:36:05,634 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 333 [2025-03-09 07:36:05,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 363 states to 363 states and 491 transitions. [2025-03-09 07:36:05,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 363 [2025-03-09 07:36:05,636 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 363 [2025-03-09 07:36:05,636 INFO L73 IsDeterministic]: Start isDeterministic. Operand 363 states and 491 transitions. [2025-03-09 07:36:05,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:05,636 INFO L218 hiAutomatonCegarLoop]: Abstraction has 363 states and 491 transitions. [2025-03-09 07:36:05,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 363 states and 491 transitions. [2025-03-09 07:36:05,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 363 to 347. [2025-03-09 07:36:05,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 347 states, 347 states have (on average 1.3688760806916427) internal successors, (475), 346 states have internal predecessors, (475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 347 states to 347 states and 475 transitions. [2025-03-09 07:36:05,641 INFO L240 hiAutomatonCegarLoop]: Abstraction has 347 states and 475 transitions. [2025-03-09 07:36:05,641 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-09 07:36:05,642 INFO L432 stractBuchiCegarLoop]: Abstraction has 347 states and 475 transitions. [2025-03-09 07:36:05,642 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-09 07:36:05,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 347 states and 475 transitions. [2025-03-09 07:36:05,643 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 317 [2025-03-09 07:36:05,643 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:05,643 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:05,644 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,644 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,644 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:05,644 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:05,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,646 INFO L85 PathProgramCache]: Analyzing trace with hash 944754076, now seen corresponding path program 3 times [2025-03-09 07:36:05,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [692369831] [2025-03-09 07:36:05,646 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 07:36:05,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,650 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 27 statements into 1 equivalence classes. [2025-03-09 07:36:05,653 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:05,653 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 07:36:05,653 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:05,653 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:05,654 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-09 07:36:05,656 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:05,657 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,657 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:05,660 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:05,660 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,660 INFO L85 PathProgramCache]: Analyzing trace with hash 1360524146, now seen corresponding path program 1 times [2025-03-09 07:36:05,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,661 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2098450042] [2025-03-09 07:36:05,661 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,665 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-09 07:36:05,669 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-09 07:36:05,669 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,669 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:05,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:05,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:05,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2098450042] [2025-03-09 07:36:05,723 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2098450042] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:05,723 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:05,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:36:05,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1713121552] [2025-03-09 07:36:05,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:05,724 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:05,724 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:05,725 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-09 07:36:05,725 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-09 07:36:05,725 INFO L87 Difference]: Start difference. First operand 347 states and 475 transitions. cyclomatic complexity: 130 Second operand has 5 states, 5 states have (on average 8.2) internal successors, (41), 5 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:05,779 INFO L93 Difference]: Finished difference Result 356 states and 478 transitions. [2025-03-09 07:36:05,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 356 states and 478 transitions. [2025-03-09 07:36:05,780 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 326 [2025-03-09 07:36:05,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 356 states to 356 states and 478 transitions. [2025-03-09 07:36:05,782 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 356 [2025-03-09 07:36:05,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 356 [2025-03-09 07:36:05,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 356 states and 478 transitions. [2025-03-09 07:36:05,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:05,783 INFO L218 hiAutomatonCegarLoop]: Abstraction has 356 states and 478 transitions. [2025-03-09 07:36:05,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 356 states and 478 transitions. [2025-03-09 07:36:05,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 356 to 356. [2025-03-09 07:36:05,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 356 states, 356 states have (on average 1.3426966292134832) internal successors, (478), 355 states have internal predecessors, (478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 356 states to 356 states and 478 transitions. [2025-03-09 07:36:05,789 INFO L240 hiAutomatonCegarLoop]: Abstraction has 356 states and 478 transitions. [2025-03-09 07:36:05,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-09 07:36:05,790 INFO L432 stractBuchiCegarLoop]: Abstraction has 356 states and 478 transitions. [2025-03-09 07:36:05,790 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-09 07:36:05,790 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 356 states and 478 transitions. [2025-03-09 07:36:05,791 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 326 [2025-03-09 07:36:05,791 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:05,791 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:05,792 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,792 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,792 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:05,792 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:05,792 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,792 INFO L85 PathProgramCache]: Analyzing trace with hash 944754076, now seen corresponding path program 4 times [2025-03-09 07:36:05,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,793 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1521093395] [2025-03-09 07:36:05,793 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 07:36:05,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,797 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 27 statements into 2 equivalence classes. [2025-03-09 07:36:05,799 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:05,799 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 07:36:05,799 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:05,799 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:05,801 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-09 07:36:05,802 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-09 07:36:05,802 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,802 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:05,805 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:05,805 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,805 INFO L85 PathProgramCache]: Analyzing trace with hash 1293517393, now seen corresponding path program 1 times [2025-03-09 07:36:05,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641211001] [2025-03-09 07:36:05,806 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,813 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-09 07:36:05,815 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-09 07:36:05,815 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,815 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:05,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:05,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:05,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641211001] [2025-03-09 07:36:05,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641211001] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:05,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:05,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:05,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [575677618] [2025-03-09 07:36:05,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:05,837 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:05,837 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:05,838 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:05,838 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:05,838 INFO L87 Difference]: Start difference. First operand 356 states and 478 transitions. cyclomatic complexity: 124 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:05,860 INFO L93 Difference]: Finished difference Result 471 states and 621 transitions. [2025-03-09 07:36:05,860 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 471 states and 621 transitions. [2025-03-09 07:36:05,862 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 441 [2025-03-09 07:36:05,865 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 471 states to 471 states and 621 transitions. [2025-03-09 07:36:05,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 471 [2025-03-09 07:36:05,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 471 [2025-03-09 07:36:05,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 471 states and 621 transitions. [2025-03-09 07:36:05,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:05,867 INFO L218 hiAutomatonCegarLoop]: Abstraction has 471 states and 621 transitions. [2025-03-09 07:36:05,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471 states and 621 transitions. [2025-03-09 07:36:05,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471 to 461. [2025-03-09 07:36:05,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 461 states, 461 states have (on average 1.3188720173535793) internal successors, (608), 460 states have internal predecessors, (608), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 608 transitions. [2025-03-09 07:36:05,883 INFO L240 hiAutomatonCegarLoop]: Abstraction has 461 states and 608 transitions. [2025-03-09 07:36:05,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:05,884 INFO L432 stractBuchiCegarLoop]: Abstraction has 461 states and 608 transitions. [2025-03-09 07:36:05,885 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-09 07:36:05,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 461 states and 608 transitions. [2025-03-09 07:36:05,886 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 431 [2025-03-09 07:36:05,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:05,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:05,887 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,887 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,887 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-03-09 07:36:05,887 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" [2025-03-09 07:36:05,887 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,888 INFO L85 PathProgramCache]: Analyzing trace with hash -777394514, now seen corresponding path program 1 times [2025-03-09 07:36:05,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470182946] [2025-03-09 07:36:05,888 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,892 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-09 07:36:05,894 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-09 07:36:05,895 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,895 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:05,895 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:05,896 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-09 07:36:05,898 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-09 07:36:05,898 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,898 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:05,902 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:05,903 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,903 INFO L85 PathProgramCache]: Analyzing trace with hash 1196416480, now seen corresponding path program 1 times [2025-03-09 07:36:05,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1639989961] [2025-03-09 07:36:05,903 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,905 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-09 07:36:05,905 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-09 07:36:05,905 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,906 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:05,906 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:05,906 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-09 07:36:05,907 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-09 07:36:05,907 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,907 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:05,908 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:05,908 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,908 INFO L85 PathProgramCache]: Analyzing trace with hash 1426729427, now seen corresponding path program 1 times [2025-03-09 07:36:05,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291561371] [2025-03-09 07:36:05,908 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,911 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-03-09 07:36:05,913 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-03-09 07:36:05,913 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,913 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:05,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:05,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:05,927 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291561371] [2025-03-09 07:36:05,927 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1291561371] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:05,927 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:05,927 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 07:36:05,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18280592] [2025-03-09 07:36:05,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:05,962 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:05,962 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:05,962 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:05,963 INFO L87 Difference]: Start difference. First operand 461 states and 608 transitions. cyclomatic complexity: 150 Second operand has 3 states, 2 states have (on average 18.5) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:05,992 INFO L93 Difference]: Finished difference Result 750 states and 981 transitions. [2025-03-09 07:36:05,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 750 states and 981 transitions. [2025-03-09 07:36:05,995 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 719 [2025-03-09 07:36:05,998 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 750 states to 750 states and 981 transitions. [2025-03-09 07:36:05,998 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 750 [2025-03-09 07:36:05,999 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 750 [2025-03-09 07:36:05,999 INFO L73 IsDeterministic]: Start isDeterministic. Operand 750 states and 981 transitions. [2025-03-09 07:36:05,999 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:05,999 INFO L218 hiAutomatonCegarLoop]: Abstraction has 750 states and 981 transitions. [2025-03-09 07:36:06,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 750 states and 981 transitions. [2025-03-09 07:36:06,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 750 to 750. [2025-03-09 07:36:06,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 750 states, 750 states have (on average 1.308) internal successors, (981), 749 states have internal predecessors, (981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:06,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 750 states to 750 states and 981 transitions. [2025-03-09 07:36:06,013 INFO L240 hiAutomatonCegarLoop]: Abstraction has 750 states and 981 transitions. [2025-03-09 07:36:06,013 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:06,015 INFO L432 stractBuchiCegarLoop]: Abstraction has 750 states and 981 transitions. [2025-03-09 07:36:06,015 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-09 07:36:06,015 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 750 states and 981 transitions. [2025-03-09 07:36:06,017 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 719 [2025-03-09 07:36:06,017 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:06,017 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:06,018 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:06,018 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:06,018 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-03-09 07:36:06,018 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" [2025-03-09 07:36:06,019 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,019 INFO L85 PathProgramCache]: Analyzing trace with hash -777394514, now seen corresponding path program 2 times [2025-03-09 07:36:06,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241272391] [2025-03-09 07:36:06,019 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:36:06,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,022 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 28 statements into 1 equivalence classes. [2025-03-09 07:36:06,025 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-09 07:36:06,025 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:36:06,025 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:06,025 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:06,027 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-09 07:36:06,028 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-09 07:36:06,029 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,029 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:06,031 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:06,032 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,032 INFO L85 PathProgramCache]: Analyzing trace with hash -1294994611, now seen corresponding path program 1 times [2025-03-09 07:36:06,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,032 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1912207545] [2025-03-09 07:36:06,032 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:06,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,034 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-03-09 07:36:06,035 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-03-09 07:36:06,035 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,035 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:06,035 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:06,036 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-03-09 07:36:06,036 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-03-09 07:36:06,036 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,037 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:06,038 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:06,038 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,038 INFO L85 PathProgramCache]: Analyzing trace with hash 992415360, now seen corresponding path program 1 times [2025-03-09 07:36:06,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [16797002] [2025-03-09 07:36:06,038 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:06,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,042 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-09 07:36:06,044 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-09 07:36:06,044 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,044 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:06,044 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:06,045 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-09 07:36:06,047 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-09 07:36:06,047 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,047 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:06,052 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:06,393 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-09 07:36:06,396 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-09 07:36:06,396 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,396 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:06,397 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:06,401 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-09 07:36:06,404 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-09 07:36:06,404 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,404 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:06,471 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 09.03 07:36:06 BoogieIcfgContainer [2025-03-09 07:36:06,471 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-09 07:36:06,476 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-09 07:36:06,476 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-09 07:36:06,476 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-09 07:36:06,476 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:36:04" (3/4) ... [2025-03-09 07:36:06,478 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-03-09 07:36:06,514 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-09 07:36:06,515 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-09 07:36:06,515 INFO L158 Benchmark]: Toolchain (without parser) took 2825.62ms. Allocated memory is still 142.6MB. Free memory was 105.5MB in the beginning and 85.2MB in the end (delta: 20.2MB). Peak memory consumption was 22.8MB. Max. memory is 16.1GB. [2025-03-09 07:36:06,515 INFO L158 Benchmark]: CDTParser took 0.83ms. Allocated memory is still 201.3MB. Free memory is still 126.3MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-09 07:36:06,515 INFO L158 Benchmark]: CACSL2BoogieTranslator took 174.33ms. Allocated memory is still 142.6MB. Free memory was 105.5MB in the beginning and 92.8MB in the end (delta: 12.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-09 07:36:06,516 INFO L158 Benchmark]: Boogie Procedure Inliner took 27.63ms. Allocated memory is still 142.6MB. Free memory was 92.8MB in the beginning and 90.8MB in the end (delta: 2.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-09 07:36:06,516 INFO L158 Benchmark]: Boogie Preprocessor took 23.61ms. Allocated memory is still 142.6MB. Free memory was 90.8MB in the beginning and 89.0MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-09 07:36:06,516 INFO L158 Benchmark]: IcfgBuilder took 404.82ms. Allocated memory is still 142.6MB. Free memory was 89.0MB in the beginning and 67.5MB in the end (delta: 21.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-09 07:36:06,516 INFO L158 Benchmark]: BuchiAutomizer took 2142.68ms. Allocated memory is still 142.6MB. Free memory was 67.5MB in the beginning and 89.6MB in the end (delta: -22.1MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-09 07:36:06,516 INFO L158 Benchmark]: Witness Printer took 38.99ms. Allocated memory is still 142.6MB. Free memory was 89.6MB in the beginning and 85.2MB in the end (delta: 4.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-09 07:36:06,519 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.83ms. Allocated memory is still 201.3MB. Free memory is still 126.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 174.33ms. Allocated memory is still 142.6MB. Free memory was 105.5MB in the beginning and 92.8MB in the end (delta: 12.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 27.63ms. Allocated memory is still 142.6MB. Free memory was 92.8MB in the beginning and 90.8MB in the end (delta: 2.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 23.61ms. Allocated memory is still 142.6MB. Free memory was 90.8MB in the beginning and 89.0MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 404.82ms. Allocated memory is still 142.6MB. Free memory was 89.0MB in the beginning and 67.5MB in the end (delta: 21.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 2142.68ms. Allocated memory is still 142.6MB. Free memory was 67.5MB in the beginning and 89.6MB in the end (delta: -22.1MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 38.99ms. Allocated memory is still 142.6MB. Free memory was 89.6MB in the beginning and 85.2MB in the end (delta: 4.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 750 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.0s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 1.3s. Construction of modules took 0.2s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 11 MinimizatonAttempts, 231 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1413 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1413 mSDsluCounter, 3796 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1789 mSDsCounter, 69 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 283 IncrementalHoareTripleChecker+Invalid, 352 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 69 mSolverCounterUnsat, 2007 mSDtfsCounter, 283 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc1 concLT0 SILN0 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 204]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 204]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-03-09 07:36:06,535 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)