./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e2fb8bed Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c --- Real Ultimate output --- This is Ultimate 0.3.0-?-e2fb8be-m [2025-03-09 07:36:02,846 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-09 07:36:02,897 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-09 07:36:02,901 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-09 07:36:02,901 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-09 07:36:02,901 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-09 07:36:02,916 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-09 07:36:02,917 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-09 07:36:02,917 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-09 07:36:02,917 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-09 07:36:02,917 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-09 07:36:02,919 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-09 07:36:02,919 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-09 07:36:02,919 INFO L153 SettingsManager]: * Use SBE=true [2025-03-09 07:36:02,919 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-09 07:36:02,920 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-09 07:36:02,920 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-09 07:36:02,921 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-09 07:36:02,921 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-09 07:36:02,921 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-09 07:36:02,921 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-09 07:36:02,921 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-09 07:36:02,921 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-09 07:36:02,921 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-09 07:36:02,921 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-09 07:36:02,921 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-09 07:36:02,922 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-09 07:36:02,922 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c [2025-03-09 07:36:03,191 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-09 07:36:03,199 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-09 07:36:03,201 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-09 07:36:03,202 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-09 07:36:03,202 INFO L274 PluginConnector]: CDTParser initialized [2025-03-09 07:36:03,204 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.02.cil.c [2025-03-09 07:36:04,406 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/57729be60/90a5cd86bb2041b797d24abfc94b7142/FLAGf41eb1073 [2025-03-09 07:36:04,620 INFO L384 CDTParser]: Found 1 translation units. [2025-03-09 07:36:04,620 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.02.cil.c [2025-03-09 07:36:04,650 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/57729be60/90a5cd86bb2041b797d24abfc94b7142/FLAGf41eb1073 [2025-03-09 07:36:04,680 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/57729be60/90a5cd86bb2041b797d24abfc94b7142 [2025-03-09 07:36:04,683 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-09 07:36:04,684 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-09 07:36:04,686 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-09 07:36:04,686 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-09 07:36:04,690 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-09 07:36:04,691 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:04,692 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@409f5042 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04, skipping insertion in model container [2025-03-09 07:36:04,693 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:04,712 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-09 07:36:04,855 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 07:36:04,868 INFO L200 MainTranslator]: Completed pre-run [2025-03-09 07:36:04,899 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 07:36:04,914 INFO L204 MainTranslator]: Completed translation [2025-03-09 07:36:04,915 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04 WrapperNode [2025-03-09 07:36:04,915 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-09 07:36:04,916 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-09 07:36:04,916 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-09 07:36:04,916 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-09 07:36:04,921 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:04,930 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:04,955 INFO L138 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 45, statements flattened = 518 [2025-03-09 07:36:04,955 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-09 07:36:04,956 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-09 07:36:04,956 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-09 07:36:04,956 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-09 07:36:04,961 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:04,961 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:04,968 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:04,985 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-09 07:36:04,986 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:04,986 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:04,990 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:04,991 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:04,992 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:04,993 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:04,999 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-09 07:36:05,000 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-09 07:36:05,000 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-09 07:36:05,000 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-09 07:36:05,000 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04" (1/1) ... [2025-03-09 07:36:05,009 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 07:36:05,022 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 07:36:05,035 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 07:36:05,037 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-09 07:36:05,054 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-09 07:36:05,054 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-09 07:36:05,054 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-09 07:36:05,054 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-09 07:36:05,108 INFO L256 CfgBuilder]: Building ICFG [2025-03-09 07:36:05,110 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-09 07:36:05,491 INFO L? ?]: Removed 90 outVars from TransFormulas that were not future-live. [2025-03-09 07:36:05,492 INFO L307 CfgBuilder]: Performing block encoding [2025-03-09 07:36:05,504 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-09 07:36:05,504 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-09 07:36:05,505 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:36:05 BoogieIcfgContainer [2025-03-09 07:36:05,505 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-09 07:36:05,506 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-09 07:36:05,506 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-09 07:36:05,510 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-09 07:36:05,510 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:36:05,510 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.03 07:36:04" (1/3) ... [2025-03-09 07:36:05,511 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@14c7b3ce and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 07:36:05, skipping insertion in model container [2025-03-09 07:36:05,512 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:36:05,512 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:04" (2/3) ... [2025-03-09 07:36:05,512 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@14c7b3ce and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 07:36:05, skipping insertion in model container [2025-03-09 07:36:05,512 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:36:05,512 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:36:05" (3/3) ... [2025-03-09 07:36:05,513 INFO L363 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2025-03-09 07:36:05,559 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-09 07:36:05,559 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-09 07:36:05,559 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-09 07:36:05,560 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-09 07:36:05,560 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-09 07:36:05,560 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-09 07:36:05,560 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-09 07:36:05,560 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-09 07:36:05,566 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 203 states, 202 states have (on average 1.5148514851485149) internal successors, (306), 202 states have internal predecessors, (306), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,586 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 158 [2025-03-09 07:36:05,586 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:05,586 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:05,594 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,594 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,594 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-09 07:36:05,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 203 states, 202 states have (on average 1.5148514851485149) internal successors, (306), 202 states have internal predecessors, (306), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 158 [2025-03-09 07:36:05,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:05,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:05,605 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,605 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,613 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:05,614 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:05,621 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,621 INFO L85 PathProgramCache]: Analyzing trace with hash 1368100121, now seen corresponding path program 1 times [2025-03-09 07:36:05,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,628 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090624894] [2025-03-09 07:36:05,628 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,684 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:05,698 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:05,699 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,699 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:05,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:05,810 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:05,811 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2090624894] [2025-03-09 07:36:05,811 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2090624894] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:05,812 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:05,812 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:05,813 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168144793] [2025-03-09 07:36:05,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:05,816 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:05,818 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,819 INFO L85 PathProgramCache]: Analyzing trace with hash -1184468853, now seen corresponding path program 1 times [2025-03-09 07:36:05,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,819 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737164711] [2025-03-09 07:36:05,819 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,831 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 46 statements into 1 equivalence classes. [2025-03-09 07:36:05,834 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 46 of 46 statements. [2025-03-09 07:36:05,834 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,834 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:05,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:05,857 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:05,858 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [737164711] [2025-03-09 07:36:05,858 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [737164711] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:05,858 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:05,858 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 07:36:05,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1986555899] [2025-03-09 07:36:05,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:05,859 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:05,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:05,883 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:05,883 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:05,886 INFO L87 Difference]: Start difference. First operand has 203 states, 202 states have (on average 1.5148514851485149) internal successors, (306), 202 states have internal predecessors, (306), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:05,921 INFO L93 Difference]: Finished difference Result 201 states and 296 transitions. [2025-03-09 07:36:05,922 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201 states and 296 transitions. [2025-03-09 07:36:05,925 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2025-03-09 07:36:05,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201 states to 195 states and 290 transitions. [2025-03-09 07:36:05,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-03-09 07:36:05,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2025-03-09 07:36:05,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 290 transitions. [2025-03-09 07:36:05,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:05,933 INFO L218 hiAutomatonCegarLoop]: Abstraction has 195 states and 290 transitions. [2025-03-09 07:36:05,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 290 transitions. [2025-03-09 07:36:05,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2025-03-09 07:36:05,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.4871794871794872) internal successors, (290), 194 states have internal predecessors, (290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:05,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 290 transitions. [2025-03-09 07:36:05,963 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 290 transitions. [2025-03-09 07:36:05,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:05,969 INFO L432 stractBuchiCegarLoop]: Abstraction has 195 states and 290 transitions. [2025-03-09 07:36:05,970 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-09 07:36:05,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 290 transitions. [2025-03-09 07:36:05,972 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2025-03-09 07:36:05,972 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:05,972 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:05,973 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,973 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:05,973 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:05,973 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:05,975 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:05,975 INFO L85 PathProgramCache]: Analyzing trace with hash 342608122, now seen corresponding path program 1 times [2025-03-09 07:36:05,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:05,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222733050] [2025-03-09 07:36:05,975 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:05,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:05,981 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:05,986 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:05,986 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:05,986 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:06,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:06,021 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:06,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [222733050] [2025-03-09 07:36:06,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [222733050] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:06,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:06,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:06,022 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [138327975] [2025-03-09 07:36:06,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:06,022 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:06,023 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,023 INFO L85 PathProgramCache]: Analyzing trace with hash 1787818057, now seen corresponding path program 1 times [2025-03-09 07:36:06,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233554996] [2025-03-09 07:36:06,023 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:06,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,035 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-03-09 07:36:06,046 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-09 07:36:06,046 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,046 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:06,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:06,148 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:06,148 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [233554996] [2025-03-09 07:36:06,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [233554996] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:06,148 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:06,149 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:36:06,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2042205231] [2025-03-09 07:36:06,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:06,149 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:06,151 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:06,151 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:06,151 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:06,151 INFO L87 Difference]: Start difference. First operand 195 states and 290 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:06,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:06,171 INFO L93 Difference]: Finished difference Result 195 states and 289 transitions. [2025-03-09 07:36:06,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195 states and 289 transitions. [2025-03-09 07:36:06,172 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2025-03-09 07:36:06,173 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195 states to 195 states and 289 transitions. [2025-03-09 07:36:06,173 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-03-09 07:36:06,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2025-03-09 07:36:06,177 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 289 transitions. [2025-03-09 07:36:06,178 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:06,179 INFO L218 hiAutomatonCegarLoop]: Abstraction has 195 states and 289 transitions. [2025-03-09 07:36:06,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 289 transitions. [2025-03-09 07:36:06,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2025-03-09 07:36:06,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.4820512820512821) internal successors, (289), 194 states have internal predecessors, (289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:06,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 289 transitions. [2025-03-09 07:36:06,187 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 289 transitions. [2025-03-09 07:36:06,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:06,189 INFO L432 stractBuchiCegarLoop]: Abstraction has 195 states and 289 transitions. [2025-03-09 07:36:06,189 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-09 07:36:06,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 289 transitions. [2025-03-09 07:36:06,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2025-03-09 07:36:06,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:06,192 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:06,193 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:06,195 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:06,195 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:06,195 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:06,196 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,196 INFO L85 PathProgramCache]: Analyzing trace with hash -1768682247, now seen corresponding path program 1 times [2025-03-09 07:36:06,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [668381850] [2025-03-09 07:36:06,196 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:06,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,205 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:06,208 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:06,208 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,208 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:06,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:06,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:06,234 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [668381850] [2025-03-09 07:36:06,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [668381850] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:06,234 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:06,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:06,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778294364] [2025-03-09 07:36:06,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:06,235 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:06,235 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,235 INFO L85 PathProgramCache]: Analyzing trace with hash 1787818057, now seen corresponding path program 2 times [2025-03-09 07:36:06,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,235 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795735959] [2025-03-09 07:36:06,235 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:36:06,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,245 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 50 statements into 1 equivalence classes. [2025-03-09 07:36:06,253 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-09 07:36:06,253 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:36:06,253 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:06,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:06,315 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:06,315 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [795735959] [2025-03-09 07:36:06,315 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [795735959] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:06,315 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:06,315 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:36:06,315 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788154983] [2025-03-09 07:36:06,315 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:06,315 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:06,315 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:06,315 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:06,315 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:06,316 INFO L87 Difference]: Start difference. First operand 195 states and 289 transitions. cyclomatic complexity: 95 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:06,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:06,324 INFO L93 Difference]: Finished difference Result 195 states and 288 transitions. [2025-03-09 07:36:06,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195 states and 288 transitions. [2025-03-09 07:36:06,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2025-03-09 07:36:06,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195 states to 195 states and 288 transitions. [2025-03-09 07:36:06,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-03-09 07:36:06,330 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2025-03-09 07:36:06,330 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 288 transitions. [2025-03-09 07:36:06,330 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:06,330 INFO L218 hiAutomatonCegarLoop]: Abstraction has 195 states and 288 transitions. [2025-03-09 07:36:06,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 288 transitions. [2025-03-09 07:36:06,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2025-03-09 07:36:06,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.476923076923077) internal successors, (288), 194 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:06,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 288 transitions. [2025-03-09 07:36:06,337 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 288 transitions. [2025-03-09 07:36:06,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:06,340 INFO L432 stractBuchiCegarLoop]: Abstraction has 195 states and 288 transitions. [2025-03-09 07:36:06,340 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-09 07:36:06,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 288 transitions. [2025-03-09 07:36:06,341 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2025-03-09 07:36:06,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:06,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:06,342 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:06,342 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:06,342 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:06,342 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:06,344 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,346 INFO L85 PathProgramCache]: Analyzing trace with hash 241421594, now seen corresponding path program 1 times [2025-03-09 07:36:06,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102851513] [2025-03-09 07:36:06,346 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:06,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,351 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:06,354 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:06,354 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,354 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:06,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:06,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:06,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102851513] [2025-03-09 07:36:06,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1102851513] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:06,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:06,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 07:36:06,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [622783972] [2025-03-09 07:36:06,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:06,390 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:06,391 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,392 INFO L85 PathProgramCache]: Analyzing trace with hash 1787818057, now seen corresponding path program 3 times [2025-03-09 07:36:06,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1295421004] [2025-03-09 07:36:06,392 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 07:36:06,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,399 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 50 statements into 1 equivalence classes. [2025-03-09 07:36:06,406 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-09 07:36:06,410 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 07:36:06,410 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:06,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:06,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:06,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1295421004] [2025-03-09 07:36:06,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1295421004] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:06,467 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:06,467 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:36:06,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [706774476] [2025-03-09 07:36:06,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:06,468 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:06,468 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:06,468 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:06,468 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:06,469 INFO L87 Difference]: Start difference. First operand 195 states and 288 transitions. cyclomatic complexity: 94 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:06,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:06,511 INFO L93 Difference]: Finished difference Result 342 states and 497 transitions. [2025-03-09 07:36:06,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342 states and 497 transitions. [2025-03-09 07:36:06,513 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 301 [2025-03-09 07:36:06,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342 states to 342 states and 497 transitions. [2025-03-09 07:36:06,520 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 342 [2025-03-09 07:36:06,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 342 [2025-03-09 07:36:06,521 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342 states and 497 transitions. [2025-03-09 07:36:06,522 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:06,523 INFO L218 hiAutomatonCegarLoop]: Abstraction has 342 states and 497 transitions. [2025-03-09 07:36:06,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states and 497 transitions. [2025-03-09 07:36:06,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 321. [2025-03-09 07:36:06,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 321 states, 321 states have (on average 1.4610591900311527) internal successors, (469), 320 states have internal predecessors, (469), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:06,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 321 states to 321 states and 469 transitions. [2025-03-09 07:36:06,533 INFO L240 hiAutomatonCegarLoop]: Abstraction has 321 states and 469 transitions. [2025-03-09 07:36:06,534 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:06,534 INFO L432 stractBuchiCegarLoop]: Abstraction has 321 states and 469 transitions. [2025-03-09 07:36:06,534 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-09 07:36:06,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 321 states and 469 transitions. [2025-03-09 07:36:06,536 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 280 [2025-03-09 07:36:06,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:06,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:06,536 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:06,536 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:06,537 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:06,537 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:06,537 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,537 INFO L85 PathProgramCache]: Analyzing trace with hash 1979853175, now seen corresponding path program 1 times [2025-03-09 07:36:06,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,537 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416623624] [2025-03-09 07:36:06,537 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:06,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,546 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:06,551 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:06,554 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,554 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:06,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:06,587 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:06,587 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416623624] [2025-03-09 07:36:06,587 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416623624] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:06,587 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:06,587 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 07:36:06,588 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1851319465] [2025-03-09 07:36:06,588 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:06,588 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:06,588 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,589 INFO L85 PathProgramCache]: Analyzing trace with hash 650700832, now seen corresponding path program 1 times [2025-03-09 07:36:06,589 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,589 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1190257535] [2025-03-09 07:36:06,590 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:06,590 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,595 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-03-09 07:36:06,598 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-09 07:36:06,599 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,599 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:06,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:06,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:06,644 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1190257535] [2025-03-09 07:36:06,644 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1190257535] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:06,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:06,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:36:06,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1070404332] [2025-03-09 07:36:06,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:06,645 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:06,645 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:06,645 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:06,646 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:06,646 INFO L87 Difference]: Start difference. First operand 321 states and 469 transitions. cyclomatic complexity: 150 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:06,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:06,681 INFO L93 Difference]: Finished difference Result 549 states and 798 transitions. [2025-03-09 07:36:06,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 549 states and 798 transitions. [2025-03-09 07:36:06,685 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 504 [2025-03-09 07:36:06,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 549 states to 549 states and 798 transitions. [2025-03-09 07:36:06,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 549 [2025-03-09 07:36:06,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 549 [2025-03-09 07:36:06,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 549 states and 798 transitions. [2025-03-09 07:36:06,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:06,691 INFO L218 hiAutomatonCegarLoop]: Abstraction has 549 states and 798 transitions. [2025-03-09 07:36:06,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 549 states and 798 transitions. [2025-03-09 07:36:06,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 549 to 547. [2025-03-09 07:36:06,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 547 states, 547 states have (on average 1.4552102376599634) internal successors, (796), 546 states have internal predecessors, (796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:06,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 547 states to 547 states and 796 transitions. [2025-03-09 07:36:06,709 INFO L240 hiAutomatonCegarLoop]: Abstraction has 547 states and 796 transitions. [2025-03-09 07:36:06,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:06,711 INFO L432 stractBuchiCegarLoop]: Abstraction has 547 states and 796 transitions. [2025-03-09 07:36:06,711 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-09 07:36:06,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 547 states and 796 transitions. [2025-03-09 07:36:06,714 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 502 [2025-03-09 07:36:06,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:06,716 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:06,717 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:06,718 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:06,718 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:06,718 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:06,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,719 INFO L85 PathProgramCache]: Analyzing trace with hash -1723838572, now seen corresponding path program 1 times [2025-03-09 07:36:06,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194060155] [2025-03-09 07:36:06,719 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:06,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,725 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:06,728 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:06,728 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,728 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:06,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:06,760 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:06,760 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [194060155] [2025-03-09 07:36:06,760 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [194060155] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:06,760 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:06,761 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 07:36:06,761 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027118767] [2025-03-09 07:36:06,761 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:06,761 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:06,761 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,761 INFO L85 PathProgramCache]: Analyzing trace with hash 650700832, now seen corresponding path program 2 times [2025-03-09 07:36:06,763 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,763 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133733203] [2025-03-09 07:36:06,763 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:36:06,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,786 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 50 statements into 1 equivalence classes. [2025-03-09 07:36:06,791 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-09 07:36:06,791 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:36:06,791 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:06,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:06,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:06,822 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133733203] [2025-03-09 07:36:06,822 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133733203] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:06,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:06,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:36:06,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962584812] [2025-03-09 07:36:06,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:06,822 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:06,822 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:06,823 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:06,823 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:06,823 INFO L87 Difference]: Start difference. First operand 547 states and 796 transitions. cyclomatic complexity: 253 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:06,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:06,863 INFO L93 Difference]: Finished difference Result 1038 states and 1495 transitions. [2025-03-09 07:36:06,863 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1038 states and 1495 transitions. [2025-03-09 07:36:06,872 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 980 [2025-03-09 07:36:06,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1038 states to 1038 states and 1495 transitions. [2025-03-09 07:36:06,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1038 [2025-03-09 07:36:06,881 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1038 [2025-03-09 07:36:06,881 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1038 states and 1495 transitions. [2025-03-09 07:36:06,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:06,883 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1038 states and 1495 transitions. [2025-03-09 07:36:06,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1038 states and 1495 transitions. [2025-03-09 07:36:06,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1038 to 1026. [2025-03-09 07:36:06,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1026 states, 1026 states have (on average 1.4415204678362572) internal successors, (1479), 1025 states have internal predecessors, (1479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:06,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1026 states to 1026 states and 1479 transitions. [2025-03-09 07:36:06,903 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1026 states and 1479 transitions. [2025-03-09 07:36:06,903 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:06,904 INFO L432 stractBuchiCegarLoop]: Abstraction has 1026 states and 1479 transitions. [2025-03-09 07:36:06,904 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-09 07:36:06,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1026 states and 1479 transitions. [2025-03-09 07:36:06,908 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 976 [2025-03-09 07:36:06,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:06,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:06,909 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:06,909 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:06,909 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:06,909 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:06,910 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,910 INFO L85 PathProgramCache]: Analyzing trace with hash 1999146865, now seen corresponding path program 1 times [2025-03-09 07:36:06,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1495526180] [2025-03-09 07:36:06,910 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:06,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,914 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:06,916 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:06,916 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:06,916 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:06,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:06,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:06,959 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1495526180] [2025-03-09 07:36:06,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1495526180] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:06,959 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:06,959 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:06,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815489068] [2025-03-09 07:36:06,959 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:06,960 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:06,960 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:06,960 INFO L85 PathProgramCache]: Analyzing trace with hash 650700832, now seen corresponding path program 3 times [2025-03-09 07:36:06,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:06,961 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156297205] [2025-03-09 07:36:06,961 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 07:36:06,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:06,966 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 50 statements into 1 equivalence classes. [2025-03-09 07:36:06,969 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-09 07:36:06,969 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 07:36:06,969 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:06,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:06,996 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:06,996 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156297205] [2025-03-09 07:36:06,996 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156297205] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:06,997 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:06,997 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:36:06,997 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [643921929] [2025-03-09 07:36:06,997 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:06,997 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:06,997 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:06,997 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-09 07:36:06,997 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-09 07:36:06,998 INFO L87 Difference]: Start difference. First operand 1026 states and 1479 transitions. cyclomatic complexity: 461 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:07,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:07,104 INFO L93 Difference]: Finished difference Result 1987 states and 2815 transitions. [2025-03-09 07:36:07,104 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1987 states and 2815 transitions. [2025-03-09 07:36:07,114 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 1868 [2025-03-09 07:36:07,123 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1987 states to 1987 states and 2815 transitions. [2025-03-09 07:36:07,123 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1987 [2025-03-09 07:36:07,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1987 [2025-03-09 07:36:07,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1987 states and 2815 transitions. [2025-03-09 07:36:07,127 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:07,127 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1987 states and 2815 transitions. [2025-03-09 07:36:07,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1987 states and 2815 transitions. [2025-03-09 07:36:07,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1987 to 1971. [2025-03-09 07:36:07,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1971 states, 1971 states have (on average 1.4190766108574329) internal successors, (2797), 1970 states have internal predecessors, (2797), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:07,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1971 states to 1971 states and 2797 transitions. [2025-03-09 07:36:07,160 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1971 states and 2797 transitions. [2025-03-09 07:36:07,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-09 07:36:07,162 INFO L432 stractBuchiCegarLoop]: Abstraction has 1971 states and 2797 transitions. [2025-03-09 07:36:07,163 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-09 07:36:07,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1971 states and 2797 transitions. [2025-03-09 07:36:07,170 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 1856 [2025-03-09 07:36:07,170 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:07,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:07,171 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:07,171 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:07,171 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:07,171 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:07,171 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:07,172 INFO L85 PathProgramCache]: Analyzing trace with hash 1956810931, now seen corresponding path program 1 times [2025-03-09 07:36:07,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:07,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744288790] [2025-03-09 07:36:07,172 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:07,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:07,176 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:07,178 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:07,179 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:07,179 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:07,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:07,205 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:07,205 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744288790] [2025-03-09 07:36:07,205 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744288790] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:07,205 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:07,205 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 07:36:07,205 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [146343620] [2025-03-09 07:36:07,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:07,205 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:07,205 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:07,205 INFO L85 PathProgramCache]: Analyzing trace with hash 650700832, now seen corresponding path program 4 times [2025-03-09 07:36:07,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:07,206 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853690194] [2025-03-09 07:36:07,206 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 07:36:07,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:07,212 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 50 statements into 2 equivalence classes. [2025-03-09 07:36:07,215 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-09 07:36:07,216 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-03-09 07:36:07,216 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:07,257 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:07,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:07,257 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [853690194] [2025-03-09 07:36:07,257 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [853690194] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:07,257 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:07,257 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:36:07,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [663293421] [2025-03-09 07:36:07,257 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:07,258 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:07,258 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:07,258 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:07,258 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:07,258 INFO L87 Difference]: Start difference. First operand 1971 states and 2797 transitions. cyclomatic complexity: 842 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:07,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:07,327 INFO L93 Difference]: Finished difference Result 2963 states and 4180 transitions. [2025-03-09 07:36:07,327 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2963 states and 4180 transitions. [2025-03-09 07:36:07,343 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 2864 [2025-03-09 07:36:07,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2963 states to 2963 states and 4180 transitions. [2025-03-09 07:36:07,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2963 [2025-03-09 07:36:07,362 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2963 [2025-03-09 07:36:07,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2963 states and 4180 transitions. [2025-03-09 07:36:07,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:07,366 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2963 states and 4180 transitions. [2025-03-09 07:36:07,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2963 states and 4180 transitions. [2025-03-09 07:36:07,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2963 to 2274. [2025-03-09 07:36:07,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2274 states, 2274 states have (on average 1.4094107299912049) internal successors, (3205), 2273 states have internal predecessors, (3205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:07,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2274 states to 2274 states and 3205 transitions. [2025-03-09 07:36:07,405 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2274 states and 3205 transitions. [2025-03-09 07:36:07,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:07,407 INFO L432 stractBuchiCegarLoop]: Abstraction has 2274 states and 3205 transitions. [2025-03-09 07:36:07,408 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-09 07:36:07,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2274 states and 3205 transitions. [2025-03-09 07:36:07,418 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2188 [2025-03-09 07:36:07,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:07,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:07,419 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:07,419 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:07,419 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:07,419 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:07,420 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:07,421 INFO L85 PathProgramCache]: Analyzing trace with hash 1968127058, now seen corresponding path program 1 times [2025-03-09 07:36:07,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:07,421 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687195971] [2025-03-09 07:36:07,421 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:07,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:07,425 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:07,428 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:07,428 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:07,428 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:07,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:07,460 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:07,460 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687195971] [2025-03-09 07:36:07,460 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1687195971] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:07,460 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:07,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:07,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [457150475] [2025-03-09 07:36:07,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:07,461 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-09 07:36:07,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:07,461 INFO L85 PathProgramCache]: Analyzing trace with hash -222298274, now seen corresponding path program 1 times [2025-03-09 07:36:07,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:07,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824603850] [2025-03-09 07:36:07,461 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:07,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:07,466 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-03-09 07:36:07,474 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-09 07:36:07,475 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:07,475 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:07,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:07,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:07,510 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824603850] [2025-03-09 07:36:07,510 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1824603850] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:07,510 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:07,510 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:36:07,511 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [306716376] [2025-03-09 07:36:07,511 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:07,511 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:07,511 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:07,511 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-09 07:36:07,511 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-09 07:36:07,511 INFO L87 Difference]: Start difference. First operand 2274 states and 3205 transitions. cyclomatic complexity: 939 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:07,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:07,575 INFO L93 Difference]: Finished difference Result 2534 states and 3555 transitions. [2025-03-09 07:36:07,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2534 states and 3555 transitions. [2025-03-09 07:36:07,588 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 2456 [2025-03-09 07:36:07,599 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2534 states to 2534 states and 3555 transitions. [2025-03-09 07:36:07,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2534 [2025-03-09 07:36:07,601 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2534 [2025-03-09 07:36:07,601 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2534 states and 3555 transitions. [2025-03-09 07:36:07,604 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:07,604 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2534 states and 3555 transitions. [2025-03-09 07:36:07,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2534 states and 3555 transitions. [2025-03-09 07:36:07,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2534 to 1842. [2025-03-09 07:36:07,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1842 states, 1842 states have (on average 1.4033659066232356) internal successors, (2585), 1841 states have internal predecessors, (2585), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:07,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1842 states to 1842 states and 2585 transitions. [2025-03-09 07:36:07,638 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1842 states and 2585 transitions. [2025-03-09 07:36:07,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-09 07:36:07,640 INFO L432 stractBuchiCegarLoop]: Abstraction has 1842 states and 2585 transitions. [2025-03-09 07:36:07,640 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-09 07:36:07,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1842 states and 2585 transitions. [2025-03-09 07:36:07,649 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1780 [2025-03-09 07:36:07,649 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:07,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:07,650 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:07,653 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:07,654 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:07,654 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume !(1 == ~E_2~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:07,654 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:07,654 INFO L85 PathProgramCache]: Analyzing trace with hash 1999146896, now seen corresponding path program 1 times [2025-03-09 07:36:07,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:07,654 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498155179] [2025-03-09 07:36:07,655 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:07,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:07,658 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:07,664 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:07,664 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:07,664 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:07,664 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:07,666 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:07,668 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:07,668 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:07,668 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:07,688 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:07,689 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:07,689 INFO L85 PathProgramCache]: Analyzing trace with hash 904947100, now seen corresponding path program 1 times [2025-03-09 07:36:07,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:07,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843550756] [2025-03-09 07:36:07,689 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:07,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:07,694 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-03-09 07:36:07,698 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-09 07:36:07,698 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:07,698 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:07,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:07,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:07,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [843550756] [2025-03-09 07:36:07,742 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [843550756] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:07,742 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:07,742 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:36:07,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [70038853] [2025-03-09 07:36:07,742 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:07,743 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:07,743 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:07,743 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-09 07:36:07,743 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-09 07:36:07,743 INFO L87 Difference]: Start difference. First operand 1842 states and 2585 transitions. cyclomatic complexity: 751 Second operand has 5 states, 5 states have (on average 10.0) internal successors, (50), 5 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:07,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:07,788 INFO L93 Difference]: Finished difference Result 1954 states and 2697 transitions. [2025-03-09 07:36:07,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1954 states and 2697 transitions. [2025-03-09 07:36:07,797 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1892 [2025-03-09 07:36:07,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1954 states to 1954 states and 2697 transitions. [2025-03-09 07:36:07,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1954 [2025-03-09 07:36:07,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1954 [2025-03-09 07:36:07,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1954 states and 2697 transitions. [2025-03-09 07:36:07,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:07,807 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1954 states and 2697 transitions. [2025-03-09 07:36:07,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1954 states and 2697 transitions. [2025-03-09 07:36:07,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1954 to 1890. [2025-03-09 07:36:07,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1890 states, 1890 states have (on average 1.3931216931216932) internal successors, (2633), 1889 states have internal predecessors, (2633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:07,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1890 states to 1890 states and 2633 transitions. [2025-03-09 07:36:07,834 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1890 states and 2633 transitions. [2025-03-09 07:36:07,835 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-09 07:36:07,835 INFO L432 stractBuchiCegarLoop]: Abstraction has 1890 states and 2633 transitions. [2025-03-09 07:36:07,835 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-09 07:36:07,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1890 states and 2633 transitions. [2025-03-09 07:36:07,840 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1828 [2025-03-09 07:36:07,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:07,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:07,841 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:07,841 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:07,841 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:07,842 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume !(1 == ~E_2~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:07,842 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:07,842 INFO L85 PathProgramCache]: Analyzing trace with hash 1999146896, now seen corresponding path program 2 times [2025-03-09 07:36:07,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:07,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366404196] [2025-03-09 07:36:07,842 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:36:07,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:07,847 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:07,850 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:07,850 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:36:07,850 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:07,850 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:07,853 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:07,855 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:07,855 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:07,855 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:07,861 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:07,861 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:07,861 INFO L85 PathProgramCache]: Analyzing trace with hash -2024868429, now seen corresponding path program 1 times [2025-03-09 07:36:07,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:07,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2078654819] [2025-03-09 07:36:07,861 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:07,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:07,869 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 52 statements into 1 equivalence classes. [2025-03-09 07:36:07,873 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-03-09 07:36:07,873 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:07,873 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:07,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:07,921 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:07,921 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2078654819] [2025-03-09 07:36:07,921 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2078654819] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:07,921 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:07,921 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 07:36:07,921 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043760286] [2025-03-09 07:36:07,921 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:07,922 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:07,922 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:07,922 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-09 07:36:07,922 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-09 07:36:07,922 INFO L87 Difference]: Start difference. First operand 1890 states and 2633 transitions. cyclomatic complexity: 751 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:07,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:07,996 INFO L93 Difference]: Finished difference Result 1932 states and 2648 transitions. [2025-03-09 07:36:07,996 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1932 states and 2648 transitions. [2025-03-09 07:36:08,003 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1870 [2025-03-09 07:36:08,010 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1932 states to 1932 states and 2648 transitions. [2025-03-09 07:36:08,010 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1932 [2025-03-09 07:36:08,011 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1932 [2025-03-09 07:36:08,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1932 states and 2648 transitions. [2025-03-09 07:36:08,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:08,013 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1932 states and 2648 transitions. [2025-03-09 07:36:08,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1932 states and 2648 transitions. [2025-03-09 07:36:08,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1932 to 1932. [2025-03-09 07:36:08,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1932 states, 1932 states have (on average 1.370600414078675) internal successors, (2648), 1931 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:08,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1932 states to 1932 states and 2648 transitions. [2025-03-09 07:36:08,042 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1932 states and 2648 transitions. [2025-03-09 07:36:08,042 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-09 07:36:08,043 INFO L432 stractBuchiCegarLoop]: Abstraction has 1932 states and 2648 transitions. [2025-03-09 07:36:08,043 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-09 07:36:08,043 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1932 states and 2648 transitions. [2025-03-09 07:36:08,047 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1870 [2025-03-09 07:36:08,048 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:08,048 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:08,048 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:08,048 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:08,048 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-09 07:36:08,049 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume !(1 == ~E_2~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-09 07:36:08,049 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:08,049 INFO L85 PathProgramCache]: Analyzing trace with hash 1999146896, now seen corresponding path program 3 times [2025-03-09 07:36:08,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:08,049 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046461246] [2025-03-09 07:36:08,049 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 07:36:08,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:08,055 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:08,061 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:08,061 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 07:36:08,061 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,061 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:08,063 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-09 07:36:08,069 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-09 07:36:08,069 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,070 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,077 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:08,078 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:08,078 INFO L85 PathProgramCache]: Analyzing trace with hash 259995026, now seen corresponding path program 1 times [2025-03-09 07:36:08,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:08,078 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627026044] [2025-03-09 07:36:08,078 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:08,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:08,086 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 52 statements into 1 equivalence classes. [2025-03-09 07:36:08,092 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-03-09 07:36:08,092 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,092 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:08,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:08,111 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:08,111 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1627026044] [2025-03-09 07:36:08,111 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1627026044] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:08,111 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:08,111 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:08,111 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445132125] [2025-03-09 07:36:08,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:08,111 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:36:08,111 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:08,111 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:08,111 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:08,111 INFO L87 Difference]: Start difference. First operand 1932 states and 2648 transitions. cyclomatic complexity: 724 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:08,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:08,147 INFO L93 Difference]: Finished difference Result 2680 states and 3604 transitions. [2025-03-09 07:36:08,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2680 states and 3604 transitions. [2025-03-09 07:36:08,155 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 2609 [2025-03-09 07:36:08,165 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2680 states to 2680 states and 3604 transitions. [2025-03-09 07:36:08,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2680 [2025-03-09 07:36:08,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2680 [2025-03-09 07:36:08,167 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2680 states and 3604 transitions. [2025-03-09 07:36:08,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:08,170 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2680 states and 3604 transitions. [2025-03-09 07:36:08,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2680 states and 3604 transitions. [2025-03-09 07:36:08,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2680 to 2616. [2025-03-09 07:36:08,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2616 states, 2616 states have (on average 1.3478593272171253) internal successors, (3526), 2615 states have internal predecessors, (3526), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:08,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2616 states to 2616 states and 3526 transitions. [2025-03-09 07:36:08,206 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2616 states and 3526 transitions. [2025-03-09 07:36:08,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:08,207 INFO L432 stractBuchiCegarLoop]: Abstraction has 2616 states and 3526 transitions. [2025-03-09 07:36:08,207 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-09 07:36:08,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2616 states and 3526 transitions. [2025-03-09 07:36:08,212 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 2545 [2025-03-09 07:36:08,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:08,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:08,213 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:08,213 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:08,213 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-03-09 07:36:08,213 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" [2025-03-09 07:36:08,213 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:08,214 INFO L85 PathProgramCache]: Analyzing trace with hash 1844011947, now seen corresponding path program 1 times [2025-03-09 07:36:08,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:08,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127793629] [2025-03-09 07:36:08,214 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:08,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:08,218 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-09 07:36:08,220 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-09 07:36:08,220 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,220 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,220 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:08,221 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-09 07:36:08,223 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-09 07:36:08,223 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,223 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,230 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:08,233 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:08,233 INFO L85 PathProgramCache]: Analyzing trace with hash 1277421573, now seen corresponding path program 1 times [2025-03-09 07:36:08,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:08,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438767839] [2025-03-09 07:36:08,233 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:08,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:08,236 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-09 07:36:08,238 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-09 07:36:08,238 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,238 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,238 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:08,238 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-09 07:36:08,239 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-09 07:36:08,239 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,239 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,241 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:08,242 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:08,242 INFO L85 PathProgramCache]: Analyzing trace with hash 2076983087, now seen corresponding path program 1 times [2025-03-09 07:36:08,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:08,243 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958486286] [2025-03-09 07:36:08,243 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:08,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:08,248 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-03-09 07:36:08,253 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-03-09 07:36:08,253 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,253 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:08,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:08,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:08,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [958486286] [2025-03-09 07:36:08,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [958486286] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:08,272 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:08,272 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-09 07:36:08,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1863751001] [2025-03-09 07:36:08,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:08,325 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:08,326 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:08,326 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:08,326 INFO L87 Difference]: Start difference. First operand 2616 states and 3526 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:08,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:08,389 INFO L93 Difference]: Finished difference Result 2648 states and 3500 transitions. [2025-03-09 07:36:08,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2648 states and 3500 transitions. [2025-03-09 07:36:08,397 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 2544 [2025-03-09 07:36:08,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2648 states to 2648 states and 3500 transitions. [2025-03-09 07:36:08,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2648 [2025-03-09 07:36:08,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2648 [2025-03-09 07:36:08,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2648 states and 3500 transitions. [2025-03-09 07:36:08,418 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:08,418 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2648 states and 3500 transitions. [2025-03-09 07:36:08,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2648 states and 3500 transitions. [2025-03-09 07:36:08,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2648 to 2515. [2025-03-09 07:36:08,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2515 states, 2515 states have (on average 1.327634194831014) internal successors, (3339), 2514 states have internal predecessors, (3339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:08,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2515 states to 2515 states and 3339 transitions. [2025-03-09 07:36:08,455 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2515 states and 3339 transitions. [2025-03-09 07:36:08,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:08,456 INFO L432 stractBuchiCegarLoop]: Abstraction has 2515 states and 3339 transitions. [2025-03-09 07:36:08,457 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-09 07:36:08,457 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2515 states and 3339 transitions. [2025-03-09 07:36:08,462 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 2411 [2025-03-09 07:36:08,462 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:08,462 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:08,463 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:08,463 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:08,463 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-03-09 07:36:08,463 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" [2025-03-09 07:36:08,464 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:08,464 INFO L85 PathProgramCache]: Analyzing trace with hash 1844011947, now seen corresponding path program 2 times [2025-03-09 07:36:08,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:08,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1712033526] [2025-03-09 07:36:08,464 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:36:08,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:08,469 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 39 statements into 1 equivalence classes. [2025-03-09 07:36:08,472 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-09 07:36:08,472 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:36:08,472 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,472 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:08,474 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-09 07:36:08,476 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-09 07:36:08,476 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,476 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,479 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:08,481 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:08,481 INFO L85 PathProgramCache]: Analyzing trace with hash -758487045, now seen corresponding path program 1 times [2025-03-09 07:36:08,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:08,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159999852] [2025-03-09 07:36:08,482 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:08,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:08,484 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-03-09 07:36:08,484 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-03-09 07:36:08,484 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,484 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,485 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:08,485 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-03-09 07:36:08,486 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-03-09 07:36:08,486 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,486 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,487 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:08,487 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:08,487 INFO L85 PathProgramCache]: Analyzing trace with hash -1179018075, now seen corresponding path program 1 times [2025-03-09 07:36:08,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:08,487 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517651457] [2025-03-09 07:36:08,488 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:08,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:08,492 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-03-09 07:36:08,495 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-03-09 07:36:08,495 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,495 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:36:08,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:36:08,515 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:36:08,516 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517651457] [2025-03-09 07:36:08,516 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1517651457] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:36:08,516 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:36:08,516 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 07:36:08,516 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927110938] [2025-03-09 07:36:08,516 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:36:08,550 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:36:08,551 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-09 07:36:08,551 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-09 07:36:08,551 INFO L87 Difference]: Start difference. First operand 2515 states and 3339 transitions. cyclomatic complexity: 836 Second operand has 3 states, 2 states have (on average 25.5) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:08,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:36:08,582 INFO L93 Difference]: Finished difference Result 2615 states and 3432 transitions. [2025-03-09 07:36:08,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2615 states and 3432 transitions. [2025-03-09 07:36:08,589 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 2430 [2025-03-09 07:36:08,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2615 states to 2615 states and 3432 transitions. [2025-03-09 07:36:08,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2615 [2025-03-09 07:36:08,597 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2615 [2025-03-09 07:36:08,597 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2615 states and 3432 transitions. [2025-03-09 07:36:08,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:36:08,600 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2615 states and 3432 transitions. [2025-03-09 07:36:08,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2615 states and 3432 transitions. [2025-03-09 07:36:08,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2615 to 2615. [2025-03-09 07:36:08,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2615 states, 2615 states have (on average 1.3124282982791586) internal successors, (3432), 2614 states have internal predecessors, (3432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:36:08,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2615 states to 2615 states and 3432 transitions. [2025-03-09 07:36:08,630 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2615 states and 3432 transitions. [2025-03-09 07:36:08,630 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-09 07:36:08,631 INFO L432 stractBuchiCegarLoop]: Abstraction has 2615 states and 3432 transitions. [2025-03-09 07:36:08,631 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-09 07:36:08,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2615 states and 3432 transitions. [2025-03-09 07:36:08,636 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 2430 [2025-03-09 07:36:08,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:36:08,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:36:08,637 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:08,637 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:36:08,637 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-03-09 07:36:08,637 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" [2025-03-09 07:36:08,637 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:08,637 INFO L85 PathProgramCache]: Analyzing trace with hash 1844011947, now seen corresponding path program 3 times [2025-03-09 07:36:08,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:08,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797617264] [2025-03-09 07:36:08,637 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 07:36:08,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:08,642 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 39 statements into 1 equivalence classes. [2025-03-09 07:36:08,644 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-09 07:36:08,644 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 07:36:08,644 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,644 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:08,645 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-09 07:36:08,647 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-09 07:36:08,647 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,648 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,650 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:08,651 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:08,651 INFO L85 PathProgramCache]: Analyzing trace with hash 1238394856, now seen corresponding path program 1 times [2025-03-09 07:36:08,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:08,651 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66589897] [2025-03-09 07:36:08,651 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:08,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:08,656 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 14 statements into 1 equivalence classes. [2025-03-09 07:36:08,657 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 14 of 14 statements. [2025-03-09 07:36:08,657 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,657 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,657 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:08,657 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 14 statements into 1 equivalence classes. [2025-03-09 07:36:08,658 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 14 of 14 statements. [2025-03-09 07:36:08,658 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,658 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,660 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:08,660 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:36:08,660 INFO L85 PathProgramCache]: Analyzing trace with hash 835000850, now seen corresponding path program 1 times [2025-03-09 07:36:08,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:36:08,660 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516372941] [2025-03-09 07:36:08,660 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:36:08,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:36:08,665 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 53 statements into 1 equivalence classes. [2025-03-09 07:36:08,668 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 53 of 53 statements. [2025-03-09 07:36:08,668 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,668 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,668 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:08,670 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 53 statements into 1 equivalence classes. [2025-03-09 07:36:08,672 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 53 of 53 statements. [2025-03-09 07:36:08,672 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:08,672 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:08,677 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:36:09,149 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-09 07:36:09,153 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-09 07:36:09,153 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:09,153 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:09,153 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:36:09,159 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-09 07:36:09,163 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-09 07:36:09,163 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:36:09,163 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:36:09,236 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 09.03 07:36:09 BoogieIcfgContainer [2025-03-09 07:36:09,236 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-09 07:36:09,237 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-09 07:36:09,237 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-09 07:36:09,237 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-09 07:36:09,238 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:36:05" (3/4) ... [2025-03-09 07:36:09,240 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-03-09 07:36:09,293 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-09 07:36:09,294 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-09 07:36:09,295 INFO L158 Benchmark]: Toolchain (without parser) took 4610.45ms. Allocated memory was 167.8MB in the beginning and 369.1MB in the end (delta: 201.3MB). Free memory was 123.9MB in the beginning and 243.6MB in the end (delta: -119.7MB). Peak memory consumption was 78.4MB. Max. memory is 16.1GB. [2025-03-09 07:36:09,295 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 201.3MB. Free memory is still 117.1MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-09 07:36:09,295 INFO L158 Benchmark]: CACSL2BoogieTranslator took 229.45ms. Allocated memory is still 167.8MB. Free memory was 123.9MB in the beginning and 110.1MB in the end (delta: 13.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-09 07:36:09,295 INFO L158 Benchmark]: Boogie Procedure Inliner took 39.45ms. Allocated memory is still 167.8MB. Free memory was 110.1MB in the beginning and 108.2MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-09 07:36:09,298 INFO L158 Benchmark]: Boogie Preprocessor took 43.22ms. Allocated memory is still 167.8MB. Free memory was 108.2MB in the beginning and 106.3MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-09 07:36:09,299 INFO L158 Benchmark]: IcfgBuilder took 505.19ms. Allocated memory is still 167.8MB. Free memory was 106.3MB in the beginning and 75.7MB in the end (delta: 30.6MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2025-03-09 07:36:09,299 INFO L158 Benchmark]: BuchiAutomizer took 3730.60ms. Allocated memory was 167.8MB in the beginning and 369.1MB in the end (delta: 201.3MB). Free memory was 75.7MB in the beginning and 251.7MB in the end (delta: -175.9MB). Peak memory consumption was 28.1MB. Max. memory is 16.1GB. [2025-03-09 07:36:09,299 INFO L158 Benchmark]: Witness Printer took 57.33ms. Allocated memory is still 369.1MB. Free memory was 251.7MB in the beginning and 243.6MB in the end (delta: 8.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-09 07:36:09,300 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 201.3MB. Free memory is still 117.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 229.45ms. Allocated memory is still 167.8MB. Free memory was 123.9MB in the beginning and 110.1MB in the end (delta: 13.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 39.45ms. Allocated memory is still 167.8MB. Free memory was 110.1MB in the beginning and 108.2MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 43.22ms. Allocated memory is still 167.8MB. Free memory was 108.2MB in the beginning and 106.3MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 505.19ms. Allocated memory is still 167.8MB. Free memory was 106.3MB in the beginning and 75.7MB in the end (delta: 30.6MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 3730.60ms. Allocated memory was 167.8MB in the beginning and 369.1MB in the end (delta: 201.3MB). Free memory was 75.7MB in the beginning and 251.7MB in the end (delta: -175.9MB). Peak memory consumption was 28.1MB. Max. memory is 16.1GB. * Witness Printer took 57.33ms. Allocated memory is still 369.1MB. Free memory was 251.7MB in the beginning and 243.6MB in the end (delta: 8.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 14 terminating modules (14 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.14 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 2615 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.6s and 15 iterations. TraceHistogramMax:1. Analysis of lassos took 2.1s. Construction of modules took 0.3s. Büchi inclusion checks took 1.0s. Highest rank in rank-based complementation 0. Minimization of det autom 14. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 14 MinimizatonAttempts, 1693 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3278 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3278 mSDsluCounter, 7672 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3557 mSDsCounter, 112 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 368 IncrementalHoareTripleChecker+Invalid, 480 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 112 mSolverCounterUnsat, 4115 mSDtfsCounter, 368 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc2 concLT0 SILN0 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 274]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 274]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-03-09 07:36:09,315 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)