./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit


--------------------------------------------------------------------------------


Checking for termination
Using default analysis
Version e2fb8bed
Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) )

 --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f
--- Real Ultimate output ---
This is Ultimate 0.3.0-?-e2fb8be-m
[2025-03-09 07:36:07,711 INFO  L188        SettingsManager]: Resetting all preferences to default values...
[2025-03-09 07:36:07,765 INFO  L114        SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf
[2025-03-09 07:36:07,769 WARN  L101        SettingsManager]: Preference file contains the following unknown settings:
[2025-03-09 07:36:07,769 WARN  L103        SettingsManager]:   * de.uni_freiburg.informatik.ultimate.core.Log level for class
[2025-03-09 07:36:07,769 WARN  L103        SettingsManager]:   * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG
[2025-03-09 07:36:07,790 INFO  L130        SettingsManager]: Preferences different from defaults after loading the file:
[2025-03-09 07:36:07,792 INFO  L151        SettingsManager]: Preferences of UltimateCore differ from their defaults:
[2025-03-09 07:36:07,792 INFO  L153        SettingsManager]:  * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR;
[2025-03-09 07:36:07,792 INFO  L151        SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults:
[2025-03-09 07:36:07,793 INFO  L153        SettingsManager]:  * Use memory slicer=true
[2025-03-09 07:36:07,793 INFO  L151        SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults:
[2025-03-09 07:36:07,793 INFO  L153        SettingsManager]:  * Create parallel compositions if possible=false
[2025-03-09 07:36:07,794 INFO  L153        SettingsManager]:  * Use SBE=true
[2025-03-09 07:36:07,794 INFO  L151        SettingsManager]: Preferences of BuchiAutomizer differ from their defaults:
[2025-03-09 07:36:07,794 INFO  L153        SettingsManager]:  * NCSB implementation=INTSET_LAZY3
[2025-03-09 07:36:07,794 INFO  L153        SettingsManager]:  * Use old map elimination=false
[2025-03-09 07:36:07,794 INFO  L153        SettingsManager]:  * Use external solver (rank synthesis)=false
[2025-03-09 07:36:07,794 INFO  L153        SettingsManager]:  * Use only trivial implications for array writes=true
[2025-03-09 07:36:07,794 INFO  L153        SettingsManager]:  * Rank analysis=LINEAR_WITH_GUESSES
[2025-03-09 07:36:07,794 INFO  L151        SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults:
[2025-03-09 07:36:07,795 INFO  L153        SettingsManager]:  * Pointer base address is valid at dereference=ASSUME
[2025-03-09 07:36:07,795 INFO  L153        SettingsManager]:  * sizeof long=4
[2025-03-09 07:36:07,795 INFO  L153        SettingsManager]:  * Overapproximate operations on floating types=true
[2025-03-09 07:36:07,795 INFO  L153        SettingsManager]:  * sizeof POINTER=4
[2025-03-09 07:36:07,795 INFO  L153        SettingsManager]:  * Check division by zero=IGNORE
[2025-03-09 07:36:07,795 INFO  L153        SettingsManager]:  * Pointer to allocated memory at dereference=ASSUME
[2025-03-09 07:36:07,795 INFO  L153        SettingsManager]:  * If two pointers are subtracted or compared they have the same base address=ASSUME
[2025-03-09 07:36:07,795 INFO  L153        SettingsManager]:  * Check array bounds for arrays that are off heap=ASSUME
[2025-03-09 07:36:07,795 INFO  L153        SettingsManager]:  * Check unreachability of reach_error function=false
[2025-03-09 07:36:07,795 INFO  L153        SettingsManager]:  * sizeof long double=12
[2025-03-09 07:36:07,795 INFO  L153        SettingsManager]:  * Check if freed pointer was valid=false
[2025-03-09 07:36:07,796 INFO  L153        SettingsManager]:  * Assume nondeterminstic values are in range=false
[2025-03-09 07:36:07,796 INFO  L153        SettingsManager]:  * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR
[2025-03-09 07:36:07,796 INFO  L153        SettingsManager]:  * Use constant arrays=true
[2025-03-09 07:36:07,796 INFO  L151        SettingsManager]: Preferences of IcfgBuilder differ from their defaults:
[2025-03-09 07:36:07,796 INFO  L153        SettingsManager]:  * Size of a code block=SequenceOfStatements
[2025-03-09 07:36:07,796 INFO  L151        SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2025-03-09 07:36:07,796 INFO  L153        SettingsManager]:  * Trace refinement strategy=CAMEL
[2025-03-09 07:36:07,797 INFO  L151        SettingsManager]: Preferences of IcfgTransformer differ from their defaults:
[2025-03-09 07:36:07,797 INFO  L153        SettingsManager]:  * TransformationType=MODULO_NEIGHBOR
Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) )


Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f
[2025-03-09 07:36:08,026 INFO  L75    nceAwareModelManager]: Repository-Root is: /tmp
[2025-03-09 07:36:08,033 INFO  L261   ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized
[2025-03-09 07:36:08,035 INFO  L217   ainManager$Toolchain]: [Toolchain 1]: Toolchain selected.
[2025-03-09 07:36:08,036 INFO  L270        PluginConnector]: Initializing CDTParser...
[2025-03-09 07:36:08,036 INFO  L274        PluginConnector]: CDTParser initialized
[2025-03-09 07:36:08,037 INFO  L431   ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.05.cil.c
[2025-03-09 07:36:09,194 INFO  L533              CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c5443f75f/2da8575b5df44540baa3b3d97081c317/FLAG5ea782fed
[2025-03-09 07:36:09,425 INFO  L384              CDTParser]: Found 1 translation units.
[2025-03-09 07:36:09,425 INFO  L180              CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.05.cil.c
[2025-03-09 07:36:09,434 INFO  L427              CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c5443f75f/2da8575b5df44540baa3b3d97081c317/FLAG5ea782fed
[2025-03-09 07:36:09,756 INFO  L435              CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c5443f75f/2da8575b5df44540baa3b3d97081c317
[2025-03-09 07:36:09,759 INFO  L299   ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2025-03-09 07:36:09,760 INFO  L133        ToolchainWalker]: Walking toolchain with 6 elements.
[2025-03-09 07:36:09,761 INFO  L112        PluginConnector]: ------------------------CACSL2BoogieTranslator----------------------------
[2025-03-09 07:36:09,761 INFO  L270        PluginConnector]: Initializing CACSL2BoogieTranslator...
[2025-03-09 07:36:09,765 INFO  L274        PluginConnector]: CACSL2BoogieTranslator initialized
[2025-03-09 07:36:09,766 INFO  L184        PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 07:36:09" (1/1) ...
[2025-03-09 07:36:09,767 INFO  L204        PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7d5ee1f0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:09, skipping insertion in model container
[2025-03-09 07:36:09,767 INFO  L184        PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 07:36:09" (1/1) ...
[2025-03-09 07:36:09,792 INFO  L175         MainTranslator]: Built tables and reachable declarations
[2025-03-09 07:36:09,952 INFO  L210          PostProcessor]: Analyzing one entry point: main
[2025-03-09 07:36:09,965 INFO  L200         MainTranslator]: Completed pre-run
[2025-03-09 07:36:10,014 INFO  L210          PostProcessor]: Analyzing one entry point: main
[2025-03-09 07:36:10,034 INFO  L204         MainTranslator]: Completed translation
[2025-03-09 07:36:10,035 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10 WrapperNode
[2025-03-09 07:36:10,035 INFO  L131        PluginConnector]: ------------------------ END CACSL2BoogieTranslator----------------------------
[2025-03-09 07:36:10,036 INFO  L112        PluginConnector]: ------------------------Boogie Procedure Inliner----------------------------
[2025-03-09 07:36:10,036 INFO  L270        PluginConnector]: Initializing Boogie Procedure Inliner...
[2025-03-09 07:36:10,036 INFO  L274        PluginConnector]: Boogie Procedure Inliner initialized
[2025-03-09 07:36:10,040 INFO  L184        PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10" (1/1) ...
[2025-03-09 07:36:10,046 INFO  L184        PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10" (1/1) ...
[2025-03-09 07:36:10,081 INFO  L138                Inliner]: procedures = 38, calls = 46, calls flagged for inlining = 41, calls inlined = 87, statements flattened = 1214
[2025-03-09 07:36:10,082 INFO  L131        PluginConnector]: ------------------------ END Boogie Procedure Inliner----------------------------
[2025-03-09 07:36:10,082 INFO  L112        PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2025-03-09 07:36:10,082 INFO  L270        PluginConnector]: Initializing Boogie Preprocessor...
[2025-03-09 07:36:10,082 INFO  L274        PluginConnector]: Boogie Preprocessor initialized
[2025-03-09 07:36:10,090 INFO  L184        PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10" (1/1) ...
[2025-03-09 07:36:10,090 INFO  L184        PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10" (1/1) ...
[2025-03-09 07:36:10,093 INFO  L184        PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10" (1/1) ...
[2025-03-09 07:36:10,118 INFO  L175           MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0].
[2025-03-09 07:36:10,119 INFO  L184        PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10" (1/1) ...
[2025-03-09 07:36:10,119 INFO  L184        PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10" (1/1) ...
[2025-03-09 07:36:10,129 INFO  L184        PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10" (1/1) ...
[2025-03-09 07:36:10,134 INFO  L184        PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10" (1/1) ...
[2025-03-09 07:36:10,136 INFO  L184        PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10" (1/1) ...
[2025-03-09 07:36:10,137 INFO  L184        PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10" (1/1) ...
[2025-03-09 07:36:10,143 INFO  L131        PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2025-03-09 07:36:10,144 INFO  L112        PluginConnector]: ------------------------IcfgBuilder----------------------------
[2025-03-09 07:36:10,144 INFO  L270        PluginConnector]: Initializing IcfgBuilder...
[2025-03-09 07:36:10,144 INFO  L274        PluginConnector]: IcfgBuilder initialized
[2025-03-09 07:36:10,145 INFO  L184        PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10" (1/1) ...
[2025-03-09 07:36:10,149 INFO  L173          SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000
[2025-03-09 07:36:10,161 INFO  L189       MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3
[2025-03-09 07:36:10,177 INFO  L229       MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null)
[2025-03-09 07:36:10,183 INFO  L327       MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process
[2025-03-09 07:36:10,200 INFO  L130     BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit
[2025-03-09 07:36:10,200 INFO  L130     BoogieDeclarations]: Found specification of procedure write~init~int#0
[2025-03-09 07:36:10,200 INFO  L130     BoogieDeclarations]: Found specification of procedure ULTIMATE.start
[2025-03-09 07:36:10,200 INFO  L138     BoogieDeclarations]: Found implementation of procedure ULTIMATE.start
[2025-03-09 07:36:10,279 INFO  L256             CfgBuilder]: Building ICFG
[2025-03-09 07:36:10,281 INFO  L286             CfgBuilder]: Building CFG for each procedure with an implementation
[2025-03-09 07:36:11,112 INFO  L?                        ?]: Removed 228 outVars from TransFormulas that were not future-live.
[2025-03-09 07:36:11,112 INFO  L307             CfgBuilder]: Performing block encoding
[2025-03-09 07:36:11,136 INFO  L331             CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start)
[2025-03-09 07:36:11,137 INFO  L336             CfgBuilder]: Removed 0 assume(true) statements.
[2025-03-09 07:36:11,137 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:36:11 BoogieIcfgContainer
[2025-03-09 07:36:11,137 INFO  L131        PluginConnector]: ------------------------ END IcfgBuilder----------------------------
[2025-03-09 07:36:11,138 INFO  L112        PluginConnector]: ------------------------BuchiAutomizer----------------------------
[2025-03-09 07:36:11,138 INFO  L270        PluginConnector]: Initializing BuchiAutomizer...
[2025-03-09 07:36:11,142 INFO  L274        PluginConnector]: BuchiAutomizer initialized
[2025-03-09 07:36:11,142 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-03-09 07:36:11,142 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.03 07:36:09" (1/3) ...
[2025-03-09 07:36:11,143 INFO  L204        PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@62a5acd2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 07:36:11, skipping insertion in model container
[2025-03-09 07:36:11,143 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-03-09 07:36:11,143 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:36:10" (2/3) ...
[2025-03-09 07:36:11,143 INFO  L204        PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@62a5acd2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 07:36:11, skipping insertion in model container
[2025-03-09 07:36:11,143 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-03-09 07:36:11,143 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:36:11" (3/3) ...
[2025-03-09 07:36:11,144 INFO  L363   chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c
[2025-03-09 07:36:11,186 INFO  L306   stractBuchiCegarLoop]: Interprodecural is true
[2025-03-09 07:36:11,186 INFO  L307   stractBuchiCegarLoop]: Hoare is None
[2025-03-09 07:36:11,186 INFO  L308   stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates
[2025-03-09 07:36:11,186 INFO  L309   stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE
[2025-03-09 07:36:11,187 INFO  L310   stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION
[2025-03-09 07:36:11,187 INFO  L311   stractBuchiCegarLoop]: Difference is false
[2025-03-09 07:36:11,187 INFO  L312   stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA
[2025-03-09 07:36:11,187 INFO  L316   stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ========
[2025-03-09 07:36:11,194 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand  has 503 states, 502 states have (on average 1.5179282868525896) internal successors, (762), 502 states have internal predecessors, (762), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:11,227 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 422
[2025-03-09 07:36:11,227 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:11,227 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:11,234 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:11,234 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:11,234 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 1 ============
[2025-03-09 07:36:11,236 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand  has 503 states, 502 states have (on average 1.5179282868525896) internal successors, (762), 502 states have internal predecessors, (762), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:11,244 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 422
[2025-03-09 07:36:11,245 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:11,245 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:11,246 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:11,246 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:11,256 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:11,258 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:11,263 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:11,264 INFO  L85        PathProgramCache]: Analyzing trace with hash -62832258, now seen corresponding path program 1 times
[2025-03-09 07:36:11,269 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:11,269 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921346615]
[2025-03-09 07:36:11,269 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:11,270 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:11,323 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:11,336 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:11,336 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:11,336 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:11,437 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:11,437 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:11,437 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921346615]
[2025-03-09 07:36:11,438 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1921346615] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:11,438 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:11,438 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:11,439 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596659357]
[2025-03-09 07:36:11,440 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:11,442 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-09 07:36:11,443 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:11,443 INFO  L85        PathProgramCache]: Analyzing trace with hash -766019386, now seen corresponding path program 1 times
[2025-03-09 07:36:11,443 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:11,443 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106982586]
[2025-03-09 07:36:11,443 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:11,443 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:11,457 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes.
[2025-03-09 07:36:11,458 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements.
[2025-03-09 07:36:11,459 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:11,461 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:11,481 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:11,485 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:11,485 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106982586]
[2025-03-09 07:36:11,485 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2106982586] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:11,485 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:11,485 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-09 07:36:11,485 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308895366]
[2025-03-09 07:36:11,486 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:11,487 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:11,488 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:11,506 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:11,506 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:11,509 INFO  L87              Difference]: Start difference. First operand  has 503 states, 502 states have (on average 1.5179282868525896) internal successors, (762), 502 states have internal predecessors, (762), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand  has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:11,543 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:11,544 INFO  L93              Difference]: Finished difference Result 501 states and 749 transitions.
[2025-03-09 07:36:11,545 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 501 states and 749 transitions.
[2025-03-09 07:36:11,550 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 418
[2025-03-09 07:36:11,557 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 501 states to 495 states and 743 transitions.
[2025-03-09 07:36:11,558 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 495
[2025-03-09 07:36:11,561 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 495
[2025-03-09 07:36:11,562 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 495 states and 743 transitions.
[2025-03-09 07:36:11,566 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:11,566 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 495 states and 743 transitions.
[2025-03-09 07:36:11,577 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 495 states and 743 transitions.
[2025-03-09 07:36:11,603 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 495 to 495.
[2025-03-09 07:36:11,605 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 495 states, 495 states have (on average 1.501010101010101) internal successors, (743), 494 states have internal predecessors, (743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:11,606 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 495 states to 495 states and 743 transitions.
[2025-03-09 07:36:11,607 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 495 states and 743 transitions.
[2025-03-09 07:36:11,608 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:11,610 INFO  L432   stractBuchiCegarLoop]: Abstraction has 495 states and 743 transitions.
[2025-03-09 07:36:11,610 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 2 ============
[2025-03-09 07:36:11,611 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 495 states and 743 transitions.
[2025-03-09 07:36:11,613 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 418
[2025-03-09 07:36:11,613 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:11,613 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:11,615 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:11,615 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:11,615 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:11,618 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:11,618 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:11,619 INFO  L85        PathProgramCache]: Analyzing trace with hash 545244605, now seen corresponding path program 1 times
[2025-03-09 07:36:11,619 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:11,619 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139711943]
[2025-03-09 07:36:11,619 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:11,619 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:11,629 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:11,635 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:11,635 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:11,635 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:11,703 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:11,704 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:11,704 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139711943]
[2025-03-09 07:36:11,704 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139711943] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:11,704 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:11,704 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:11,704 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1721592022]
[2025-03-09 07:36:11,705 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:11,705 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-09 07:36:11,706 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:11,706 INFO  L85        PathProgramCache]: Analyzing trace with hash 313124740, now seen corresponding path program 1 times
[2025-03-09 07:36:11,706 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:11,706 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [699142405]
[2025-03-09 07:36:11,707 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:11,707 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:11,719 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes.
[2025-03-09 07:36:11,739 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements.
[2025-03-09 07:36:11,739 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:11,739 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:11,787 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:11,787 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:11,787 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [699142405]
[2025-03-09 07:36:11,787 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [699142405] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:11,787 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:11,787 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:11,788 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208716024]
[2025-03-09 07:36:11,788 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:11,788 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:11,788 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:11,788 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:11,788 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:11,792 INFO  L87              Difference]: Start difference. First operand 495 states and 743 transitions. cyclomatic complexity: 249 Second operand  has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:11,810 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:11,810 INFO  L93              Difference]: Finished difference Result 495 states and 742 transitions.
[2025-03-09 07:36:11,810 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 495 states and 742 transitions.
[2025-03-09 07:36:11,814 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 418
[2025-03-09 07:36:11,817 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 495 states to 495 states and 742 transitions.
[2025-03-09 07:36:11,817 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 495
[2025-03-09 07:36:11,818 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 495
[2025-03-09 07:36:11,818 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 495 states and 742 transitions.
[2025-03-09 07:36:11,819 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:11,819 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 495 states and 742 transitions.
[2025-03-09 07:36:11,820 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 495 states and 742 transitions.
[2025-03-09 07:36:11,833 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 495 to 495.
[2025-03-09 07:36:11,835 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 495 states, 495 states have (on average 1.498989898989899) internal successors, (742), 494 states have internal predecessors, (742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:11,836 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 495 states to 495 states and 742 transitions.
[2025-03-09 07:36:11,836 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 495 states and 742 transitions.
[2025-03-09 07:36:11,837 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:11,839 INFO  L432   stractBuchiCegarLoop]: Abstraction has 495 states and 742 transitions.
[2025-03-09 07:36:11,839 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 3 ============
[2025-03-09 07:36:11,839 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 495 states and 742 transitions.
[2025-03-09 07:36:11,841 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 418
[2025-03-09 07:36:11,842 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:11,843 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:11,845 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:11,846 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:11,846 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:11,846 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:11,847 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:11,848 INFO  L85        PathProgramCache]: Analyzing trace with hash -1236255330, now seen corresponding path program 1 times
[2025-03-09 07:36:11,848 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:11,849 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414528105]
[2025-03-09 07:36:11,849 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:11,849 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:11,854 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:11,859 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:11,861 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:11,861 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:11,893 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:11,896 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:11,897 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414528105]
[2025-03-09 07:36:11,897 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [414528105] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:11,897 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:11,897 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:11,897 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [557967640]
[2025-03-09 07:36:11,897 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:11,898 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-09 07:36:11,898 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:11,898 INFO  L85        PathProgramCache]: Analyzing trace with hash 19442436, now seen corresponding path program 1 times
[2025-03-09 07:36:11,898 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:11,898 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465875033]
[2025-03-09 07:36:11,899 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:11,899 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:11,909 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes.
[2025-03-09 07:36:11,915 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements.
[2025-03-09 07:36:11,915 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:11,915 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:11,959 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:11,959 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:11,959 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1465875033]
[2025-03-09 07:36:11,959 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1465875033] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:11,960 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:11,960 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:11,960 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1216096578]
[2025-03-09 07:36:11,960 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:11,960 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:11,960 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:11,960 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:11,961 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:11,961 INFO  L87              Difference]: Start difference. First operand 495 states and 742 transitions. cyclomatic complexity: 248 Second operand  has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:11,970 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:11,970 INFO  L93              Difference]: Finished difference Result 495 states and 741 transitions.
[2025-03-09 07:36:11,970 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 495 states and 741 transitions.
[2025-03-09 07:36:11,973 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 418
[2025-03-09 07:36:11,975 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 495 states to 495 states and 741 transitions.
[2025-03-09 07:36:11,975 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 495
[2025-03-09 07:36:11,976 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 495
[2025-03-09 07:36:11,976 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 495 states and 741 transitions.
[2025-03-09 07:36:11,976 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:11,977 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 495 states and 741 transitions.
[2025-03-09 07:36:11,977 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 495 states and 741 transitions.
[2025-03-09 07:36:11,981 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 495 to 495.
[2025-03-09 07:36:11,982 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 495 states, 495 states have (on average 1.496969696969697) internal successors, (741), 494 states have internal predecessors, (741), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:11,984 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 495 states to 495 states and 741 transitions.
[2025-03-09 07:36:11,984 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 495 states and 741 transitions.
[2025-03-09 07:36:11,984 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:11,985 INFO  L432   stractBuchiCegarLoop]: Abstraction has 495 states and 741 transitions.
[2025-03-09 07:36:11,985 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 4 ============
[2025-03-09 07:36:11,985 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 495 states and 741 transitions.
[2025-03-09 07:36:11,987 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 418
[2025-03-09 07:36:11,987 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:11,987 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:11,988 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:11,988 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:11,988 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:11,989 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:11,989 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:11,989 INFO  L85        PathProgramCache]: Analyzing trace with hash 1754318237, now seen corresponding path program 1 times
[2025-03-09 07:36:11,989 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:11,989 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254839397]
[2025-03-09 07:36:11,990 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:11,990 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:11,996 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:12,002 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:12,002 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:12,002 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:12,034 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:12,034 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:12,034 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254839397]
[2025-03-09 07:36:12,034 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254839397] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:12,034 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:12,034 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:12,034 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590300040]
[2025-03-09 07:36:12,034 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:12,034 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-09 07:36:12,035 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:12,035 INFO  L85        PathProgramCache]: Analyzing trace with hash 1738434401, now seen corresponding path program 1 times
[2025-03-09 07:36:12,035 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:12,035 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027529811]
[2025-03-09 07:36:12,035 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:12,035 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:12,041 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes.
[2025-03-09 07:36:12,044 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements.
[2025-03-09 07:36:12,044 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:12,044 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:12,067 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:12,067 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:12,067 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1027529811]
[2025-03-09 07:36:12,068 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1027529811] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:12,068 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:12,068 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:12,068 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [326355795]
[2025-03-09 07:36:12,068 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:12,068 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:12,070 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:12,071 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:12,071 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:12,071 INFO  L87              Difference]: Start difference. First operand 495 states and 741 transitions. cyclomatic complexity: 247 Second operand  has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:12,094 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:12,094 INFO  L93              Difference]: Finished difference Result 495 states and 740 transitions.
[2025-03-09 07:36:12,094 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 495 states and 740 transitions.
[2025-03-09 07:36:12,097 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 418
[2025-03-09 07:36:12,099 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 495 states to 495 states and 740 transitions.
[2025-03-09 07:36:12,099 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 495
[2025-03-09 07:36:12,099 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 495
[2025-03-09 07:36:12,099 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 495 states and 740 transitions.
[2025-03-09 07:36:12,100 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:12,100 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 495 states and 740 transitions.
[2025-03-09 07:36:12,100 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 495 states and 740 transitions.
[2025-03-09 07:36:12,104 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 495 to 495.
[2025-03-09 07:36:12,105 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 495 states, 495 states have (on average 1.494949494949495) internal successors, (740), 494 states have internal predecessors, (740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:12,107 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 495 states to 495 states and 740 transitions.
[2025-03-09 07:36:12,107 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 495 states and 740 transitions.
[2025-03-09 07:36:12,107 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:12,108 INFO  L432   stractBuchiCegarLoop]: Abstraction has 495 states and 740 transitions.
[2025-03-09 07:36:12,108 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 5 ============
[2025-03-09 07:36:12,108 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 495 states and 740 transitions.
[2025-03-09 07:36:12,109 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 418
[2025-03-09 07:36:12,109 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:12,109 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:12,110 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:12,110 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:12,110 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:12,111 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:12,111 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:12,111 INFO  L85        PathProgramCache]: Analyzing trace with hash 1963016540, now seen corresponding path program 1 times
[2025-03-09 07:36:12,111 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:12,111 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343303327]
[2025-03-09 07:36:12,111 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:12,111 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:12,117 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:12,119 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:12,120 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:12,120 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:12,138 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:12,138 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:12,138 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1343303327]
[2025-03-09 07:36:12,138 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1343303327] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:12,138 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:12,138 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:12,138 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1292930719]
[2025-03-09 07:36:12,138 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:12,139 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-09 07:36:12,139 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:12,139 INFO  L85        PathProgramCache]: Analyzing trace with hash 313124740, now seen corresponding path program 2 times
[2025-03-09 07:36:12,140 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:12,140 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [378023257]
[2025-03-09 07:36:12,140 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-09 07:36:12,141 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:12,148 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 80 statements into 1 equivalence classes.
[2025-03-09 07:36:12,150 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 80 of 80 statements.
[2025-03-09 07:36:12,150 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-09 07:36:12,150 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:12,175 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:12,175 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:12,175 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [378023257]
[2025-03-09 07:36:12,175 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [378023257] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:12,175 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:12,175 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:12,175 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753200605]
[2025-03-09 07:36:12,175 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:12,176 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:12,176 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:12,176 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:12,176 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:12,176 INFO  L87              Difference]: Start difference. First operand 495 states and 740 transitions. cyclomatic complexity: 246 Second operand  has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:12,184 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:12,185 INFO  L93              Difference]: Finished difference Result 495 states and 739 transitions.
[2025-03-09 07:36:12,185 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 495 states and 739 transitions.
[2025-03-09 07:36:12,187 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 418
[2025-03-09 07:36:12,189 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 495 states to 495 states and 739 transitions.
[2025-03-09 07:36:12,189 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 495
[2025-03-09 07:36:12,190 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 495
[2025-03-09 07:36:12,190 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 495 states and 739 transitions.
[2025-03-09 07:36:12,190 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:12,190 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 495 states and 739 transitions.
[2025-03-09 07:36:12,191 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 495 states and 739 transitions.
[2025-03-09 07:36:12,195 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 495 to 495.
[2025-03-09 07:36:12,196 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 495 states, 495 states have (on average 1.492929292929293) internal successors, (739), 494 states have internal predecessors, (739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:12,197 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 495 states to 495 states and 739 transitions.
[2025-03-09 07:36:12,197 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 495 states and 739 transitions.
[2025-03-09 07:36:12,197 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:12,199 INFO  L432   stractBuchiCegarLoop]: Abstraction has 495 states and 739 transitions.
[2025-03-09 07:36:12,199 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 6 ============
[2025-03-09 07:36:12,199 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 495 states and 739 transitions.
[2025-03-09 07:36:12,201 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 418
[2025-03-09 07:36:12,201 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:12,201 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:12,202 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:12,202 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:12,202 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:12,202 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:12,203 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:12,203 INFO  L85        PathProgramCache]: Analyzing trace with hash -524103235, now seen corresponding path program 1 times
[2025-03-09 07:36:12,203 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:12,203 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1337226952]
[2025-03-09 07:36:12,203 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:12,203 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:12,208 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:12,218 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:12,218 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:12,218 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:12,269 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:12,269 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:12,269 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1337226952]
[2025-03-09 07:36:12,269 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1337226952] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:12,269 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:12,269 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:12,269 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054031691]
[2025-03-09 07:36:12,269 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:12,270 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-09 07:36:12,270 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:12,270 INFO  L85        PathProgramCache]: Analyzing trace with hash 319015911, now seen corresponding path program 1 times
[2025-03-09 07:36:12,270 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:12,270 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133756213]
[2025-03-09 07:36:12,270 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:12,270 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:12,278 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes.
[2025-03-09 07:36:12,283 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements.
[2025-03-09 07:36:12,286 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:12,286 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:12,313 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:12,313 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:12,313 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133756213]
[2025-03-09 07:36:12,313 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133756213] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:12,313 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:12,313 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:12,313 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [156665610]
[2025-03-09 07:36:12,314 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:12,314 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:12,314 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:12,314 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-09 07:36:12,314 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-09 07:36:12,314 INFO  L87              Difference]: Start difference. First operand 495 states and 739 transitions. cyclomatic complexity: 245 Second operand  has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:12,416 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:12,416 INFO  L93              Difference]: Finished difference Result 869 states and 1292 transitions.
[2025-03-09 07:36:12,416 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 869 states and 1292 transitions.
[2025-03-09 07:36:12,420 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 781
[2025-03-09 07:36:12,424 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 869 states to 869 states and 1292 transitions.
[2025-03-09 07:36:12,424 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 869
[2025-03-09 07:36:12,425 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 869
[2025-03-09 07:36:12,425 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 869 states and 1292 transitions.
[2025-03-09 07:36:12,426 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:12,426 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 869 states and 1292 transitions.
[2025-03-09 07:36:12,428 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 869 states and 1292 transitions.
[2025-03-09 07:36:12,437 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 869 to 869.
[2025-03-09 07:36:12,438 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 869 states, 869 states have (on average 1.4867663981588033) internal successors, (1292), 868 states have internal predecessors, (1292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:12,460 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 869 states to 869 states and 1292 transitions.
[2025-03-09 07:36:12,461 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 869 states and 1292 transitions.
[2025-03-09 07:36:12,461 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-09 07:36:12,463 INFO  L432   stractBuchiCegarLoop]: Abstraction has 869 states and 1292 transitions.
[2025-03-09 07:36:12,463 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 7 ============
[2025-03-09 07:36:12,463 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 869 states and 1292 transitions.
[2025-03-09 07:36:12,466 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 781
[2025-03-09 07:36:12,466 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:12,466 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:12,467 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:12,467 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:12,468 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:12,468 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:12,469 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:12,469 INFO  L85        PathProgramCache]: Analyzing trace with hash -632848579, now seen corresponding path program 1 times
[2025-03-09 07:36:12,469 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:12,469 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139863819]
[2025-03-09 07:36:12,469 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:12,469 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:12,474 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:12,478 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:12,480 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:12,480 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:12,510 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:12,510 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:12,510 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139863819]
[2025-03-09 07:36:12,510 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139863819] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:12,510 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:12,511 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-09 07:36:12,511 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [445388523]
[2025-03-09 07:36:12,511 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:12,511 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-09 07:36:12,511 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:12,511 INFO  L85        PathProgramCache]: Analyzing trace with hash -1409606691, now seen corresponding path program 1 times
[2025-03-09 07:36:12,511 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:12,511 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454084896]
[2025-03-09 07:36:12,512 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:12,512 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:12,517 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes.
[2025-03-09 07:36:12,521 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements.
[2025-03-09 07:36:12,521 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:12,521 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:12,544 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:12,544 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:12,544 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [454084896]
[2025-03-09 07:36:12,544 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [454084896] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:12,544 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:12,544 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:12,545 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [370048638]
[2025-03-09 07:36:12,545 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:12,545 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:12,545 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:12,545 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:12,545 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:12,545 INFO  L87              Difference]: Start difference. First operand 869 states and 1292 transitions. cyclomatic complexity: 425 Second operand  has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:12,602 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:12,602 INFO  L93              Difference]: Finished difference Result 1548 states and 2283 transitions.
[2025-03-09 07:36:12,602 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 1548 states and 2283 transitions.
[2025-03-09 07:36:12,611 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 1457
[2025-03-09 07:36:12,618 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 1548 states to 1548 states and 2283 transitions.
[2025-03-09 07:36:12,618 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 1548
[2025-03-09 07:36:12,620 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 1548
[2025-03-09 07:36:12,620 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 1548 states and 2283 transitions.
[2025-03-09 07:36:12,622 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:12,622 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 1548 states and 2283 transitions.
[2025-03-09 07:36:12,623 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 1548 states and 2283 transitions.
[2025-03-09 07:36:12,646 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 1548 to 1546.
[2025-03-09 07:36:12,648 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 1546 states, 1546 states have (on average 1.4754204398447606) internal successors, (2281), 1545 states have internal predecessors, (2281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:12,653 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 1546 states to 1546 states and 2281 transitions.
[2025-03-09 07:36:12,654 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 1546 states and 2281 transitions.
[2025-03-09 07:36:12,654 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:12,656 INFO  L432   stractBuchiCegarLoop]: Abstraction has 1546 states and 2281 transitions.
[2025-03-09 07:36:12,656 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 8 ============
[2025-03-09 07:36:12,656 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 1546 states and 2281 transitions.
[2025-03-09 07:36:12,662 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 1455
[2025-03-09 07:36:12,663 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:12,663 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:12,664 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:12,664 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:12,664 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:12,664 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:12,664 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:12,665 INFO  L85        PathProgramCache]: Analyzing trace with hash -932422054, now seen corresponding path program 1 times
[2025-03-09 07:36:12,665 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:12,665 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2103109777]
[2025-03-09 07:36:12,665 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:12,665 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:12,671 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:12,674 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:12,674 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:12,674 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:12,711 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:12,711 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:12,711 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2103109777]
[2025-03-09 07:36:12,711 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2103109777] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:12,711 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:12,711 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-09 07:36:12,711 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1866141942]
[2025-03-09 07:36:12,711 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:12,712 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-09 07:36:12,712 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:12,712 INFO  L85        PathProgramCache]: Analyzing trace with hash -1709180166, now seen corresponding path program 1 times
[2025-03-09 07:36:12,712 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:12,712 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435064068]
[2025-03-09 07:36:12,712 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:12,712 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:12,719 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes.
[2025-03-09 07:36:12,723 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements.
[2025-03-09 07:36:12,723 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:12,723 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:12,744 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:12,744 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:12,744 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435064068]
[2025-03-09 07:36:12,745 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435064068] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:12,746 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:12,746 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:12,746 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [423546509]
[2025-03-09 07:36:12,746 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:12,746 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:12,746 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:12,746 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:12,746 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:12,746 INFO  L87              Difference]: Start difference. First operand 1546 states and 2281 transitions. cyclomatic complexity: 739 Second operand  has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:12,810 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:12,810 INFO  L93              Difference]: Finished difference Result 2802 states and 4107 transitions.
[2025-03-09 07:36:12,810 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 2802 states and 4107 transitions.
[2025-03-09 07:36:12,825 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 2704
[2025-03-09 07:36:12,838 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 2802 states to 2802 states and 4107 transitions.
[2025-03-09 07:36:12,839 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 2802
[2025-03-09 07:36:12,840 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 2802
[2025-03-09 07:36:12,841 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 2802 states and 4107 transitions.
[2025-03-09 07:36:12,845 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:12,845 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 2802 states and 4107 transitions.
[2025-03-09 07:36:12,848 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 2802 states and 4107 transitions.
[2025-03-09 07:36:12,888 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 2802 to 2798.
[2025-03-09 07:36:12,892 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 2798 states, 2798 states have (on average 1.4664045746962115) internal successors, (4103), 2797 states have internal predecessors, (4103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:12,902 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 2798 states to 2798 states and 4103 transitions.
[2025-03-09 07:36:12,902 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 2798 states and 4103 transitions.
[2025-03-09 07:36:12,903 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:12,904 INFO  L432   stractBuchiCegarLoop]: Abstraction has 2798 states and 4103 transitions.
[2025-03-09 07:36:12,905 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 9 ============
[2025-03-09 07:36:12,905 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 2798 states and 4103 transitions.
[2025-03-09 07:36:12,917 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 2700
[2025-03-09 07:36:12,917 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:12,917 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:12,918 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:12,919 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:12,919 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:12,919 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:12,920 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:12,920 INFO  L85        PathProgramCache]: Analyzing trace with hash 1861883703, now seen corresponding path program 1 times
[2025-03-09 07:36:12,920 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:12,920 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514262446]
[2025-03-09 07:36:12,920 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:12,920 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:12,926 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:12,929 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:12,929 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:12,929 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:12,965 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:12,965 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:12,965 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [514262446]
[2025-03-09 07:36:12,965 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [514262446] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:12,965 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:12,965 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:12,966 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1879860448]
[2025-03-09 07:36:12,966 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:12,966 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-09 07:36:12,966 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:12,967 INFO  L85        PathProgramCache]: Analyzing trace with hash -1409606691, now seen corresponding path program 2 times
[2025-03-09 07:36:12,967 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:12,967 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1126435147]
[2025-03-09 07:36:12,967 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-09 07:36:12,967 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:12,974 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 80 statements into 1 equivalence classes.
[2025-03-09 07:36:12,977 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 80 of 80 statements.
[2025-03-09 07:36:12,977 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-09 07:36:12,977 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:12,998 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:12,998 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:12,998 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1126435147]
[2025-03-09 07:36:12,999 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1126435147] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:12,999 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:12,999 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:12,999 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2068483796]
[2025-03-09 07:36:12,999 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:12,999 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:12,999 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:12,999 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-03-09 07:36:12,999 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-03-09 07:36:12,999 INFO  L87              Difference]: Start difference. First operand 2798 states and 4103 transitions. cyclomatic complexity: 1313 Second operand  has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:13,136 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:13,136 INFO  L93              Difference]: Finished difference Result 6348 states and 9235 transitions.
[2025-03-09 07:36:13,136 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 6348 states and 9235 transitions.
[2025-03-09 07:36:13,176 INFO  L131   ngComponentsAnalysis]: Automaton has 12 accepting balls. 6215
[2025-03-09 07:36:13,208 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 6348 states to 6348 states and 9235 transitions.
[2025-03-09 07:36:13,208 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 6348
[2025-03-09 07:36:13,215 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 6348
[2025-03-09 07:36:13,215 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 6348 states and 9235 transitions.
[2025-03-09 07:36:13,226 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:13,226 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 6348 states and 9235 transitions.
[2025-03-09 07:36:13,231 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 6348 states and 9235 transitions.
[2025-03-09 07:36:13,332 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 6348 to 5113.
[2025-03-09 07:36:13,340 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 5113 states, 5113 states have (on average 1.4605906512810483) internal successors, (7468), 5112 states have internal predecessors, (7468), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:13,353 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 5113 states to 5113 states and 7468 transitions.
[2025-03-09 07:36:13,354 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 5113 states and 7468 transitions.
[2025-03-09 07:36:13,354 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-03-09 07:36:13,355 INFO  L432   stractBuchiCegarLoop]: Abstraction has 5113 states and 7468 transitions.
[2025-03-09 07:36:13,355 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 10 ============
[2025-03-09 07:36:13,355 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 5113 states and 7468 transitions.
[2025-03-09 07:36:13,370 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 5004
[2025-03-09 07:36:13,370 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:13,370 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:13,371 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:13,371 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:13,371 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:13,371 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:13,372 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:13,372 INFO  L85        PathProgramCache]: Analyzing trace with hash 486996436, now seen corresponding path program 1 times
[2025-03-09 07:36:13,372 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:13,372 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589748566]
[2025-03-09 07:36:13,372 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:13,372 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:13,378 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:13,382 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:13,383 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:13,383 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:13,404 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:13,405 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:13,405 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [589748566]
[2025-03-09 07:36:13,405 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [589748566] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:13,405 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:13,405 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-09 07:36:13,405 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045239794]
[2025-03-09 07:36:13,405 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:13,405 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-09 07:36:13,406 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:13,406 INFO  L85        PathProgramCache]: Analyzing trace with hash -1709180166, now seen corresponding path program 2 times
[2025-03-09 07:36:13,406 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:13,406 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [79341697]
[2025-03-09 07:36:13,406 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-09 07:36:13,406 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:13,411 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 80 statements into 1 equivalence classes.
[2025-03-09 07:36:13,413 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 80 of 80 statements.
[2025-03-09 07:36:13,414 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-09 07:36:13,414 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:13,432 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:13,432 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:13,432 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [79341697]
[2025-03-09 07:36:13,432 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [79341697] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:13,432 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:13,432 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:13,432 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [598216423]
[2025-03-09 07:36:13,433 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:13,433 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:13,433 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:13,433 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:13,433 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:13,433 INFO  L87              Difference]: Start difference. First operand 5113 states and 7468 transitions. cyclomatic complexity: 2363 Second operand  has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:13,510 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:13,510 INFO  L93              Difference]: Finished difference Result 10044 states and 14549 transitions.
[2025-03-09 07:36:13,510 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 10044 states and 14549 transitions.
[2025-03-09 07:36:13,547 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 9880
[2025-03-09 07:36:13,590 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 10044 states to 10044 states and 14549 transitions.
[2025-03-09 07:36:13,590 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 10044
[2025-03-09 07:36:13,598 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 10044
[2025-03-09 07:36:13,598 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 10044 states and 14549 transitions.
[2025-03-09 07:36:13,611 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:13,611 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 10044 states and 14549 transitions.
[2025-03-09 07:36:13,618 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 10044 states and 14549 transitions.
[2025-03-09 07:36:13,713 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 10044 to 9996.
[2025-03-09 07:36:13,728 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 9996 states, 9996 states have (on average 1.449079631852741) internal successors, (14485), 9995 states have internal predecessors, (14485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:13,750 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 9996 states to 9996 states and 14485 transitions.
[2025-03-09 07:36:13,750 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 9996 states and 14485 transitions.
[2025-03-09 07:36:13,751 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:13,752 INFO  L432   stractBuchiCegarLoop]: Abstraction has 9996 states and 14485 transitions.
[2025-03-09 07:36:13,752 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 11 ============
[2025-03-09 07:36:13,752 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 9996 states and 14485 transitions.
[2025-03-09 07:36:13,781 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 9864
[2025-03-09 07:36:13,781 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:13,781 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:13,782 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:13,782 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:13,782 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:13,782 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:13,783 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:13,783 INFO  L85        PathProgramCache]: Analyzing trace with hash 1078271985, now seen corresponding path program 1 times
[2025-03-09 07:36:13,783 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:13,783 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667379128]
[2025-03-09 07:36:13,783 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:13,783 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:13,788 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:13,790 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:13,790 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:13,790 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:13,853 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:13,853 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:13,853 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [667379128]
[2025-03-09 07:36:13,853 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [667379128] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:13,853 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:13,853 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-09 07:36:13,853 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456988751]
[2025-03-09 07:36:13,853 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:13,853 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-09 07:36:13,854 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:13,854 INFO  L85        PathProgramCache]: Analyzing trace with hash -1709180166, now seen corresponding path program 3 times
[2025-03-09 07:36:13,854 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:13,854 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188078343]
[2025-03-09 07:36:13,854 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2
[2025-03-09 07:36:13,854 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:13,859 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 80 statements into 1 equivalence classes.
[2025-03-09 07:36:13,861 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 80 of 80 statements.
[2025-03-09 07:36:13,861 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s)
[2025-03-09 07:36:13,861 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:13,879 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:13,879 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:13,879 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [188078343]
[2025-03-09 07:36:13,879 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [188078343] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:13,879 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:13,879 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:13,879 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1867999553]
[2025-03-09 07:36:13,879 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:13,879 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:13,880 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:13,880 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:13,880 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:13,880 INFO  L87              Difference]: Start difference. First operand 9996 states and 14485 transitions. cyclomatic complexity: 4505 Second operand  has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:13,965 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:13,965 INFO  L93              Difference]: Finished difference Result 14700 states and 21183 transitions.
[2025-03-09 07:36:13,965 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 14700 states and 21183 transitions.
[2025-03-09 07:36:14,010 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 14548
[2025-03-09 07:36:14,050 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 14700 states to 14700 states and 21183 transitions.
[2025-03-09 07:36:14,050 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 14700
[2025-03-09 07:36:14,063 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 14700
[2025-03-09 07:36:14,063 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 14700 states and 21183 transitions.
[2025-03-09 07:36:14,080 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:14,081 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 14700 states and 21183 transitions.
[2025-03-09 07:36:14,094 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 14700 states and 21183 transitions.
[2025-03-09 07:36:14,197 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 14700 to 10161.
[2025-03-09 07:36:14,217 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 10161 states, 10161 states have (on average 1.4476921562838303) internal successors, (14710), 10160 states have internal predecessors, (14710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:14,244 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 10161 states to 10161 states and 14710 transitions.
[2025-03-09 07:36:14,244 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 10161 states and 14710 transitions.
[2025-03-09 07:36:14,244 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:14,244 INFO  L432   stractBuchiCegarLoop]: Abstraction has 10161 states and 14710 transitions.
[2025-03-09 07:36:14,244 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 12 ============
[2025-03-09 07:36:14,245 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 10161 states and 14710 transitions.
[2025-03-09 07:36:14,271 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 10040
[2025-03-09 07:36:14,271 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:14,271 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:14,272 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:14,272 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:14,272 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:14,272 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:14,273 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:14,274 INFO  L85        PathProgramCache]: Analyzing trace with hash 1207354704, now seen corresponding path program 1 times
[2025-03-09 07:36:14,274 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:14,274 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968508510]
[2025-03-09 07:36:14,274 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:14,274 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:14,279 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:14,282 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:14,282 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:14,282 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:14,282 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:14,284 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:14,288 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:14,288 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:14,288 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:14,319 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:14,320 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:14,320 INFO  L85        PathProgramCache]: Analyzing trace with hash -50040683, now seen corresponding path program 1 times
[2025-03-09 07:36:14,320 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:14,320 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295779720]
[2025-03-09 07:36:14,321 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:14,321 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:14,328 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes.
[2025-03-09 07:36:14,331 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements.
[2025-03-09 07:36:14,331 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:14,331 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:14,383 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:14,384 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:14,384 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295779720]
[2025-03-09 07:36:14,384 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295779720] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:14,384 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:14,384 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:14,384 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1031804420]
[2025-03-09 07:36:14,384 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:14,384 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:14,384 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:14,384 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:14,384 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:14,385 INFO  L87              Difference]: Start difference. First operand 10161 states and 14710 transitions. cyclomatic complexity: 4557 Second operand  has 3 states, 3 states have (on average 26.666666666666668) internal successors, (80), 3 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:14,426 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:14,427 INFO  L93              Difference]: Finished difference Result 11875 states and 17178 transitions.
[2025-03-09 07:36:14,427 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 11875 states and 17178 transitions.
[2025-03-09 07:36:14,469 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 11704
[2025-03-09 07:36:14,500 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 11875 states to 11875 states and 17178 transitions.
[2025-03-09 07:36:14,500 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 11875
[2025-03-09 07:36:14,511 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 11875
[2025-03-09 07:36:14,511 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 11875 states and 17178 transitions.
[2025-03-09 07:36:14,526 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:14,527 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 11875 states and 17178 transitions.
[2025-03-09 07:36:14,537 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 11875 states and 17178 transitions.
[2025-03-09 07:36:14,629 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 11875 to 11875.
[2025-03-09 07:36:14,644 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 11875 states, 11875 states have (on average 1.4465684210526315) internal successors, (17178), 11874 states have internal predecessors, (17178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:14,669 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 11875 states to 11875 states and 17178 transitions.
[2025-03-09 07:36:14,669 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 11875 states and 17178 transitions.
[2025-03-09 07:36:14,670 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:14,671 INFO  L432   stractBuchiCegarLoop]: Abstraction has 11875 states and 17178 transitions.
[2025-03-09 07:36:14,671 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 13 ============
[2025-03-09 07:36:14,671 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 11875 states and 17178 transitions.
[2025-03-09 07:36:14,697 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 11704
[2025-03-09 07:36:14,697 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:14,697 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:14,699 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:14,699 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:14,699 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:14,699 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:14,699 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:14,700 INFO  L85        PathProgramCache]: Analyzing trace with hash -373541682, now seen corresponding path program 1 times
[2025-03-09 07:36:14,700 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:14,700 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619630860]
[2025-03-09 07:36:14,700 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:14,700 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:14,704 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:14,706 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:14,706 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:14,706 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:14,734 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:14,734 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:14,734 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1619630860]
[2025-03-09 07:36:14,734 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1619630860] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:14,737 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:14,738 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-09 07:36:14,738 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1877859447]
[2025-03-09 07:36:14,738 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:14,738 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-09 07:36:14,738 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:14,738 INFO  L85        PathProgramCache]: Analyzing trace with hash -706230351, now seen corresponding path program 1 times
[2025-03-09 07:36:14,738 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:14,738 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817186856]
[2025-03-09 07:36:14,738 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:14,738 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:14,746 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes.
[2025-03-09 07:36:14,750 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements.
[2025-03-09 07:36:14,750 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:14,750 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:14,782 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:14,783 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:14,783 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817186856]
[2025-03-09 07:36:14,783 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [817186856] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:14,783 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:14,783 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-03-09 07:36:14,783 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769215579]
[2025-03-09 07:36:14,783 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:14,783 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:14,783 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:14,784 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:14,784 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:14,784 INFO  L87              Difference]: Start difference. First operand 11875 states and 17178 transitions. cyclomatic complexity: 5311 Second operand  has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:14,814 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:14,814 INFO  L93              Difference]: Finished difference Result 10161 states and 14612 transitions.
[2025-03-09 07:36:14,814 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 10161 states and 14612 transitions.
[2025-03-09 07:36:14,896 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 10040
[2025-03-09 07:36:14,925 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 10161 states to 10161 states and 14612 transitions.
[2025-03-09 07:36:14,925 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 10161
[2025-03-09 07:36:14,935 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 10161
[2025-03-09 07:36:14,935 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 10161 states and 14612 transitions.
[2025-03-09 07:36:14,947 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:14,948 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 10161 states and 14612 transitions.
[2025-03-09 07:36:14,957 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 10161 states and 14612 transitions.
[2025-03-09 07:36:15,049 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 10161 to 10161.
[2025-03-09 07:36:15,064 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 10161 states, 10161 states have (on average 1.438047436275957) internal successors, (14612), 10160 states have internal predecessors, (14612), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:15,087 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 10161 states to 10161 states and 14612 transitions.
[2025-03-09 07:36:15,088 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 10161 states and 14612 transitions.
[2025-03-09 07:36:15,088 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:15,089 INFO  L432   stractBuchiCegarLoop]: Abstraction has 10161 states and 14612 transitions.
[2025-03-09 07:36:15,089 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 14 ============
[2025-03-09 07:36:15,089 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 10161 states and 14612 transitions.
[2025-03-09 07:36:15,119 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 10040
[2025-03-09 07:36:15,120 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:15,120 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:15,121 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:15,123 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:15,123 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:15,123 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:15,124 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:15,124 INFO  L85        PathProgramCache]: Analyzing trace with hash 1207354704, now seen corresponding path program 2 times
[2025-03-09 07:36:15,124 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:15,124 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568075299]
[2025-03-09 07:36:15,124 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-09 07:36:15,124 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:15,131 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:15,134 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:15,135 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-09 07:36:15,135 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:15,135 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:15,137 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:15,142 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:15,142 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:15,142 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:15,157 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:15,159 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:15,160 INFO  L85        PathProgramCache]: Analyzing trace with hash -658117546, now seen corresponding path program 1 times
[2025-03-09 07:36:15,160 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:15,160 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [997113958]
[2025-03-09 07:36:15,160 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:15,160 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:15,168 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes.
[2025-03-09 07:36:15,171 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements.
[2025-03-09 07:36:15,171 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:15,172 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:15,206 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:15,207 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:15,207 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [997113958]
[2025-03-09 07:36:15,207 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [997113958] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:15,207 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:15,207 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-03-09 07:36:15,207 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1267820147]
[2025-03-09 07:36:15,207 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:15,207 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:15,207 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:15,208 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2025-03-09 07:36:15,208 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2025-03-09 07:36:15,208 INFO  L87              Difference]: Start difference. First operand 10161 states and 14612 transitions. cyclomatic complexity: 4459 Second operand  has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:15,286 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:15,286 INFO  L93              Difference]: Finished difference Result 10385 states and 14836 transitions.
[2025-03-09 07:36:15,286 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 10385 states and 14836 transitions.
[2025-03-09 07:36:15,327 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 10264
[2025-03-09 07:36:15,357 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 10385 states to 10385 states and 14836 transitions.
[2025-03-09 07:36:15,357 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 10385
[2025-03-09 07:36:15,369 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 10385
[2025-03-09 07:36:15,370 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 10385 states and 14836 transitions.
[2025-03-09 07:36:15,382 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:15,382 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 10385 states and 14836 transitions.
[2025-03-09 07:36:15,391 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 10385 states and 14836 transitions.
[2025-03-09 07:36:15,484 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 10385 to 10257.
[2025-03-09 07:36:15,499 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 10257 states, 10257 states have (on average 1.4339475480159891) internal successors, (14708), 10256 states have internal predecessors, (14708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:15,517 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 10257 states to 10257 states and 14708 transitions.
[2025-03-09 07:36:15,517 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 10257 states and 14708 transitions.
[2025-03-09 07:36:15,518 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 
[2025-03-09 07:36:15,519 INFO  L432   stractBuchiCegarLoop]: Abstraction has 10257 states and 14708 transitions.
[2025-03-09 07:36:15,519 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 15 ============
[2025-03-09 07:36:15,519 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 10257 states and 14708 transitions.
[2025-03-09 07:36:15,546 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 10136
[2025-03-09 07:36:15,546 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:15,546 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:15,547 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:15,547 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:15,548 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:15,548 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:15,549 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:15,549 INFO  L85        PathProgramCache]: Analyzing trace with hash 1207354704, now seen corresponding path program 3 times
[2025-03-09 07:36:15,549 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:15,549 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670526882]
[2025-03-09 07:36:15,549 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2
[2025-03-09 07:36:15,549 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:15,555 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:15,558 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:15,558 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s)
[2025-03-09 07:36:15,558 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:15,558 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:15,561 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:15,565 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:15,565 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:15,566 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:15,579 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:15,580 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:15,580 INFO  L85        PathProgramCache]: Analyzing trace with hash 319871996, now seen corresponding path program 1 times
[2025-03-09 07:36:15,580 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:15,580 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457328680]
[2025-03-09 07:36:15,581 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:15,581 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:15,588 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 85 statements into 1 equivalence classes.
[2025-03-09 07:36:15,593 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 85 of 85 statements.
[2025-03-09 07:36:15,593 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:15,593 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:15,654 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:15,654 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:15,654 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [457328680]
[2025-03-09 07:36:15,654 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [457328680] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:15,654 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:15,654 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-03-09 07:36:15,654 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [975856954]
[2025-03-09 07:36:15,654 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:15,655 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:15,655 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:15,655 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2025-03-09 07:36:15,655 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2025-03-09 07:36:15,655 INFO  L87              Difference]: Start difference. First operand 10257 states and 14708 transitions. cyclomatic complexity: 4459 Second operand  has 5 states, 5 states have (on average 17.0) internal successors, (85), 5 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:15,817 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:15,818 INFO  L93              Difference]: Finished difference Result 10521 states and 14899 transitions.
[2025-03-09 07:36:15,818 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 10521 states and 14899 transitions.
[2025-03-09 07:36:15,852 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 10400
[2025-03-09 07:36:15,876 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 10521 states to 10521 states and 14899 transitions.
[2025-03-09 07:36:15,877 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 10521
[2025-03-09 07:36:15,884 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 10521
[2025-03-09 07:36:15,884 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 10521 states and 14899 transitions.
[2025-03-09 07:36:15,893 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:15,893 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 10521 states and 14899 transitions.
[2025-03-09 07:36:15,900 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 10521 states and 14899 transitions.
[2025-03-09 07:36:15,968 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 10521 to 10521.
[2025-03-09 07:36:15,982 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 10521 states, 10521 states have (on average 1.4161201406710389) internal successors, (14899), 10520 states have internal predecessors, (14899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:16,003 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 10521 states to 10521 states and 14899 transitions.
[2025-03-09 07:36:16,004 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 10521 states and 14899 transitions.
[2025-03-09 07:36:16,004 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 
[2025-03-09 07:36:16,004 INFO  L432   stractBuchiCegarLoop]: Abstraction has 10521 states and 14899 transitions.
[2025-03-09 07:36:16,005 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 16 ============
[2025-03-09 07:36:16,005 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 10521 states and 14899 transitions.
[2025-03-09 07:36:16,033 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 10400
[2025-03-09 07:36:16,033 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:16,033 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:16,034 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:16,034 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:16,035 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:16,035 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:16,035 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:16,035 INFO  L85        PathProgramCache]: Analyzing trace with hash 1207354704, now seen corresponding path program 4 times
[2025-03-09 07:36:16,036 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:16,036 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351485944]
[2025-03-09 07:36:16,036 INFO  L95    rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST
[2025-03-09 07:36:16,036 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:16,042 INFO  L108    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 71 statements into 2 equivalence classes.
[2025-03-09 07:36:16,046 INFO  L111    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:16,046 INFO  L114    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s)
[2025-03-09 07:36:16,046 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:16,046 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:16,049 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:16,052 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:16,052 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:16,052 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:16,060 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:16,065 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:16,065 INFO  L85        PathProgramCache]: Analyzing trace with hash 1840870910, now seen corresponding path program 1 times
[2025-03-09 07:36:16,065 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:16,065 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [707925826]
[2025-03-09 07:36:16,065 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:16,066 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:16,071 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 85 statements into 1 equivalence classes.
[2025-03-09 07:36:16,074 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 85 of 85 statements.
[2025-03-09 07:36:16,077 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:16,077 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:16,103 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:16,104 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:16,104 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [707925826]
[2025-03-09 07:36:16,104 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [707925826] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:16,105 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:16,105 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:16,105 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1519495161]
[2025-03-09 07:36:16,105 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:16,105 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:16,105 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:16,105 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:16,105 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:16,105 INFO  L87              Difference]: Start difference. First operand 10521 states and 14899 transitions. cyclomatic complexity: 4386 Second operand  has 3 states, 3 states have (on average 28.333333333333332) internal successors, (85), 3 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:16,166 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:16,167 INFO  L93              Difference]: Finished difference Result 18169 states and 25411 transitions.
[2025-03-09 07:36:16,167 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 18169 states and 25411 transitions.
[2025-03-09 07:36:16,230 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 18000
[2025-03-09 07:36:16,279 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 18169 states to 18169 states and 25411 transitions.
[2025-03-09 07:36:16,279 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 18169
[2025-03-09 07:36:16,291 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 18169
[2025-03-09 07:36:16,292 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 18169 states and 25411 transitions.
[2025-03-09 07:36:16,306 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:16,306 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 18169 states and 25411 transitions.
[2025-03-09 07:36:16,320 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 18169 states and 25411 transitions.
[2025-03-09 07:36:16,592 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 18169 to 17593.
[2025-03-09 07:36:16,612 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 17593 states, 17593 states have (on average 1.4016370147217643) internal successors, (24659), 17592 states have internal predecessors, (24659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:16,647 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 17593 states to 17593 states and 24659 transitions.
[2025-03-09 07:36:16,647 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 17593 states and 24659 transitions.
[2025-03-09 07:36:16,648 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:16,649 INFO  L432   stractBuchiCegarLoop]: Abstraction has 17593 states and 24659 transitions.
[2025-03-09 07:36:16,649 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 17 ============
[2025-03-09 07:36:16,649 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 17593 states and 24659 transitions.
[2025-03-09 07:36:16,694 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 17424
[2025-03-09 07:36:16,694 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:16,694 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:16,696 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:16,696 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:16,696 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:16,699 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1;" "assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_time_events } true;" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:16,700 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:16,700 INFO  L85        PathProgramCache]: Analyzing trace with hash 1207354704, now seen corresponding path program 5 times
[2025-03-09 07:36:16,700 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:16,700 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [186463007]
[2025-03-09 07:36:16,700 INFO  L95    rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1
[2025-03-09 07:36:16,700 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:16,705 INFO  L108    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:16,710 INFO  L111    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:16,711 INFO  L114    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-09 07:36:16,711 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:16,711 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:16,713 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:16,716 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:16,718 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:16,718 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:16,724 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:16,725 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:16,725 INFO  L85        PathProgramCache]: Analyzing trace with hash 1931410683, now seen corresponding path program 1 times
[2025-03-09 07:36:16,725 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:16,725 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540338914]
[2025-03-09 07:36:16,725 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:16,725 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:16,732 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 135 statements into 1 equivalence classes.
[2025-03-09 07:36:16,736 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 135 of 135 statements.
[2025-03-09 07:36:16,736 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:16,737 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:16,761 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:16,762 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:16,762 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [540338914]
[2025-03-09 07:36:16,762 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [540338914] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:16,762 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:16,762 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:16,762 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164657326]
[2025-03-09 07:36:16,762 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:16,762 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:16,763 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:16,763 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:16,763 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:16,763 INFO  L87              Difference]: Start difference. First operand 17593 states and 24659 transitions. cyclomatic complexity: 7074 Second operand  has 3 states, 3 states have (on average 45.0) internal successors, (135), 3 states have internal predecessors, (135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:16,866 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:16,866 INFO  L93              Difference]: Finished difference Result 31896 states and 44465 transitions.
[2025-03-09 07:36:16,866 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 31896 states and 44465 transitions.
[2025-03-09 07:36:16,977 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 31632
[2025-03-09 07:36:17,069 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 31896 states to 31896 states and 44465 transitions.
[2025-03-09 07:36:17,069 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 31896
[2025-03-09 07:36:17,093 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 31896
[2025-03-09 07:36:17,093 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 31896 states and 44465 transitions.
[2025-03-09 07:36:17,117 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:17,118 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 31896 states and 44465 transitions.
[2025-03-09 07:36:17,139 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 31896 states and 44465 transitions.
[2025-03-09 07:36:17,529 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 31896 to 31864.
[2025-03-09 07:36:17,566 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 31864 states, 31864 states have (on average 1.3944576952046197) internal successors, (44433), 31863 states have internal predecessors, (44433), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:17,636 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 31864 states to 31864 states and 44433 transitions.
[2025-03-09 07:36:17,636 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 31864 states and 44433 transitions.
[2025-03-09 07:36:17,639 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:17,639 INFO  L432   stractBuchiCegarLoop]: Abstraction has 31864 states and 44433 transitions.
[2025-03-09 07:36:17,639 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 18 ============
[2025-03-09 07:36:17,639 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 31864 states and 44433 transitions.
[2025-03-09 07:36:17,738 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 31600
[2025-03-09 07:36:17,738 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:17,738 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:17,742 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:17,742 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:17,742 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" 
[2025-03-09 07:36:17,743 INFO  L754   eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;" "assume 0 == ~m_pc~0;" "~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;" "assume { :end_inline_immediate_notify } true;~E_1~0 := 2;" "~m_pc~0 := 1;~m_st~0 := 2;" "assume { :end_inline_master } true;" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume !(1 == ~M_E~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1;" "assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_time_events } true;" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1;" "assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_time_events } true;" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" 
[2025-03-09 07:36:17,743 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:17,744 INFO  L85        PathProgramCache]: Analyzing trace with hash 1207354704, now seen corresponding path program 6 times
[2025-03-09 07:36:17,744 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:17,744 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1258327612]
[2025-03-09 07:36:17,744 INFO  L95    rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE
[2025-03-09 07:36:17,744 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:17,751 INFO  L108    AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:17,754 INFO  L111    AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:17,754 INFO  L114    AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s)
[2025-03-09 07:36:17,754 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:17,754 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:17,760 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 71 statements into 1 equivalence classes.
[2025-03-09 07:36:17,767 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 71 of 71 statements.
[2025-03-09 07:36:17,768 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:17,768 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:17,774 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:17,775 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:17,775 INFO  L85        PathProgramCache]: Analyzing trace with hash -970763589, now seen corresponding path program 1 times
[2025-03-09 07:36:17,775 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:17,775 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140235230]
[2025-03-09 07:36:17,775 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:17,775 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:17,791 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 324 statements into 1 equivalence classes.
[2025-03-09 07:36:17,794 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 324 of 324 statements.
[2025-03-09 07:36:17,794 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:17,794 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:17,853 INFO  L134       CoverageAnalysis]: Checked inductivity of 142 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 131 trivial. 0 not checked.
[2025-03-09 07:36:17,853 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:17,854 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140235230]
[2025-03-09 07:36:17,854 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [140235230] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:17,854 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:17,854 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:17,854 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916121710]
[2025-03-09 07:36:17,854 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:17,854 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-03-09 07:36:17,854 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:17,855 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:17,855 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:17,855 INFO  L87              Difference]: Start difference. First operand 31864 states and 44433 transitions. cyclomatic complexity: 12585 Second operand  has 3 states, 3 states have (on average 67.33333333333333) internal successors, (202), 3 states have internal predecessors, (202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:17,968 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:17,968 INFO  L93              Difference]: Finished difference Result 35053 states and 48450 transitions.
[2025-03-09 07:36:17,968 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 35053 states and 48450 transitions.
[2025-03-09 07:36:18,126 INFO  L131   ngComponentsAnalysis]: Automaton has 20 accepting balls. 34440
[2025-03-09 07:36:18,228 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 35053 states to 35053 states and 48450 transitions.
[2025-03-09 07:36:18,229 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 35053
[2025-03-09 07:36:18,255 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 35053
[2025-03-09 07:36:18,255 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 35053 states and 48450 transitions.
[2025-03-09 07:36:18,285 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:18,286 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 35053 states and 48450 transitions.
[2025-03-09 07:36:18,309 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 35053 states and 48450 transitions.
[2025-03-09 07:36:18,827 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 35053 to 33581.
[2025-03-09 07:36:18,856 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 33581 states, 33581 states have (on average 1.3856049551829903) internal successors, (46530), 33580 states have internal predecessors, (46530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:18,900 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 33581 states to 33581 states and 46530 transitions.
[2025-03-09 07:36:18,900 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 33581 states and 46530 transitions.
[2025-03-09 07:36:18,900 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:18,901 INFO  L432   stractBuchiCegarLoop]: Abstraction has 33581 states and 46530 transitions.
[2025-03-09 07:36:18,901 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 19 ============
[2025-03-09 07:36:18,901 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 33581 states and 46530 transitions.
[2025-03-09 07:36:18,987 INFO  L131   ngComponentsAnalysis]: Automaton has 20 accepting balls. 32968
[2025-03-09 07:36:18,988 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:18,988 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:18,988 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:18,988 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:18,989 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" 
[2025-03-09 07:36:18,989 INFO  L754   eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" 
[2025-03-09 07:36:18,989 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:18,989 INFO  L85        PathProgramCache]: Analyzing trace with hash -1226709042, now seen corresponding path program 1 times
[2025-03-09 07:36:18,989 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:18,989 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185543350]
[2025-03-09 07:36:18,989 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:18,989 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:18,994 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 72 statements into 1 equivalence classes.
[2025-03-09 07:36:18,997 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-09 07:36:18,997 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:18,997 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:18,997 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:18,999 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 72 statements into 1 equivalence classes.
[2025-03-09 07:36:19,003 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-09 07:36:19,003 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:19,003 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:19,010 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:19,011 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:19,012 INFO  L85        PathProgramCache]: Analyzing trace with hash -364595178, now seen corresponding path program 1 times
[2025-03-09 07:36:19,012 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:19,012 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711018269]
[2025-03-09 07:36:19,012 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:19,012 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:19,014 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes.
[2025-03-09 07:36:19,016 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements.
[2025-03-09 07:36:19,016 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:19,016 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:19,016 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:19,017 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes.
[2025-03-09 07:36:19,018 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements.
[2025-03-09 07:36:19,018 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:19,018 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:19,020 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:19,021 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:19,021 INFO  L85        PathProgramCache]: Analyzing trace with hash -1236886359, now seen corresponding path program 1 times
[2025-03-09 07:36:19,021 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:19,021 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [423026734]
[2025-03-09 07:36:19,021 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:19,022 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:19,027 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 87 statements into 1 equivalence classes.
[2025-03-09 07:36:19,030 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 87 of 87 statements.
[2025-03-09 07:36:19,033 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:19,033 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:19,056 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:19,056 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:19,056 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [423026734]
[2025-03-09 07:36:19,056 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [423026734] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:19,056 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:19,056 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:19,057 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1442057909]
[2025-03-09 07:36:19,057 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:19,132 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:19,132 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:19,133 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:19,133 INFO  L87              Difference]: Start difference. First operand 33581 states and 46530 transitions. cyclomatic complexity: 12969 Second operand  has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:19,234 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:19,234 INFO  L93              Difference]: Finished difference Result 39594 states and 54357 transitions.
[2025-03-09 07:36:19,234 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 39594 states and 54357 transitions.
[2025-03-09 07:36:19,376 INFO  L131   ngComponentsAnalysis]: Automaton has 22 accepting balls. 38497
[2025-03-09 07:36:19,478 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 39594 states to 39594 states and 54357 transitions.
[2025-03-09 07:36:19,479 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 39594
[2025-03-09 07:36:19,509 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 39594
[2025-03-09 07:36:19,509 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 39594 states and 54357 transitions.
[2025-03-09 07:36:19,540 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:19,540 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 39594 states and 54357 transitions.
[2025-03-09 07:36:19,566 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 39594 states and 54357 transitions.
[2025-03-09 07:36:20,098 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 39594 to 37326.
[2025-03-09 07:36:20,148 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 37326 states, 37326 states have (on average 1.3757970315597707) internal successors, (51353), 37325 states have internal predecessors, (51353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:20,220 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 37326 states to 37326 states and 51353 transitions.
[2025-03-09 07:36:20,221 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 37326 states and 51353 transitions.
[2025-03-09 07:36:20,221 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:20,222 INFO  L432   stractBuchiCegarLoop]: Abstraction has 37326 states and 51353 transitions.
[2025-03-09 07:36:20,222 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 20 ============
[2025-03-09 07:36:20,222 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 37326 states and 51353 transitions.
[2025-03-09 07:36:20,361 INFO  L131   ngComponentsAnalysis]: Automaton has 22 accepting balls. 36229
[2025-03-09 07:36:20,361 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:20,361 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:20,362 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:20,362 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:20,363 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" 
[2025-03-09 07:36:20,363 INFO  L754   eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" 
[2025-03-09 07:36:20,363 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:20,363 INFO  L85        PathProgramCache]: Analyzing trace with hash -1226709042, now seen corresponding path program 2 times
[2025-03-09 07:36:20,363 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:20,363 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457463569]
[2025-03-09 07:36:20,364 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-09 07:36:20,364 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:20,371 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 72 statements into 1 equivalence classes.
[2025-03-09 07:36:20,379 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-09 07:36:20,379 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-09 07:36:20,379 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:20,380 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:20,382 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 72 statements into 1 equivalence classes.
[2025-03-09 07:36:20,386 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-09 07:36:20,386 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:20,386 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:20,392 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:20,393 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:20,393 INFO  L85        PathProgramCache]: Analyzing trace with hash 36034236, now seen corresponding path program 1 times
[2025-03-09 07:36:20,393 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:20,393 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583042280]
[2025-03-09 07:36:20,393 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:20,393 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:20,396 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes.
[2025-03-09 07:36:20,397 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements.
[2025-03-09 07:36:20,397 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:20,397 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:20,398 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:20,398 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes.
[2025-03-09 07:36:20,399 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements.
[2025-03-09 07:36:20,399 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:20,399 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:20,400 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:20,401 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:20,401 INFO  L85        PathProgramCache]: Analyzing trace with hash -717167985, now seen corresponding path program 1 times
[2025-03-09 07:36:20,401 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:20,401 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877770301]
[2025-03-09 07:36:20,401 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:20,401 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:20,408 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes.
[2025-03-09 07:36:20,411 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements.
[2025-03-09 07:36:20,411 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:20,411 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:20,439 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:20,439 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:20,439 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [877770301]
[2025-03-09 07:36:20,439 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [877770301] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:20,439 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:20,439 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:20,439 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121373559]
[2025-03-09 07:36:20,440 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:20,519 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:20,520 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:20,520 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:20,520 INFO  L87              Difference]: Start difference. First operand 37326 states and 51353 transitions. cyclomatic complexity: 14049 Second operand  has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:20,821 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:20,822 INFO  L93              Difference]: Finished difference Result 69892 states and 95787 transitions.
[2025-03-09 07:36:20,822 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 69892 states and 95787 transitions.
[2025-03-09 07:36:21,430 INFO  L131   ngComponentsAnalysis]: Automaton has 22 accepting balls. 67706
[2025-03-09 07:36:21,579 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 69892 states to 69892 states and 95787 transitions.
[2025-03-09 07:36:21,579 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 69892
[2025-03-09 07:36:21,628 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 69892
[2025-03-09 07:36:21,628 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 69892 states and 95787 transitions.
[2025-03-09 07:36:21,702 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:21,703 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 69892 states and 95787 transitions.
[2025-03-09 07:36:21,747 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 69892 states and 95787 transitions.
[2025-03-09 07:36:22,302 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 69892 to 68341.
[2025-03-09 07:36:22,364 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 68341 states, 68341 states have (on average 1.3720314306199792) internal successors, (93766), 68340 states have internal predecessors, (93766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:22,469 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 68341 states to 68341 states and 93766 transitions.
[2025-03-09 07:36:22,469 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 68341 states and 93766 transitions.
[2025-03-09 07:36:22,469 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:22,470 INFO  L432   stractBuchiCegarLoop]: Abstraction has 68341 states and 93766 transitions.
[2025-03-09 07:36:22,470 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 21 ============
[2025-03-09 07:36:22,470 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 68341 states and 93766 transitions.
[2025-03-09 07:36:22,795 INFO  L131   ngComponentsAnalysis]: Automaton has 22 accepting balls. 66155
[2025-03-09 07:36:22,795 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:22,795 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:22,796 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:22,796 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:22,796 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" 
[2025-03-09 07:36:22,796 INFO  L754   eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" 
[2025-03-09 07:36:22,797 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:22,797 INFO  L85        PathProgramCache]: Analyzing trace with hash -883929330, now seen corresponding path program 1 times
[2025-03-09 07:36:22,797 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:22,797 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1432375036]
[2025-03-09 07:36:22,797 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:22,798 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:22,807 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 72 statements into 1 equivalence classes.
[2025-03-09 07:36:22,810 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-09 07:36:22,810 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:22,810 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:22,827 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:22,827 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:22,828 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1432375036]
[2025-03-09 07:36:22,828 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1432375036] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:22,828 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:22,828 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:22,828 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [249263798]
[2025-03-09 07:36:22,828 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:22,828 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-03-09 07:36:22,829 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:22,829 INFO  L85        PathProgramCache]: Analyzing trace with hash 271022178, now seen corresponding path program 1 times
[2025-03-09 07:36:22,829 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:22,829 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1155991691]
[2025-03-09 07:36:22,829 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:22,829 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:22,831 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes.
[2025-03-09 07:36:22,833 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements.
[2025-03-09 07:36:22,833 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:22,833 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:22,833 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:22,834 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes.
[2025-03-09 07:36:22,835 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements.
[2025-03-09 07:36:22,835 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:22,835 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:22,837 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:22,907 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:22,908 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:22,908 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:22,908 INFO  L87              Difference]: Start difference. First operand 68341 states and 93766 transitions. cyclomatic complexity: 25447 Second operand  has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:23,156 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:23,157 INFO  L93              Difference]: Finished difference Result 68276 states and 93676 transitions.
[2025-03-09 07:36:23,157 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 68276 states and 93676 transitions.
[2025-03-09 07:36:23,558 INFO  L131   ngComponentsAnalysis]: Automaton has 22 accepting balls. 66155
[2025-03-09 07:36:23,684 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 68276 states to 68276 states and 93676 transitions.
[2025-03-09 07:36:23,684 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 68276
[2025-03-09 07:36:23,718 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 68276
[2025-03-09 07:36:23,718 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 68276 states and 93676 transitions.
[2025-03-09 07:36:23,752 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:23,753 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 68276 states and 93676 transitions.
[2025-03-09 07:36:23,784 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 68276 states and 93676 transitions.
[2025-03-09 07:36:24,268 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 68276 to 68276.
[2025-03-09 07:36:24,325 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 68276 states, 68276 states have (on average 1.3720194504657566) internal successors, (93676), 68275 states have internal predecessors, (93676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:24,589 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 68276 states to 68276 states and 93676 transitions.
[2025-03-09 07:36:24,589 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 68276 states and 93676 transitions.
[2025-03-09 07:36:24,590 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:24,590 INFO  L432   stractBuchiCegarLoop]: Abstraction has 68276 states and 93676 transitions.
[2025-03-09 07:36:24,590 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 22 ============
[2025-03-09 07:36:24,590 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 68276 states and 93676 transitions.
[2025-03-09 07:36:24,752 INFO  L131   ngComponentsAnalysis]: Automaton has 22 accepting balls. 66155
[2025-03-09 07:36:24,753 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:24,753 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:24,753 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:24,753 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:24,754 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" 
[2025-03-09 07:36:24,754 INFO  L754   eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" 
[2025-03-09 07:36:24,754 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:24,755 INFO  L85        PathProgramCache]: Analyzing trace with hash -1226709042, now seen corresponding path program 3 times
[2025-03-09 07:36:24,755 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:24,755 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [376101497]
[2025-03-09 07:36:24,755 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2
[2025-03-09 07:36:24,755 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:24,761 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 72 statements into 1 equivalence classes.
[2025-03-09 07:36:24,764 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-09 07:36:24,765 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s)
[2025-03-09 07:36:24,765 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:24,765 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:24,767 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 72 statements into 1 equivalence classes.
[2025-03-09 07:36:24,770 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-09 07:36:24,770 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:24,770 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:24,777 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:24,777 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:24,777 INFO  L85        PathProgramCache]: Analyzing trace with hash 271022178, now seen corresponding path program 2 times
[2025-03-09 07:36:24,777 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:24,777 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788171135]
[2025-03-09 07:36:24,778 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-03-09 07:36:24,778 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:24,780 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 19 statements into 1 equivalence classes.
[2025-03-09 07:36:24,781 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 19 of 19 statements.
[2025-03-09 07:36:24,781 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-09 07:36:24,781 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:24,781 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:24,782 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes.
[2025-03-09 07:36:24,783 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements.
[2025-03-09 07:36:24,783 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:24,783 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:24,784 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:24,785 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:24,785 INFO  L85        PathProgramCache]: Analyzing trace with hash -2001806475, now seen corresponding path program 1 times
[2025-03-09 07:36:24,785 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:24,785 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138728292]
[2025-03-09 07:36:24,785 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:24,785 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:24,791 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 91 statements into 1 equivalence classes.
[2025-03-09 07:36:24,794 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 91 of 91 statements.
[2025-03-09 07:36:24,794 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:24,794 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:24,817 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:24,817 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:24,817 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1138728292]
[2025-03-09 07:36:24,817 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1138728292] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:24,817 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:24,818 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-03-09 07:36:24,818 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [746924023]
[2025-03-09 07:36:24,818 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:24,888 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:24,888 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:24,889 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:24,889 INFO  L87              Difference]: Start difference. First operand 68276 states and 93676 transitions. cyclomatic complexity: 25422 Second operand  has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:25,316 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:25,317 INFO  L93              Difference]: Finished difference Result 119683 states and 163727 transitions.
[2025-03-09 07:36:25,317 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 119683 states and 163727 transitions.
[2025-03-09 07:36:25,765 INFO  L131   ngComponentsAnalysis]: Automaton has 22 accepting balls. 115514
[2025-03-09 07:36:26,220 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 119683 states to 119683 states and 163727 transitions.
[2025-03-09 07:36:26,221 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 119683
[2025-03-09 07:36:26,275 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 119683
[2025-03-09 07:36:26,275 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 119683 states and 163727 transitions.
[2025-03-09 07:36:26,326 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:26,326 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 119683 states and 163727 transitions.
[2025-03-09 07:36:26,374 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 119683 states and 163727 transitions.
[2025-03-09 07:36:27,262 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 119683 to 116111.
[2025-03-09 07:36:27,357 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 116111 states, 116111 states have (on average 1.372850117559921) internal successors, (159403), 116110 states have internal predecessors, (159403), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:27,575 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 116111 states to 116111 states and 159403 transitions.
[2025-03-09 07:36:27,575 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 116111 states and 159403 transitions.
[2025-03-09 07:36:27,575 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:27,576 INFO  L432   stractBuchiCegarLoop]: Abstraction has 116111 states and 159403 transitions.
[2025-03-09 07:36:27,576 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 23 ============
[2025-03-09 07:36:27,576 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 116111 states and 159403 transitions.
[2025-03-09 07:36:28,218 INFO  L131   ngComponentsAnalysis]: Automaton has 22 accepting balls. 111942
[2025-03-09 07:36:28,219 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:28,219 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:28,219 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:28,219 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:28,219 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" 
[2025-03-09 07:36:28,220 INFO  L754   eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_5~0#1);" "havoc eval_~tmp_ndt_5~0#1;" "assume !(0 == ~t5_st~0);" 
[2025-03-09 07:36:28,220 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:28,221 INFO  L85        PathProgramCache]: Analyzing trace with hash -1226709042, now seen corresponding path program 4 times
[2025-03-09 07:36:28,221 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:28,221 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735336991]
[2025-03-09 07:36:28,221 INFO  L95    rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST
[2025-03-09 07:36:28,221 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:28,226 INFO  L108    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 72 statements into 2 equivalence classes.
[2025-03-09 07:36:28,230 INFO  L111    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-09 07:36:28,230 INFO  L114    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s)
[2025-03-09 07:36:28,230 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:28,230 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:28,233 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 72 statements into 1 equivalence classes.
[2025-03-09 07:36:28,235 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-09 07:36:28,235 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:28,235 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:28,241 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:28,242 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:28,242 INFO  L85        PathProgramCache]: Analyzing trace with hash -1540625412, now seen corresponding path program 1 times
[2025-03-09 07:36:28,242 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:28,242 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70630485]
[2025-03-09 07:36:28,243 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:28,243 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:28,245 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes.
[2025-03-09 07:36:28,246 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements.
[2025-03-09 07:36:28,246 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:28,246 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:28,246 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:28,246 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes.
[2025-03-09 07:36:28,247 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements.
[2025-03-09 07:36:28,247 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:28,247 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:28,249 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:28,250 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:28,250 INFO  L85        PathProgramCache]: Analyzing trace with hash 409392719, now seen corresponding path program 1 times
[2025-03-09 07:36:28,250 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:28,250 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [526064217]
[2025-03-09 07:36:28,250 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:28,250 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:28,256 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 93 statements into 1 equivalence classes.
[2025-03-09 07:36:28,258 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 93 of 93 statements.
[2025-03-09 07:36:28,259 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:28,259 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-03-09 07:36:28,278 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-03-09 07:36:28,279 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-03-09 07:36:28,279 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [526064217]
[2025-03-09 07:36:28,279 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [526064217] provided 1 perfect and 0 imperfect interpolant sequences
[2025-03-09 07:36:28,279 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-03-09 07:36:28,279 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-03-09 07:36:28,279 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141879239]
[2025-03-09 07:36:28,279 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-03-09 07:36:28,348 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-03-09 07:36:28,348 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-03-09 07:36:28,348 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-03-09 07:36:28,348 INFO  L87              Difference]: Start difference. First operand 116111 states and 159403 transitions. cyclomatic complexity: 43314 Second operand  has 3 states, 2 states have (on average 46.5) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:28,665 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-03-09 07:36:28,665 INFO  L93              Difference]: Finished difference Result 136359 states and 186323 transitions.
[2025-03-09 07:36:28,665 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 136359 states and 186323 transitions.
[2025-03-09 07:36:29,506 INFO  L131   ngComponentsAnalysis]: Automaton has 23 accepting balls. 128634
[2025-03-09 07:36:29,823 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 136359 states to 136359 states and 186323 transitions.
[2025-03-09 07:36:29,824 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 136359
[2025-03-09 07:36:29,917 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 136359
[2025-03-09 07:36:29,917 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 136359 states and 186323 transitions.
[2025-03-09 07:36:29,986 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-03-09 07:36:29,986 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 136359 states and 186323 transitions.
[2025-03-09 07:36:30,071 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 136359 states and 186323 transitions.
[2025-03-09 07:36:31,293 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 136359 to 136359.
[2025-03-09 07:36:31,406 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 136359 states, 136359 states have (on average 1.3664151247809093) internal successors, (186323), 136358 states have internal predecessors, (186323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-03-09 07:36:31,686 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 136359 states to 136359 states and 186323 transitions.
[2025-03-09 07:36:31,686 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 136359 states and 186323 transitions.
[2025-03-09 07:36:31,687 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-03-09 07:36:31,687 INFO  L432   stractBuchiCegarLoop]: Abstraction has 136359 states and 186323 transitions.
[2025-03-09 07:36:31,687 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 24 ============
[2025-03-09 07:36:31,687 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 136359 states and 186323 transitions.
[2025-03-09 07:36:32,154 INFO  L131   ngComponentsAnalysis]: Automaton has 23 accepting balls. 128634
[2025-03-09 07:36:32,155 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-03-09 07:36:32,155 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-03-09 07:36:32,155 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:32,155 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-03-09 07:36:32,155 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" 
[2025-03-09 07:36:32,156 INFO  L754   eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_5~0#1);" "havoc eval_~tmp_ndt_5~0#1;" "assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp_ndt_6~0#1);" "havoc eval_~tmp_ndt_6~0#1;" 
[2025-03-09 07:36:32,156 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:32,156 INFO  L85        PathProgramCache]: Analyzing trace with hash -1226709042, now seen corresponding path program 5 times
[2025-03-09 07:36:32,156 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:32,156 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271963170]
[2025-03-09 07:36:32,156 INFO  L95    rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1
[2025-03-09 07:36:32,156 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:32,162 INFO  L108    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 72 statements into 1 equivalence classes.
[2025-03-09 07:36:32,164 INFO  L111    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-09 07:36:32,164 INFO  L114    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-03-09 07:36:32,164 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:32,165 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:32,166 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 72 statements into 1 equivalence classes.
[2025-03-09 07:36:32,168 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-09 07:36:32,168 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:32,168 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:32,174 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:32,174 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:32,174 INFO  L85        PathProgramCache]: Analyzing trace with hash 1222705001, now seen corresponding path program 1 times
[2025-03-09 07:36:32,175 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:32,175 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019666498]
[2025-03-09 07:36:32,175 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:32,175 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:32,177 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes.
[2025-03-09 07:36:32,178 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements.
[2025-03-09 07:36:32,178 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:32,178 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:32,178 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:32,179 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes.
[2025-03-09 07:36:32,179 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements.
[2025-03-09 07:36:32,180 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:32,180 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:32,181 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:32,181 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-03-09 07:36:32,181 INFO  L85        PathProgramCache]: Analyzing trace with hash -1710579460, now seen corresponding path program 1 times
[2025-03-09 07:36:32,181 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-03-09 07:36:32,181 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442707552]
[2025-03-09 07:36:32,182 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-03-09 07:36:32,182 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-03-09 07:36:32,187 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 95 statements into 1 equivalence classes.
[2025-03-09 07:36:32,189 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 95 of 95 statements.
[2025-03-09 07:36:32,190 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:32,190 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:32,190 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:32,192 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 95 statements into 1 equivalence classes.
[2025-03-09 07:36:32,194 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 95 of 95 statements.
[2025-03-09 07:36:32,194 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:32,194 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:32,202 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-03-09 07:36:33,534 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 72 statements into 1 equivalence classes.
[2025-03-09 07:36:33,540 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-09 07:36:33,541 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:33,541 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:33,541 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-03-09 07:36:33,551 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 72 statements into 1 equivalence classes.
[2025-03-09 07:36:33,557 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 72 of 72 statements.
[2025-03-09 07:36:33,557 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-03-09 07:36:33,557 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-03-09 07:36:33,711 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 09.03 07:36:33 BoogieIcfgContainer
[2025-03-09 07:36:33,711 INFO  L131        PluginConnector]: ------------------------ END BuchiAutomizer----------------------------
[2025-03-09 07:36:33,712 INFO  L112        PluginConnector]: ------------------------Witness Printer----------------------------
[2025-03-09 07:36:33,712 INFO  L270        PluginConnector]: Initializing Witness Printer...
[2025-03-09 07:36:33,712 INFO  L274        PluginConnector]: Witness Printer initialized
[2025-03-09 07:36:33,713 INFO  L184        PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:36:11" (3/4) ...
[2025-03-09 07:36:33,714 INFO  L143         WitnessPrinter]: Generating witness for non-termination counterexample
[2025-03-09 07:36:33,795 INFO  L149         WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml
[2025-03-09 07:36:33,795 INFO  L131        PluginConnector]: ------------------------ END Witness Printer----------------------------
[2025-03-09 07:36:33,795 INFO  L158              Benchmark]: Toolchain (without parser) took 24035.37ms. Allocated memory was 142.6MB in the beginning and 9.8GB in the end (delta: 9.7GB). Free memory was 105.8MB in the beginning and 8.1GB in the end (delta: -8.0GB). Peak memory consumption was 1.7GB. Max. memory is 16.1GB.
[2025-03-09 07:36:33,796 INFO  L158              Benchmark]: CDTParser took 0.21ms. Allocated memory is still 201.3MB. Free memory is still 115.7MB. There was no memory consumed. Max. memory is 16.1GB.
[2025-03-09 07:36:33,796 INFO  L158              Benchmark]: CACSL2BoogieTranslator took 274.37ms. Allocated memory is still 142.6MB. Free memory was 105.8MB in the beginning and 90.4MB in the end (delta: 15.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
[2025-03-09 07:36:33,796 INFO  L158              Benchmark]: Boogie Procedure Inliner took 46.03ms. Allocated memory is still 142.6MB. Free memory was 90.4MB in the beginning and 85.6MB in the end (delta: 4.8MB). There was no memory consumed. Max. memory is 16.1GB.
[2025-03-09 07:36:33,796 INFO  L158              Benchmark]: Boogie Preprocessor took 61.40ms. Allocated memory is still 142.6MB. Free memory was 85.6MB in the beginning and 82.0MB in the end (delta: 3.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
[2025-03-09 07:36:33,796 INFO  L158              Benchmark]: IcfgBuilder took 992.95ms. Allocated memory is still 142.6MB. Free memory was 82.0MB in the beginning and 83.4MB in the end (delta: -1.4MB). Peak memory consumption was 57.2MB. Max. memory is 16.1GB.
[2025-03-09 07:36:33,796 INFO  L158              Benchmark]: BuchiAutomizer took 22573.18ms. Allocated memory was 142.6MB in the beginning and 9.8GB in the end (delta: 9.7GB). Free memory was 83.4MB in the beginning and 8.1GB in the end (delta: -8.0GB). Peak memory consumption was 1.6GB. Max. memory is 16.1GB.
[2025-03-09 07:36:33,796 INFO  L158              Benchmark]: Witness Printer took 83.23ms. Allocated memory is still 9.8GB. Free memory was 8.1GB in the beginning and 8.1GB in the end (delta: 12.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
[2025-03-09 07:36:33,798 INFO  L338   ainManager$Toolchain]: #######################  End [Toolchain 1] #######################
 --- Results ---
 * Results from de.uni_freiburg.informatik.ultimate.core:
  - StatisticsResult: Toolchain Benchmarks
    Benchmark results are:
 * CDTParser took 0.21ms. Allocated memory is still 201.3MB. Free memory is still 115.7MB. There was no memory consumed. Max. memory is 16.1GB.
 * CACSL2BoogieTranslator took 274.37ms. Allocated memory is still 142.6MB. Free memory was 105.8MB in the beginning and 90.4MB in the end (delta: 15.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
 * Boogie Procedure Inliner took 46.03ms. Allocated memory is still 142.6MB. Free memory was 90.4MB in the beginning and 85.6MB in the end (delta: 4.8MB). There was no memory consumed. Max. memory is 16.1GB.
 * Boogie Preprocessor took 61.40ms. Allocated memory is still 142.6MB. Free memory was 85.6MB in the beginning and 82.0MB in the end (delta: 3.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
 * IcfgBuilder took 992.95ms. Allocated memory is still 142.6MB. Free memory was 82.0MB in the beginning and 83.4MB in the end (delta: -1.4MB). Peak memory consumption was 57.2MB. Max. memory is 16.1GB.
 * BuchiAutomizer took 22573.18ms. Allocated memory was 142.6MB in the beginning and 9.8GB in the end (delta: 9.7GB). Free memory was 83.4MB in the beginning and 8.1GB in the end (delta: -8.0GB). Peak memory consumption was 1.6GB. Max. memory is 16.1GB.
 * Witness Printer took 83.23ms. Allocated memory is still 9.8GB. Free memory was 8.1GB in the beginning and 8.1GB in the end (delta: 12.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction:
  - StatisticsResult: Constructed decomposition of program
    Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 136359 locations.
  - StatisticsResult: Timing statistics
    BüchiAutomizer plugin needed 22.4s and 24 iterations.  TraceHistogramMax:3. Analysis of lassos took 3.9s. Construction of modules took 0.5s. Büchi inclusion checks took 15.6s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 7.9s AutomataMinimizationTime, 23 MinimizatonAttempts, 15427 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 4.8s Buchi closure took 0.4s. Biggest automaton had -1 states and ocurred in iteration -1.	Nontrivial modules had stage [0, 0, 0, 0, 0].	InterpolantCoveringCapabilityFinite: 0/0	InterpolantCoveringCapabilityBuchi: 0/0	HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 14425 SdHoareTripleChecker+Valid, 0.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 14425 mSDsluCounter, 30674 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 13283 mSDsCounter, 245 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 547 IncrementalHoareTripleChecker+Invalid, 792 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 245 mSolverCounterUnsat, 17391 mSDtfsCounter, 547 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown	LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc4 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0	LassoNonterminationAnalysisSatUnbounded: 0	LassoNonterminationAnalysisUnsat: 0	LassoNonterminationAnalysisUnknown: 0	LassoNonterminationAnalysisTime: 0.0s	InitialAbstractionConstructionTime: 0.0s
  - TerminationAnalysisResult: Nontermination possible
    Buchi Automizer proved that your program is nonterminating for some inputs
  - LassoShapedNonTerminationArgument [Line: 484]: Nontermination argument in form of an infinite program execution.
    Nontermination argument in form of an infinite program execution.
Stem:
[L25]               int m_pc  =    0;
[L26]               int t1_pc  =    0;
[L27]               int t2_pc  =    0;
[L28]               int t3_pc  =    0;
[L29]               int t4_pc  =    0;
[L30]               int t5_pc  =    0;
[L31]               int m_st  ;
[L32]               int t1_st  ;
[L33]               int t2_st  ;
[L34]               int t3_st  ;
[L35]               int t4_st  ;
[L36]               int t5_st  ;
[L37]               int m_i  ;
[L38]               int t1_i  ;
[L39]               int t2_i  ;
[L40]               int t3_i  ;
[L41]               int t4_i  ;
[L42]               int t5_i  ;
[L43]               int M_E  =    2;
[L44]               int T1_E  =    2;
[L45]               int T2_E  =    2;
[L46]               int T3_E  =    2;
[L47]               int T4_E  =    2;
[L48]               int T5_E  =    2;
[L49]               int E_1  =    2;
[L50]               int E_2  =    2;
[L51]               int E_3  =    2;
[L52]               int E_4  =    2;
[L53]               int E_5  =    2;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0]
[L945]              int __retres1 ;
[L949]  CALL        init_model()
[L856]              m_i = 1
[L857]              t1_i = 1
[L858]              t2_i = 1
[L859]              t3_i = 1
[L860]              t4_i = 1
[L861]              t5_i = 1
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L949]  RET         init_model()
[L950]  CALL        start_simulation()
[L886]              int kernel_st ;
[L887]              int tmp ;
[L888]              int tmp___0 ;
[L892]              kernel_st = 0
[L893]  FCALL       update_channels()
[L894]  CALL        init_threads()
[L401]  COND TRUE   m_i == 1
[L402]              m_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L406]  COND TRUE   t1_i == 1
[L407]              t1_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L411]  COND TRUE   t2_i == 1
[L412]              t2_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L416]  COND TRUE   t3_i == 1
[L417]              t3_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L421]  COND TRUE   t4_i == 1
[L422]              t4_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L426]  COND TRUE   t5_i == 1
[L427]              t5_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L894]  RET         init_threads()
[L895]  CALL        fire_delta_events()
[L586]  COND FALSE  !(M_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L591]  COND FALSE  !(T1_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L596]  COND FALSE  !(T2_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L601]  COND FALSE  !(T3_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L606]  COND FALSE  !(T4_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L611]  COND FALSE  !(T5_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L616]  COND FALSE  !(E_1 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L621]  COND FALSE  !(E_2 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L626]  COND FALSE  !(E_3 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L631]  COND FALSE  !(E_4 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L636]  COND FALSE  !(E_5 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L895]  RET         fire_delta_events()
[L896]  CALL        activate_threads()
[L709]              int tmp ;
[L710]              int tmp___0 ;
[L711]              int tmp___1 ;
[L712]              int tmp___2 ;
[L713]              int tmp___3 ;
[L714]              int tmp___4 ;
[L718]  CALL, EXPR  is_master_triggered()
[L276]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L279]  COND FALSE  !(m_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L289]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L291]              return (__retres1);
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L718]  RET, EXPR   is_master_triggered()
[L718]              tmp = is_master_triggered()
[L720]  COND FALSE  !(\read(tmp))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L726]  CALL, EXPR  is_transmit1_triggered()
[L295]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L298]  COND FALSE  !(t1_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L308]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L310]              return (__retres1);
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L726]  RET, EXPR   is_transmit1_triggered()
[L726]              tmp___0 = is_transmit1_triggered()
[L728]  COND FALSE  !(\read(tmp___0))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L734]  CALL, EXPR  is_transmit2_triggered()
[L314]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L317]  COND FALSE  !(t2_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L327]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L329]              return (__retres1);
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L734]  RET, EXPR   is_transmit2_triggered()
[L734]              tmp___1 = is_transmit2_triggered()
[L736]  COND FALSE  !(\read(tmp___1))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L742]  CALL, EXPR  is_transmit3_triggered()
[L333]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L336]  COND FALSE  !(t3_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L346]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L348]              return (__retres1);
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L742]  RET, EXPR   is_transmit3_triggered()
[L742]              tmp___2 = is_transmit3_triggered()
[L744]  COND FALSE  !(\read(tmp___2))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L750]  CALL, EXPR  is_transmit4_triggered()
[L352]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L355]  COND FALSE  !(t4_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L365]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L367]              return (__retres1);
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L750]  RET, EXPR   is_transmit4_triggered()
[L750]              tmp___3 = is_transmit4_triggered()
[L752]  COND FALSE  !(\read(tmp___3))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L758]  CALL, EXPR  is_transmit5_triggered()
[L371]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L374]  COND FALSE  !(t5_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L384]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L386]              return (__retres1);
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L758]  RET, EXPR   is_transmit5_triggered()
[L758]              tmp___4 = is_transmit5_triggered()
[L760]  COND FALSE  !(\read(tmp___4))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L896]  RET         activate_threads()
[L897]  CALL        reset_delta_events()
[L649]  COND FALSE  !(M_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L654]  COND FALSE  !(T1_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L659]  COND FALSE  !(T2_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L664]  COND FALSE  !(T3_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L669]  COND FALSE  !(T4_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L674]  COND FALSE  !(T5_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L679]  COND FALSE  !(E_1 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L684]  COND FALSE  !(E_2 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L689]  COND FALSE  !(E_3 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L694]  COND FALSE  !(E_4 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L699]  COND FALSE  !(E_5 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L897]  RET         reset_delta_events()
[L903]              kernel_st = 1
[L904]  CALL        eval()
[L477]              int tmp ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
Loop:
[L484]  CALL, EXPR  exists_runnable_thread()
[L436]              int __retres1 ;
[L439]  COND TRUE   m_st == 0
[L440]              __retres1 = 1
[L472]              return (__retres1);
[L484]  RET, EXPR   exists_runnable_thread()
[L484]              tmp = exists_runnable_thread()
[L486]  COND TRUE   \read(tmp)
[L491]  COND TRUE   m_st == 0
[L492]              int tmp_ndt_1;
[L493]              tmp_ndt_1 = __VERIFIER_nondet_int()
[L494]  COND FALSE  !(\read(tmp_ndt_1))
[L505]  COND TRUE   t1_st == 0
[L506]              int tmp_ndt_2;
[L507]              tmp_ndt_2 = __VERIFIER_nondet_int()
[L508]  COND FALSE  !(\read(tmp_ndt_2))
[L519]  COND TRUE   t2_st == 0
[L520]              int tmp_ndt_3;
[L521]              tmp_ndt_3 = __VERIFIER_nondet_int()
[L522]  COND FALSE  !(\read(tmp_ndt_3))
[L533]  COND TRUE   t3_st == 0
[L534]              int tmp_ndt_4;
[L535]              tmp_ndt_4 = __VERIFIER_nondet_int()
[L536]  COND FALSE  !(\read(tmp_ndt_4))
[L547]  COND TRUE   t4_st == 0
[L548]              int tmp_ndt_5;
[L549]              tmp_ndt_5 = __VERIFIER_nondet_int()
[L550]  COND FALSE  !(\read(tmp_ndt_5))
[L561]  COND TRUE   t5_st == 0
[L562]              int tmp_ndt_6;
[L563]              tmp_ndt_6 = __VERIFIER_nondet_int()
[L564]  COND FALSE  !(\read(tmp_ndt_6))
End of lasso representation.
  - StatisticsResult: NonterminationArgumentStatistics
    Fixpoint
  - NonterminatingLassoResult [Line: 484]: Nonterminating execution
    Found a nonterminating execution for the following lasso shaped sequence of statements.
Stem:
[L25]               int m_pc  =    0;
[L26]               int t1_pc  =    0;
[L27]               int t2_pc  =    0;
[L28]               int t3_pc  =    0;
[L29]               int t4_pc  =    0;
[L30]               int t5_pc  =    0;
[L31]               int m_st  ;
[L32]               int t1_st  ;
[L33]               int t2_st  ;
[L34]               int t3_st  ;
[L35]               int t4_st  ;
[L36]               int t5_st  ;
[L37]               int m_i  ;
[L38]               int t1_i  ;
[L39]               int t2_i  ;
[L40]               int t3_i  ;
[L41]               int t4_i  ;
[L42]               int t5_i  ;
[L43]               int M_E  =    2;
[L44]               int T1_E  =    2;
[L45]               int T2_E  =    2;
[L46]               int T3_E  =    2;
[L47]               int T4_E  =    2;
[L48]               int T5_E  =    2;
[L49]               int E_1  =    2;
[L50]               int E_2  =    2;
[L51]               int E_3  =    2;
[L52]               int E_4  =    2;
[L53]               int E_5  =    2;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0]
[L945]              int __retres1 ;
[L949]  CALL        init_model()
[L856]              m_i = 1
[L857]              t1_i = 1
[L858]              t2_i = 1
[L859]              t3_i = 1
[L860]              t4_i = 1
[L861]              t5_i = 1
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L949]  RET         init_model()
[L950]  CALL        start_simulation()
[L886]              int kernel_st ;
[L887]              int tmp ;
[L888]              int tmp___0 ;
[L892]              kernel_st = 0
[L893]  FCALL       update_channels()
[L894]  CALL        init_threads()
[L401]  COND TRUE   m_i == 1
[L402]              m_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L406]  COND TRUE   t1_i == 1
[L407]              t1_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L411]  COND TRUE   t2_i == 1
[L412]              t2_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L416]  COND TRUE   t3_i == 1
[L417]              t3_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L421]  COND TRUE   t4_i == 1
[L422]              t4_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L426]  COND TRUE   t5_i == 1
[L427]              t5_st = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L894]  RET         init_threads()
[L895]  CALL        fire_delta_events()
[L586]  COND FALSE  !(M_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L591]  COND FALSE  !(T1_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L596]  COND FALSE  !(T2_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L601]  COND FALSE  !(T3_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L606]  COND FALSE  !(T4_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L611]  COND FALSE  !(T5_E == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L616]  COND FALSE  !(E_1 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L621]  COND FALSE  !(E_2 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L626]  COND FALSE  !(E_3 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L631]  COND FALSE  !(E_4 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L636]  COND FALSE  !(E_5 == 0)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L895]  RET         fire_delta_events()
[L896]  CALL        activate_threads()
[L709]              int tmp ;
[L710]              int tmp___0 ;
[L711]              int tmp___1 ;
[L712]              int tmp___2 ;
[L713]              int tmp___3 ;
[L714]              int tmp___4 ;
[L718]  CALL, EXPR  is_master_triggered()
[L276]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L279]  COND FALSE  !(m_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L289]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L291]              return (__retres1);
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L718]  RET, EXPR   is_master_triggered()
[L718]              tmp = is_master_triggered()
[L720]  COND FALSE  !(\read(tmp))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L726]  CALL, EXPR  is_transmit1_triggered()
[L295]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L298]  COND FALSE  !(t1_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L308]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L310]              return (__retres1);
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L726]  RET, EXPR   is_transmit1_triggered()
[L726]              tmp___0 = is_transmit1_triggered()
[L728]  COND FALSE  !(\read(tmp___0))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L734]  CALL, EXPR  is_transmit2_triggered()
[L314]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L317]  COND FALSE  !(t2_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L327]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L329]              return (__retres1);
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L734]  RET, EXPR   is_transmit2_triggered()
[L734]              tmp___1 = is_transmit2_triggered()
[L736]  COND FALSE  !(\read(tmp___1))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L742]  CALL, EXPR  is_transmit3_triggered()
[L333]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L336]  COND FALSE  !(t3_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L346]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L348]              return (__retres1);
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L742]  RET, EXPR   is_transmit3_triggered()
[L742]              tmp___2 = is_transmit3_triggered()
[L744]  COND FALSE  !(\read(tmp___2))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L750]  CALL, EXPR  is_transmit4_triggered()
[L352]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L355]  COND FALSE  !(t4_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L365]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L367]              return (__retres1);
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L750]  RET, EXPR   is_transmit4_triggered()
[L750]              tmp___3 = is_transmit4_triggered()
[L752]  COND FALSE  !(\read(tmp___3))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L758]  CALL, EXPR  is_transmit5_triggered()
[L371]              int __retres1 ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L374]  COND FALSE  !(t5_pc == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L384]              __retres1 = 0
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L386]              return (__retres1);
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L758]  RET, EXPR   is_transmit5_triggered()
[L758]              tmp___4 = is_transmit5_triggered()
[L760]  COND FALSE  !(\read(tmp___4))
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L896]  RET         activate_threads()
[L897]  CALL        reset_delta_events()
[L649]  COND FALSE  !(M_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L654]  COND FALSE  !(T1_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L659]  COND FALSE  !(T2_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L664]  COND FALSE  !(T3_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L669]  COND FALSE  !(T4_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L674]  COND FALSE  !(T5_E == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L679]  COND FALSE  !(E_1 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L684]  COND FALSE  !(E_2 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L689]  COND FALSE  !(E_3 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L694]  COND FALSE  !(E_4 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L699]  COND FALSE  !(E_5 == 1)
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L897]  RET         reset_delta_events()
[L903]              kernel_st = 1
[L904]  CALL        eval()
[L477]              int tmp ;
        VAL         [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
Loop:
[L484]  CALL, EXPR  exists_runnable_thread()
[L436]              int __retres1 ;
[L439]  COND TRUE   m_st == 0
[L440]              __retres1 = 1
[L472]              return (__retres1);
[L484]  RET, EXPR   exists_runnable_thread()
[L484]              tmp = exists_runnable_thread()
[L486]  COND TRUE   \read(tmp)
[L491]  COND TRUE   m_st == 0
[L492]              int tmp_ndt_1;
[L493]              tmp_ndt_1 = __VERIFIER_nondet_int()
[L494]  COND FALSE  !(\read(tmp_ndt_1))
[L505]  COND TRUE   t1_st == 0
[L506]              int tmp_ndt_2;
[L507]              tmp_ndt_2 = __VERIFIER_nondet_int()
[L508]  COND FALSE  !(\read(tmp_ndt_2))
[L519]  COND TRUE   t2_st == 0
[L520]              int tmp_ndt_3;
[L521]              tmp_ndt_3 = __VERIFIER_nondet_int()
[L522]  COND FALSE  !(\read(tmp_ndt_3))
[L533]  COND TRUE   t3_st == 0
[L534]              int tmp_ndt_4;
[L535]              tmp_ndt_4 = __VERIFIER_nondet_int()
[L536]  COND FALSE  !(\read(tmp_ndt_4))
[L547]  COND TRUE   t4_st == 0
[L548]              int tmp_ndt_5;
[L549]              tmp_ndt_5 = __VERIFIER_nondet_int()
[L550]  COND FALSE  !(\read(tmp_ndt_5))
[L561]  COND TRUE   t5_st == 0
[L562]              int tmp_ndt_6;
[L563]              tmp_ndt_6 = __VERIFIER_nondet_int()
[L564]  COND FALSE  !(\read(tmp_ndt_6))
End of lasso representation.
RESULT: Ultimate proved your program to be incorrect!
[2025-03-09 07:36:33,819 INFO  L552       MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0
Received shutdown request...
--- End real Ultimate output ---

Execution finished normally
Writing output log to file Ultimate.log
Writing human readable error path to file UltimateCounterExample.errorpath
Result:
FALSE(TERM)