./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test1-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e2fb8bed Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test1-2.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bfb70cce6cd508003f6161c30aa2ac99ac8ddeb6209ddd86b65ca0c623c2fb1c --- Real Ultimate output --- This is Ultimate 0.3.0-?-e2fb8be-m [2025-03-09 07:57:26,992 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-09 07:57:27,034 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-09 07:57:27,038 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-09 07:57:27,038 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-09 07:57:27,039 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-09 07:57:27,056 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-09 07:57:27,057 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-09 07:57:27,057 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-09 07:57:27,058 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-09 07:57:27,058 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-09 07:57:27,059 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-09 07:57:27,059 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-09 07:57:27,059 INFO L153 SettingsManager]: * Use SBE=true [2025-03-09 07:57:27,059 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-09 07:57:27,059 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-09 07:57:27,059 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-09 07:57:27,059 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-09 07:57:27,059 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-09 07:57:27,060 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-09 07:57:27,060 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-09 07:57:27,060 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-09 07:57:27,060 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-09 07:57:27,060 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-09 07:57:27,060 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-09 07:57:27,060 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-09 07:57:27,060 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-09 07:57:27,060 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-09 07:57:27,060 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-09 07:57:27,060 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-09 07:57:27,061 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-09 07:57:27,061 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-09 07:57:27,061 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-09 07:57:27,061 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-09 07:57:27,061 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-09 07:57:27,061 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-09 07:57:27,061 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-09 07:57:27,061 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-09 07:57:27,061 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-09 07:57:27,061 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-09 07:57:27,062 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bfb70cce6cd508003f6161c30aa2ac99ac8ddeb6209ddd86b65ca0c623c2fb1c [2025-03-09 07:57:27,264 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-09 07:57:27,268 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-09 07:57:27,272 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-09 07:57:27,273 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-09 07:57:27,273 INFO L274 PluginConnector]: CDTParser initialized [2025-03-09 07:57:27,274 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test1-2.i [2025-03-09 07:57:28,392 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/202b1ec55/bff20f42746b4dcda20512e79f8de450/FLAG7fa742e96 [2025-03-09 07:57:28,699 INFO L384 CDTParser]: Found 1 translation units. [2025-03-09 07:57:28,699 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/uthash-2.0.2/uthash_OAT_test1-2.i [2025-03-09 07:57:28,715 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/202b1ec55/bff20f42746b4dcda20512e79f8de450/FLAG7fa742e96 [2025-03-09 07:57:28,934 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/202b1ec55/bff20f42746b4dcda20512e79f8de450 [2025-03-09 07:57:28,936 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-09 07:57:28,937 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-09 07:57:28,938 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-09 07:57:28,938 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-09 07:57:28,940 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-09 07:57:28,941 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 07:57:28" (1/1) ... [2025-03-09 07:57:28,945 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@dfd54a9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:28, skipping insertion in model container [2025-03-09 07:57:28,945 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 07:57:28" (1/1) ... [2025-03-09 07:57:28,973 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-09 07:57:29,264 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 07:57:29,274 INFO L200 MainTranslator]: Completed pre-run [2025-03-09 07:57:29,347 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 07:57:29,371 INFO L204 MainTranslator]: Completed translation [2025-03-09 07:57:29,372 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29 WrapperNode [2025-03-09 07:57:29,372 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-09 07:57:29,373 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-09 07:57:29,373 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-09 07:57:29,373 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-09 07:57:29,376 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29" (1/1) ... [2025-03-09 07:57:29,390 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29" (1/1) ... [2025-03-09 07:57:29,423 INFO L138 Inliner]: procedures = 176, calls = 231, calls flagged for inlining = 14, calls inlined = 23, statements flattened = 1022 [2025-03-09 07:57:29,423 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-09 07:57:29,424 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-09 07:57:29,424 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-09 07:57:29,424 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-09 07:57:29,429 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29" (1/1) ... [2025-03-09 07:57:29,429 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29" (1/1) ... [2025-03-09 07:57:29,435 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29" (1/1) ... [2025-03-09 07:57:29,484 INFO L175 MemorySlicer]: Split 206 memory accesses to 2 slices as follows [2, 204]. 99 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0]. The 50 writes are split as follows [0, 50]. [2025-03-09 07:57:29,484 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29" (1/1) ... [2025-03-09 07:57:29,484 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29" (1/1) ... [2025-03-09 07:57:29,516 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29" (1/1) ... [2025-03-09 07:57:29,517 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29" (1/1) ... [2025-03-09 07:57:29,524 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29" (1/1) ... [2025-03-09 07:57:29,527 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29" (1/1) ... [2025-03-09 07:57:29,536 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-09 07:57:29,537 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-09 07:57:29,537 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-09 07:57:29,537 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-09 07:57:29,537 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29" (1/1) ... [2025-03-09 07:57:29,542 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 07:57:29,549 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 07:57:29,561 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 07:57:29,562 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#0 [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#1 [2025-03-09 07:57:29,576 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#0 [2025-03-09 07:57:29,576 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#1 [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#0 [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#1 [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#0 [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#1 [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-03-09 07:57:29,576 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-09 07:57:29,576 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-09 07:57:29,720 INFO L256 CfgBuilder]: Building ICFG [2025-03-09 07:57:29,721 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-09 07:57:30,626 INFO L? ?]: Removed 279 outVars from TransFormulas that were not future-live. [2025-03-09 07:57:30,627 INFO L307 CfgBuilder]: Performing block encoding [2025-03-09 07:57:30,671 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-09 07:57:30,671 INFO L336 CfgBuilder]: Removed 1 assume(true) statements. [2025-03-09 07:57:30,671 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:57:30 BoogieIcfgContainer [2025-03-09 07:57:30,671 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-09 07:57:30,672 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-09 07:57:30,672 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-09 07:57:30,679 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-09 07:57:30,679 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:57:30,679 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.03 07:57:28" (1/3) ... [2025-03-09 07:57:30,680 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@38af5aa2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 07:57:30, skipping insertion in model container [2025-03-09 07:57:30,680 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:57:30,680 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 07:57:29" (2/3) ... [2025-03-09 07:57:30,681 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@38af5aa2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 07:57:30, skipping insertion in model container [2025-03-09 07:57:30,681 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 07:57:30,681 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 07:57:30" (3/3) ... [2025-03-09 07:57:30,681 INFO L363 chiAutomizerObserver]: Analyzing ICFG uthash_OAT_test1-2.i [2025-03-09 07:57:30,717 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-09 07:57:30,718 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-09 07:57:30,718 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-09 07:57:30,718 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-09 07:57:30,718 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-09 07:57:30,718 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-09 07:57:30,718 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-09 07:57:30,718 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-09 07:57:30,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 287 states, 282 states have (on average 1.599290780141844) internal successors, (451), 282 states have internal predecessors, (451), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:30,750 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 276 [2025-03-09 07:57:30,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:30,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:30,754 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:30,754 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-03-09 07:57:30,755 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-09 07:57:30,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 287 states, 282 states have (on average 1.599290780141844) internal successors, (451), 282 states have internal predecessors, (451), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:30,765 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 276 [2025-03-09 07:57:30,765 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:30,765 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:30,765 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:30,765 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-03-09 07:57:30,772 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:30,772 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false;" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume !true;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:30,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:30,778 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 1 times [2025-03-09 07:57:30,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:30,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518032335] [2025-03-09 07:57:30,782 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:30,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:30,832 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:30,836 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:30,836 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:30,836 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:30,837 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:30,842 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:30,848 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:30,848 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:30,848 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:30,864 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:30,866 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:30,866 INFO L85 PathProgramCache]: Analyzing trace with hash 514307478, now seen corresponding path program 1 times [2025-03-09 07:57:30,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:30,867 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726743772] [2025-03-09 07:57:30,867 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:30,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:30,877 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-03-09 07:57:30,881 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-03-09 07:57:30,882 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:30,882 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:30,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:30,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:30,909 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1726743772] [2025-03-09 07:57:30,910 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1726743772] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:30,910 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:30,911 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 07:57:30,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1620638279] [2025-03-09 07:57:30,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:30,913 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:30,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:30,931 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-09 07:57:30,931 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-09 07:57:30,933 INFO L87 Difference]: Start difference. First operand has 287 states, 282 states have (on average 1.599290780141844) internal successors, (451), 282 states have internal predecessors, (451), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 2.5) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:30,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:30,989 INFO L93 Difference]: Finished difference Result 277 states and 388 transitions. [2025-03-09 07:57:30,990 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 277 states and 388 transitions. [2025-03-09 07:57:30,997 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 256 [2025-03-09 07:57:31,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 277 states to 264 states and 375 transitions. [2025-03-09 07:57:31,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 264 [2025-03-09 07:57:31,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 264 [2025-03-09 07:57:31,009 INFO L73 IsDeterministic]: Start isDeterministic. Operand 264 states and 375 transitions. [2025-03-09 07:57:31,011 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:31,011 INFO L218 hiAutomatonCegarLoop]: Abstraction has 264 states and 375 transitions. [2025-03-09 07:57:31,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 264 states and 375 transitions. [2025-03-09 07:57:31,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 264 to 264. [2025-03-09 07:57:31,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 264 states, 260 states have (on average 1.4192307692307693) internal successors, (369), 259 states have internal predecessors, (369), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:31,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 264 states to 264 states and 375 transitions. [2025-03-09 07:57:31,035 INFO L240 hiAutomatonCegarLoop]: Abstraction has 264 states and 375 transitions. [2025-03-09 07:57:31,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-09 07:57:31,038 INFO L432 stractBuchiCegarLoop]: Abstraction has 264 states and 375 transitions. [2025-03-09 07:57:31,038 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-09 07:57:31,038 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 264 states and 375 transitions. [2025-03-09 07:57:31,039 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 256 [2025-03-09 07:57:31,039 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:31,039 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:31,040 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:31,040 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:31,040 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:31,041 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem28#1 := read~int#1(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem28#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem29#1 := read~int#1(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem29#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem30#1 := read~int#1(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem30#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem31#1 := read~int#1(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem31#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem33#1 := read~int#1(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem33#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem34#1 := read~int#1(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + (if main_#t~mem34#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem34#1 % 256 % 4294967296 else main_#t~mem34#1 % 256 % 4294967296 - 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise39#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise40#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:31,042 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:31,042 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 2 times [2025-03-09 07:57:31,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:31,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [845038866] [2025-03-09 07:57:31,042 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:57:31,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:31,051 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:31,053 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:31,053 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:57:31,053 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:31,053 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:31,055 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:31,056 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:31,059 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:31,059 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:31,065 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:31,065 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:31,066 INFO L85 PathProgramCache]: Analyzing trace with hash -1251865757, now seen corresponding path program 1 times [2025-03-09 07:57:31,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:31,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442238444] [2025-03-09 07:57:31,066 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:31,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:31,096 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 73 statements into 1 equivalence classes. [2025-03-09 07:57:31,119 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 73 of 73 statements. [2025-03-09 07:57:31,123 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:31,124 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:31,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:31,428 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:31,428 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [442238444] [2025-03-09 07:57:31,428 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [442238444] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:31,428 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:31,428 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-09 07:57:31,428 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879047736] [2025-03-09 07:57:31,428 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:31,428 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:31,429 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:31,429 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-09 07:57:31,429 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-09 07:57:31,430 INFO L87 Difference]: Start difference. First operand 264 states and 375 transitions. cyclomatic complexity: 115 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 4 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:31,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:31,570 INFO L93 Difference]: Finished difference Result 267 states and 371 transitions. [2025-03-09 07:57:31,570 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 267 states and 371 transitions. [2025-03-09 07:57:31,573 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 259 [2025-03-09 07:57:31,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 267 states to 267 states and 371 transitions. [2025-03-09 07:57:31,577 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 267 [2025-03-09 07:57:31,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 267 [2025-03-09 07:57:31,578 INFO L73 IsDeterministic]: Start isDeterministic. Operand 267 states and 371 transitions. [2025-03-09 07:57:31,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:31,579 INFO L218 hiAutomatonCegarLoop]: Abstraction has 267 states and 371 transitions. [2025-03-09 07:57:31,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states and 371 transitions. [2025-03-09 07:57:31,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 264. [2025-03-09 07:57:31,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 264 states, 260 states have (on average 1.3923076923076922) internal successors, (362), 259 states have internal predecessors, (362), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:31,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 264 states to 264 states and 368 transitions. [2025-03-09 07:57:31,591 INFO L240 hiAutomatonCegarLoop]: Abstraction has 264 states and 368 transitions. [2025-03-09 07:57:31,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-09 07:57:31,592 INFO L432 stractBuchiCegarLoop]: Abstraction has 264 states and 368 transitions. [2025-03-09 07:57:31,592 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-09 07:57:31,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 264 states and 368 transitions. [2025-03-09 07:57:31,593 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 256 [2025-03-09 07:57:31,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:31,594 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:31,595 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:31,596 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:31,596 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:31,596 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise39#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise40#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:31,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:31,598 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 3 times [2025-03-09 07:57:31,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:31,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [201352965] [2025-03-09 07:57:31,598 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 07:57:31,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:31,606 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:31,607 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:31,607 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 07:57:31,607 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:31,607 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:31,609 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:31,611 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:31,611 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:31,611 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:31,615 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:31,618 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:31,619 INFO L85 PathProgramCache]: Analyzing trace with hash -607092183, now seen corresponding path program 1 times [2025-03-09 07:57:31,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:31,619 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000366965] [2025-03-09 07:57:31,619 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:31,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:31,650 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 73 statements into 1 equivalence classes. [2025-03-09 07:57:31,751 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 73 of 73 statements. [2025-03-09 07:57:31,752 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:31,752 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:32,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:32,175 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:32,176 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1000366965] [2025-03-09 07:57:32,176 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1000366965] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:32,176 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:32,176 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-09 07:57:32,176 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679877934] [2025-03-09 07:57:32,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:32,177 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:32,177 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:32,177 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-09 07:57:32,177 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-09 07:57:32,177 INFO L87 Difference]: Start difference. First operand 264 states and 368 transitions. cyclomatic complexity: 108 Second operand has 6 states, 6 states have (on average 12.166666666666666) internal successors, (73), 6 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:32,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:32,754 INFO L93 Difference]: Finished difference Result 298 states and 412 transitions. [2025-03-09 07:57:32,754 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 298 states and 412 transitions. [2025-03-09 07:57:32,756 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 290 [2025-03-09 07:57:32,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 298 states to 298 states and 412 transitions. [2025-03-09 07:57:32,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 298 [2025-03-09 07:57:32,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 298 [2025-03-09 07:57:32,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 298 states and 412 transitions. [2025-03-09 07:57:32,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:32,762 INFO L218 hiAutomatonCegarLoop]: Abstraction has 298 states and 412 transitions. [2025-03-09 07:57:32,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298 states and 412 transitions. [2025-03-09 07:57:32,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298 to 291. [2025-03-09 07:57:32,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 291 states, 287 states have (on average 1.3763066202090593) internal successors, (395), 286 states have internal predecessors, (395), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:32,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 401 transitions. [2025-03-09 07:57:32,773 INFO L240 hiAutomatonCegarLoop]: Abstraction has 291 states and 401 transitions. [2025-03-09 07:57:32,773 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-09 07:57:32,774 INFO L432 stractBuchiCegarLoop]: Abstraction has 291 states and 401 transitions. [2025-03-09 07:57:32,774 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-09 07:57:32,774 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 401 transitions. [2025-03-09 07:57:32,776 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 283 [2025-03-09 07:57:32,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:32,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:32,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:32,777 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:32,778 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:32,778 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise39#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise40#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:32,778 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:32,778 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 4 times [2025-03-09 07:57:32,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:32,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857353817] [2025-03-09 07:57:32,779 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 07:57:32,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:32,785 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-09 07:57:32,786 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:32,786 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 07:57:32,786 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:32,786 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:32,788 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:32,789 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:32,789 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:32,789 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:32,792 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:32,792 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:32,793 INFO L85 PathProgramCache]: Analyzing trace with hash 637862094, now seen corresponding path program 1 times [2025-03-09 07:57:32,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:32,793 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082320097] [2025-03-09 07:57:32,793 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:32,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:32,837 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes. [2025-03-09 07:57:32,881 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements. [2025-03-09 07:57:32,881 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:32,881 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:33,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:33,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:33,115 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1082320097] [2025-03-09 07:57:33,115 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1082320097] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:33,115 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:33,115 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-09 07:57:33,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832775602] [2025-03-09 07:57:33,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:33,115 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:33,117 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:33,117 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-09 07:57:33,117 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-09 07:57:33,117 INFO L87 Difference]: Start difference. First operand 291 states and 401 transitions. cyclomatic complexity: 114 Second operand has 7 states, 7 states have (on average 10.571428571428571) internal successors, (74), 7 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:33,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:33,613 INFO L93 Difference]: Finished difference Result 304 states and 420 transitions. [2025-03-09 07:57:33,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 304 states and 420 transitions. [2025-03-09 07:57:33,615 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 296 [2025-03-09 07:57:33,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 304 states to 304 states and 420 transitions. [2025-03-09 07:57:33,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 304 [2025-03-09 07:57:33,618 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 304 [2025-03-09 07:57:33,619 INFO L73 IsDeterministic]: Start isDeterministic. Operand 304 states and 420 transitions. [2025-03-09 07:57:33,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:33,620 INFO L218 hiAutomatonCegarLoop]: Abstraction has 304 states and 420 transitions. [2025-03-09 07:57:33,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304 states and 420 transitions. [2025-03-09 07:57:33,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304 to 301. [2025-03-09 07:57:33,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 301 states, 297 states have (on average 1.3804713804713804) internal successors, (410), 296 states have internal predecessors, (410), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:33,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 301 states to 301 states and 416 transitions. [2025-03-09 07:57:33,627 INFO L240 hiAutomatonCegarLoop]: Abstraction has 301 states and 416 transitions. [2025-03-09 07:57:33,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-09 07:57:33,628 INFO L432 stractBuchiCegarLoop]: Abstraction has 301 states and 416 transitions. [2025-03-09 07:57:33,631 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-09 07:57:33,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 301 states and 416 transitions. [2025-03-09 07:57:33,633 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 293 [2025-03-09 07:57:33,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:33,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:33,633 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:33,633 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:33,633 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:33,634 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise39#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise40#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:33,634 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:33,634 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 5 times [2025-03-09 07:57:33,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:33,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632056369] [2025-03-09 07:57:33,634 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 07:57:33,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:33,639 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:33,640 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:33,640 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:57:33,640 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:33,640 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:33,642 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:33,642 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:33,642 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:33,642 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:33,645 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:33,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:33,645 INFO L85 PathProgramCache]: Analyzing trace with hash -1004577099, now seen corresponding path program 1 times [2025-03-09 07:57:33,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:33,645 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [104623876] [2025-03-09 07:57:33,645 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:33,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:33,669 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes. [2025-03-09 07:57:33,723 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements. [2025-03-09 07:57:33,723 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:33,723 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:33,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:33,933 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:33,933 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [104623876] [2025-03-09 07:57:33,933 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [104623876] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:33,933 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:33,933 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-09 07:57:33,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289202846] [2025-03-09 07:57:33,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:33,933 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:33,933 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:33,933 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-09 07:57:33,933 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-09 07:57:33,933 INFO L87 Difference]: Start difference. First operand 301 states and 416 transitions. cyclomatic complexity: 119 Second operand has 4 states, 4 states have (on average 18.5) internal successors, (74), 4 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:34,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:34,153 INFO L93 Difference]: Finished difference Result 304 states and 419 transitions. [2025-03-09 07:57:34,153 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 304 states and 419 transitions. [2025-03-09 07:57:34,155 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 296 [2025-03-09 07:57:34,157 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 304 states to 304 states and 419 transitions. [2025-03-09 07:57:34,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 304 [2025-03-09 07:57:34,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 304 [2025-03-09 07:57:34,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 304 states and 419 transitions. [2025-03-09 07:57:34,158 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:34,158 INFO L218 hiAutomatonCegarLoop]: Abstraction has 304 states and 419 transitions. [2025-03-09 07:57:34,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304 states and 419 transitions. [2025-03-09 07:57:34,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304 to 301. [2025-03-09 07:57:34,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 301 states, 297 states have (on average 1.3771043771043772) internal successors, (409), 296 states have internal predecessors, (409), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:34,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 301 states to 301 states and 415 transitions. [2025-03-09 07:57:34,163 INFO L240 hiAutomatonCegarLoop]: Abstraction has 301 states and 415 transitions. [2025-03-09 07:57:34,164 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-09 07:57:34,165 INFO L432 stractBuchiCegarLoop]: Abstraction has 301 states and 415 transitions. [2025-03-09 07:57:34,165 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-09 07:57:34,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 301 states and 415 transitions. [2025-03-09 07:57:34,166 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 293 [2025-03-09 07:57:34,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:34,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:34,166 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:34,166 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:34,167 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:34,167 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise39#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise40#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:34,167 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:34,167 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 6 times [2025-03-09 07:57:34,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:34,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41297618] [2025-03-09 07:57:34,167 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 07:57:34,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:34,171 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:34,172 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:34,172 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 07:57:34,172 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:34,172 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:34,173 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:34,174 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:34,174 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:34,174 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:34,176 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:34,177 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:34,177 INFO L85 PathProgramCache]: Analyzing trace with hash -1723225310, now seen corresponding path program 1 times [2025-03-09 07:57:34,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:34,177 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186093027] [2025-03-09 07:57:34,177 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:34,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:34,198 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-09 07:57:34,217 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-09 07:57:34,218 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:34,218 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:34,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:34,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:34,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186093027] [2025-03-09 07:57:34,498 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186093027] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:34,498 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:34,498 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 07:57:34,499 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879731451] [2025-03-09 07:57:34,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:34,499 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:34,501 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:34,502 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 07:57:34,502 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-09 07:57:34,502 INFO L87 Difference]: Start difference. First operand 301 states and 415 transitions. cyclomatic complexity: 118 Second operand has 9 states, 9 states have (on average 8.333333333333334) internal successors, (75), 9 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:35,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:35,229 INFO L93 Difference]: Finished difference Result 317 states and 437 transitions. [2025-03-09 07:57:35,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 317 states and 437 transitions. [2025-03-09 07:57:35,230 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 309 [2025-03-09 07:57:35,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 317 states to 317 states and 437 transitions. [2025-03-09 07:57:35,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 317 [2025-03-09 07:57:35,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 317 [2025-03-09 07:57:35,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 317 states and 437 transitions. [2025-03-09 07:57:35,232 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:35,233 INFO L218 hiAutomatonCegarLoop]: Abstraction has 317 states and 437 transitions. [2025-03-09 07:57:35,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317 states and 437 transitions. [2025-03-09 07:57:35,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317 to 311. [2025-03-09 07:57:35,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 311 states, 307 states have (on average 1.3778501628664495) internal successors, (423), 306 states have internal predecessors, (423), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:35,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311 states to 311 states and 429 transitions. [2025-03-09 07:57:35,237 INFO L240 hiAutomatonCegarLoop]: Abstraction has 311 states and 429 transitions. [2025-03-09 07:57:35,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-09 07:57:35,238 INFO L432 stractBuchiCegarLoop]: Abstraction has 311 states and 429 transitions. [2025-03-09 07:57:35,238 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-09 07:57:35,238 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 311 states and 429 transitions. [2025-03-09 07:57:35,239 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 303 [2025-03-09 07:57:35,239 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:35,239 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:35,239 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:35,239 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:35,239 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:35,239 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise39#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise40#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:35,240 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:35,240 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 7 times [2025-03-09 07:57:35,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:35,240 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445107326] [2025-03-09 07:57:35,240 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 07:57:35,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:35,244 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:35,244 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:35,244 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:35,244 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:35,244 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:35,246 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:35,246 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:35,246 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:35,246 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:35,249 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:35,249 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:35,249 INFO L85 PathProgramCache]: Analyzing trace with hash 1598205542, now seen corresponding path program 1 times [2025-03-09 07:57:35,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:35,249 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [224364092] [2025-03-09 07:57:35,249 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:35,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:35,271 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-09 07:57:35,337 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-09 07:57:35,337 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:35,337 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:35,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:35,685 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:35,685 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [224364092] [2025-03-09 07:57:35,685 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [224364092] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:35,685 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:35,685 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2025-03-09 07:57:35,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129239022] [2025-03-09 07:57:35,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:35,685 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:35,686 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:35,686 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-09 07:57:35,686 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2025-03-09 07:57:35,686 INFO L87 Difference]: Start difference. First operand 311 states and 429 transitions. cyclomatic complexity: 122 Second operand has 8 states, 8 states have (on average 9.375) internal successors, (75), 8 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:36,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:36,239 INFO L93 Difference]: Finished difference Result 317 states and 436 transitions. [2025-03-09 07:57:36,239 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 317 states and 436 transitions. [2025-03-09 07:57:36,241 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 309 [2025-03-09 07:57:36,243 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 317 states to 317 states and 436 transitions. [2025-03-09 07:57:36,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 317 [2025-03-09 07:57:36,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 317 [2025-03-09 07:57:36,243 INFO L73 IsDeterministic]: Start isDeterministic. Operand 317 states and 436 transitions. [2025-03-09 07:57:36,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:36,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 317 states and 436 transitions. [2025-03-09 07:57:36,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317 states and 436 transitions. [2025-03-09 07:57:36,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317 to 314. [2025-03-09 07:57:36,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 314 states, 310 states have (on average 1.3741935483870968) internal successors, (426), 309 states have internal predecessors, (426), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:36,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 314 states to 314 states and 432 transitions. [2025-03-09 07:57:36,248 INFO L240 hiAutomatonCegarLoop]: Abstraction has 314 states and 432 transitions. [2025-03-09 07:57:36,249 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-09 07:57:36,249 INFO L432 stractBuchiCegarLoop]: Abstraction has 314 states and 432 transitions. [2025-03-09 07:57:36,249 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-09 07:57:36,249 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 314 states and 432 transitions. [2025-03-09 07:57:36,250 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 306 [2025-03-09 07:57:36,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:36,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:36,251 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:36,251 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:36,251 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:36,251 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise39#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise40#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:36,252 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:36,252 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 8 times [2025-03-09 07:57:36,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:36,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572705316] [2025-03-09 07:57:36,252 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:57:36,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:36,257 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:36,257 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:36,257 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:57:36,257 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:36,257 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:36,259 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:36,259 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:36,259 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:36,259 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:36,262 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:36,262 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:36,262 INFO L85 PathProgramCache]: Analyzing trace with hash 1935079430, now seen corresponding path program 1 times [2025-03-09 07:57:36,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:36,262 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223492722] [2025-03-09 07:57:36,262 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:36,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:36,284 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-09 07:57:36,302 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-09 07:57:36,306 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:36,306 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:36,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:36,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:36,448 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223492722] [2025-03-09 07:57:36,448 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [223492722] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:36,448 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:36,448 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-09 07:57:36,448 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [91734828] [2025-03-09 07:57:36,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:36,448 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:36,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:36,448 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-09 07:57:36,449 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-03-09 07:57:36,449 INFO L87 Difference]: Start difference. First operand 314 states and 432 transitions. cyclomatic complexity: 122 Second operand has 6 states, 6 states have (on average 12.5) internal successors, (75), 6 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:36,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:36,858 INFO L93 Difference]: Finished difference Result 317 states and 435 transitions. [2025-03-09 07:57:36,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 317 states and 435 transitions. [2025-03-09 07:57:36,860 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 309 [2025-03-09 07:57:36,861 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 317 states to 317 states and 435 transitions. [2025-03-09 07:57:36,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 317 [2025-03-09 07:57:36,861 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 317 [2025-03-09 07:57:36,861 INFO L73 IsDeterministic]: Start isDeterministic. Operand 317 states and 435 transitions. [2025-03-09 07:57:36,862 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:36,864 INFO L218 hiAutomatonCegarLoop]: Abstraction has 317 states and 435 transitions. [2025-03-09 07:57:36,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317 states and 435 transitions. [2025-03-09 07:57:36,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317 to 317. [2025-03-09 07:57:36,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 317 states, 313 states have (on average 1.3706070287539935) internal successors, (429), 312 states have internal predecessors, (429), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:36,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 435 transitions. [2025-03-09 07:57:36,871 INFO L240 hiAutomatonCegarLoop]: Abstraction has 317 states and 435 transitions. [2025-03-09 07:57:36,872 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-09 07:57:36,872 INFO L432 stractBuchiCegarLoop]: Abstraction has 317 states and 435 transitions. [2025-03-09 07:57:36,872 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-09 07:57:36,872 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 317 states and 435 transitions. [2025-03-09 07:57:36,873 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 309 [2025-03-09 07:57:36,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:36,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:36,874 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:36,874 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:36,874 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:36,874 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise39#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise40#1;assume main_#t~bitwise40#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:36,874 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:36,874 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 9 times [2025-03-09 07:57:36,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:36,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [644379252] [2025-03-09 07:57:36,875 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 07:57:36,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:36,878 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:36,879 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:36,879 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 07:57:36,879 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:36,879 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:36,880 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:36,881 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:36,881 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:36,881 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:36,883 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:36,884 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:36,884 INFO L85 PathProgramCache]: Analyzing trace with hash -1607364421, now seen corresponding path program 1 times [2025-03-09 07:57:36,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:36,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027828876] [2025-03-09 07:57:36,884 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:36,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:36,904 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-09 07:57:37,003 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-09 07:57:37,004 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:37,004 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:37,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:37,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:37,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1027828876] [2025-03-09 07:57:37,498 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1027828876] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:37,498 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:37,499 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-09 07:57:37,499 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974746784] [2025-03-09 07:57:37,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:37,499 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:37,499 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:37,499 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-09 07:57:37,499 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-09 07:57:37,500 INFO L87 Difference]: Start difference. First operand 317 states and 435 transitions. cyclomatic complexity: 122 Second operand has 13 states, 13 states have (on average 5.846153846153846) internal successors, (76), 13 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:38,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:38,742 INFO L93 Difference]: Finished difference Result 415 states and 575 transitions. [2025-03-09 07:57:38,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 415 states and 575 transitions. [2025-03-09 07:57:38,744 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 407 [2025-03-09 07:57:38,745 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 415 states to 415 states and 575 transitions. [2025-03-09 07:57:38,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 415 [2025-03-09 07:57:38,746 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 415 [2025-03-09 07:57:38,746 INFO L73 IsDeterministic]: Start isDeterministic. Operand 415 states and 575 transitions. [2025-03-09 07:57:38,747 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:38,747 INFO L218 hiAutomatonCegarLoop]: Abstraction has 415 states and 575 transitions. [2025-03-09 07:57:38,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 415 states and 575 transitions. [2025-03-09 07:57:38,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 415 to 323. [2025-03-09 07:57:38,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 319 states have (on average 1.3699059561128526) internal successors, (437), 318 states have internal predecessors, (437), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:38,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 443 transitions. [2025-03-09 07:57:38,752 INFO L240 hiAutomatonCegarLoop]: Abstraction has 323 states and 443 transitions. [2025-03-09 07:57:38,753 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-09 07:57:38,754 INFO L432 stractBuchiCegarLoop]: Abstraction has 323 states and 443 transitions. [2025-03-09 07:57:38,755 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-09 07:57:38,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 443 transitions. [2025-03-09 07:57:38,755 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 315 [2025-03-09 07:57:38,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:38,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:38,756 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:38,756 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:38,756 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:38,757 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise39#1;assume main_#t~bitwise39#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise40#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:38,757 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:38,757 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 10 times [2025-03-09 07:57:38,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:38,757 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565261590] [2025-03-09 07:57:38,757 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 07:57:38,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:38,761 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-09 07:57:38,761 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:38,761 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 07:57:38,762 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:38,762 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:38,764 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:38,764 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:38,764 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:38,764 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:38,767 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:38,768 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:38,768 INFO L85 PathProgramCache]: Analyzing trace with hash 602051466, now seen corresponding path program 1 times [2025-03-09 07:57:38,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:38,768 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598812284] [2025-03-09 07:57:38,768 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:38,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:38,791 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-09 07:57:38,839 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-09 07:57:38,839 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:38,839 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:39,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:39,024 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:39,024 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [598812284] [2025-03-09 07:57:39,024 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [598812284] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:39,024 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:39,024 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-09 07:57:39,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787180738] [2025-03-09 07:57:39,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:39,024 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:39,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:39,024 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-09 07:57:39,025 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-09 07:57:39,026 INFO L87 Difference]: Start difference. First operand 323 states and 443 transitions. cyclomatic complexity: 124 Second operand has 7 states, 7 states have (on average 10.857142857142858) internal successors, (76), 7 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:39,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:39,496 INFO L93 Difference]: Finished difference Result 330 states and 452 transitions. [2025-03-09 07:57:39,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 330 states and 452 transitions. [2025-03-09 07:57:39,497 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 322 [2025-03-09 07:57:39,499 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 330 states to 330 states and 452 transitions. [2025-03-09 07:57:39,499 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 330 [2025-03-09 07:57:39,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 330 [2025-03-09 07:57:39,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 330 states and 452 transitions. [2025-03-09 07:57:39,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:39,500 INFO L218 hiAutomatonCegarLoop]: Abstraction has 330 states and 452 transitions. [2025-03-09 07:57:39,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330 states and 452 transitions. [2025-03-09 07:57:39,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330 to 323. [2025-03-09 07:57:39,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 319 states have (on average 1.3699059561128526) internal successors, (437), 318 states have internal predecessors, (437), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:39,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 443 transitions. [2025-03-09 07:57:39,504 INFO L240 hiAutomatonCegarLoop]: Abstraction has 323 states and 443 transitions. [2025-03-09 07:57:39,504 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-09 07:57:39,504 INFO L432 stractBuchiCegarLoop]: Abstraction has 323 states and 443 transitions. [2025-03-09 07:57:39,504 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-09 07:57:39,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 443 transitions. [2025-03-09 07:57:39,505 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 315 [2025-03-09 07:57:39,505 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:39,505 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:39,506 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:39,506 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:39,506 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:39,506 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise39#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise40#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise42#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:39,506 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:39,506 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 11 times [2025-03-09 07:57:39,507 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:39,507 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568695489] [2025-03-09 07:57:39,507 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 07:57:39,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:39,510 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:39,511 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:39,511 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:57:39,511 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:39,511 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:39,512 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:39,513 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:39,513 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:39,513 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:39,515 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:39,516 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:39,516 INFO L85 PathProgramCache]: Analyzing trace with hash -2133358209, now seen corresponding path program 1 times [2025-03-09 07:57:39,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:39,516 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2116487063] [2025-03-09 07:57:39,516 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:39,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:39,536 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-09 07:57:39,562 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-09 07:57:39,563 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:39,563 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:39,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:39,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:39,775 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2116487063] [2025-03-09 07:57:39,775 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2116487063] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:39,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:39,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-09 07:57:39,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085795458] [2025-03-09 07:57:39,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:39,776 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:39,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:39,777 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-09 07:57:39,777 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-03-09 07:57:39,777 INFO L87 Difference]: Start difference. First operand 323 states and 443 transitions. cyclomatic complexity: 124 Second operand has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 6 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:40,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:40,239 INFO L93 Difference]: Finished difference Result 320 states and 439 transitions. [2025-03-09 07:57:40,239 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 320 states and 439 transitions. [2025-03-09 07:57:40,241 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 312 [2025-03-09 07:57:40,242 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 320 states to 320 states and 439 transitions. [2025-03-09 07:57:40,242 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 320 [2025-03-09 07:57:40,242 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 320 [2025-03-09 07:57:40,242 INFO L73 IsDeterministic]: Start isDeterministic. Operand 320 states and 439 transitions. [2025-03-09 07:57:40,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:40,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 320 states and 439 transitions. [2025-03-09 07:57:40,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 320 states and 439 transitions. [2025-03-09 07:57:40,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 320 to 320. [2025-03-09 07:57:40,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 320 states, 316 states have (on average 1.370253164556962) internal successors, (433), 315 states have internal predecessors, (433), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:40,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 320 states to 320 states and 439 transitions. [2025-03-09 07:57:40,247 INFO L240 hiAutomatonCegarLoop]: Abstraction has 320 states and 439 transitions. [2025-03-09 07:57:40,248 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-09 07:57:40,249 INFO L432 stractBuchiCegarLoop]: Abstraction has 320 states and 439 transitions. [2025-03-09 07:57:40,249 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-09 07:57:40,249 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 320 states and 439 transitions. [2025-03-09 07:57:40,250 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 312 [2025-03-09 07:57:40,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:40,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:40,250 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:40,250 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:40,251 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:40,251 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise39#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise40#1;assume main_#t~bitwise40#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise42#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:40,251 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:40,251 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 12 times [2025-03-09 07:57:40,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:40,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253864947] [2025-03-09 07:57:40,251 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 07:57:40,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:40,255 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:40,256 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:40,256 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 07:57:40,256 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:40,256 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:40,257 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:40,257 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:40,257 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:40,258 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:40,261 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:40,261 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:40,261 INFO L85 PathProgramCache]: Analyzing trace with hash 1986244462, now seen corresponding path program 1 times [2025-03-09 07:57:40,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:40,262 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247936417] [2025-03-09 07:57:40,262 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:40,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:40,287 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-09 07:57:40,372 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-09 07:57:40,373 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:40,373 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:40,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:40,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:40,717 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247936417] [2025-03-09 07:57:40,717 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [247936417] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:40,717 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:40,717 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2025-03-09 07:57:40,717 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766188845] [2025-03-09 07:57:40,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:40,717 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:40,717 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:40,717 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2025-03-09 07:57:40,718 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2025-03-09 07:57:40,718 INFO L87 Difference]: Start difference. First operand 320 states and 439 transitions. cyclomatic complexity: 123 Second operand has 11 states, 11 states have (on average 7.0) internal successors, (77), 11 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:41,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:41,667 INFO L93 Difference]: Finished difference Result 392 states and 537 transitions. [2025-03-09 07:57:41,668 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 392 states and 537 transitions. [2025-03-09 07:57:41,669 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 384 [2025-03-09 07:57:41,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 392 states to 392 states and 537 transitions. [2025-03-09 07:57:41,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 392 [2025-03-09 07:57:41,671 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 392 [2025-03-09 07:57:41,671 INFO L73 IsDeterministic]: Start isDeterministic. Operand 392 states and 537 transitions. [2025-03-09 07:57:41,671 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:41,671 INFO L218 hiAutomatonCegarLoop]: Abstraction has 392 states and 537 transitions. [2025-03-09 07:57:41,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states and 537 transitions. [2025-03-09 07:57:41,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 323. [2025-03-09 07:57:41,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 319 states have (on average 1.3699059561128526) internal successors, (437), 318 states have internal predecessors, (437), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:41,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 443 transitions. [2025-03-09 07:57:41,675 INFO L240 hiAutomatonCegarLoop]: Abstraction has 323 states and 443 transitions. [2025-03-09 07:57:41,676 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-09 07:57:41,678 INFO L432 stractBuchiCegarLoop]: Abstraction has 323 states and 443 transitions. [2025-03-09 07:57:41,678 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-09 07:57:41,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 443 transitions. [2025-03-09 07:57:41,679 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 315 [2025-03-09 07:57:41,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:41,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:41,679 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:41,679 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:41,679 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:41,679 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise39#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise40#1;assume main_#t~bitwise40#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise43#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:41,680 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:41,680 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 13 times [2025-03-09 07:57:41,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:41,680 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1100787414] [2025-03-09 07:57:41,680 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 07:57:41,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:41,684 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:41,684 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:41,684 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:41,685 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:41,685 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:41,686 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:41,686 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:41,686 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:41,686 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:41,689 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:41,689 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:41,689 INFO L85 PathProgramCache]: Analyzing trace with hash -1789978553, now seen corresponding path program 1 times [2025-03-09 07:57:41,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:41,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1766881011] [2025-03-09 07:57:41,689 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:41,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:41,711 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-09 07:57:41,799 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-09 07:57:41,800 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:41,800 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:42,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:42,121 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:42,121 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1766881011] [2025-03-09 07:57:42,121 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1766881011] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:42,121 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:42,121 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-09 07:57:42,121 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1837232211] [2025-03-09 07:57:42,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:42,121 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:42,121 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:42,122 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-09 07:57:42,122 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-09 07:57:42,122 INFO L87 Difference]: Start difference. First operand 323 states and 443 transitions. cyclomatic complexity: 124 Second operand has 13 states, 13 states have (on average 5.923076923076923) internal successors, (77), 13 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:43,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:43,361 INFO L93 Difference]: Finished difference Result 416 states and 575 transitions. [2025-03-09 07:57:43,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 416 states and 575 transitions. [2025-03-09 07:57:43,363 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 408 [2025-03-09 07:57:43,365 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 416 states to 416 states and 575 transitions. [2025-03-09 07:57:43,365 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 416 [2025-03-09 07:57:43,365 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 416 [2025-03-09 07:57:43,365 INFO L73 IsDeterministic]: Start isDeterministic. Operand 416 states and 575 transitions. [2025-03-09 07:57:43,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:43,366 INFO L218 hiAutomatonCegarLoop]: Abstraction has 416 states and 575 transitions. [2025-03-09 07:57:43,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416 states and 575 transitions. [2025-03-09 07:57:43,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416 to 324. [2025-03-09 07:57:43,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 324 states, 320 states have (on average 1.371875) internal successors, (439), 319 states have internal predecessors, (439), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:43,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 324 states to 324 states and 445 transitions. [2025-03-09 07:57:43,370 INFO L240 hiAutomatonCegarLoop]: Abstraction has 324 states and 445 transitions. [2025-03-09 07:57:43,371 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-09 07:57:43,371 INFO L432 stractBuchiCegarLoop]: Abstraction has 324 states and 445 transitions. [2025-03-09 07:57:43,371 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-09 07:57:43,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 324 states and 445 transitions. [2025-03-09 07:57:43,372 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 316 [2025-03-09 07:57:43,372 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:43,372 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:43,373 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:43,373 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:43,373 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:43,373 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise39#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise40#1;assume main_#t~bitwise40#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 32 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:43,373 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:43,373 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 14 times [2025-03-09 07:57:43,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:43,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1860314341] [2025-03-09 07:57:43,374 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:57:43,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:43,378 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:43,378 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:43,378 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:57:43,378 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:43,379 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:43,380 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:43,380 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:43,380 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:43,380 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:43,383 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:43,384 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:43,384 INFO L85 PathProgramCache]: Analyzing trace with hash -108993696, now seen corresponding path program 1 times [2025-03-09 07:57:43,384 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:43,384 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935799857] [2025-03-09 07:57:43,384 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:43,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:43,406 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-09 07:57:43,458 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-09 07:57:43,459 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:43,459 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:43,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:43,992 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:43,992 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [935799857] [2025-03-09 07:57:43,992 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [935799857] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:43,992 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:43,992 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 07:57:43,992 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077889241] [2025-03-09 07:57:43,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:43,992 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:43,992 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:43,993 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 07:57:43,993 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2025-03-09 07:57:43,993 INFO L87 Difference]: Start difference. First operand 324 states and 445 transitions. cyclomatic complexity: 125 Second operand has 9 states, 9 states have (on average 8.555555555555555) internal successors, (77), 9 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:44,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:44,349 INFO L93 Difference]: Finished difference Result 316 states and 432 transitions. [2025-03-09 07:57:44,349 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 316 states and 432 transitions. [2025-03-09 07:57:44,350 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 308 [2025-03-09 07:57:44,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 316 states to 316 states and 432 transitions. [2025-03-09 07:57:44,352 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 316 [2025-03-09 07:57:44,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 316 [2025-03-09 07:57:44,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 316 states and 432 transitions. [2025-03-09 07:57:44,352 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:44,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 316 states and 432 transitions. [2025-03-09 07:57:44,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 316 states and 432 transitions. [2025-03-09 07:57:44,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 316 to 314. [2025-03-09 07:57:44,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 314 states, 310 states have (on average 1.367741935483871) internal successors, (424), 309 states have internal predecessors, (424), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:44,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 314 states to 314 states and 430 transitions. [2025-03-09 07:57:44,357 INFO L240 hiAutomatonCegarLoop]: Abstraction has 314 states and 430 transitions. [2025-03-09 07:57:44,358 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-09 07:57:44,358 INFO L432 stractBuchiCegarLoop]: Abstraction has 314 states and 430 transitions. [2025-03-09 07:57:44,358 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-09 07:57:44,358 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 314 states and 430 transitions. [2025-03-09 07:57:44,359 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 306 [2025-03-09 07:57:44,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:44,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:44,359 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:44,360 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:44,360 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:44,360 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise39#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise40#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:44,360 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:44,360 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 15 times [2025-03-09 07:57:44,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:44,361 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [48415507] [2025-03-09 07:57:44,361 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 07:57:44,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:44,365 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:44,365 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:44,366 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 07:57:44,366 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:44,366 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:44,369 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:44,369 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:44,369 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:44,369 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:44,372 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:44,372 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:44,372 INFO L85 PathProgramCache]: Analyzing trace with hash 1762270655, now seen corresponding path program 1 times [2025-03-09 07:57:44,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:44,373 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918206549] [2025-03-09 07:57:44,373 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:44,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:44,394 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-09 07:57:44,409 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-09 07:57:44,410 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:44,410 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:44,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:44,601 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:44,602 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [918206549] [2025-03-09 07:57:44,602 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [918206549] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:44,602 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:44,602 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 07:57:44,602 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1828232959] [2025-03-09 07:57:44,602 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:44,602 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:44,602 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:44,603 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 07:57:44,603 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2025-03-09 07:57:44,603 INFO L87 Difference]: Start difference. First operand 314 states and 430 transitions. cyclomatic complexity: 120 Second operand has 9 states, 9 states have (on average 8.555555555555555) internal successors, (77), 9 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:45,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:45,156 INFO L93 Difference]: Finished difference Result 327 states and 446 transitions. [2025-03-09 07:57:45,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 446 transitions. [2025-03-09 07:57:45,157 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 319 [2025-03-09 07:57:45,158 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 327 states and 446 transitions. [2025-03-09 07:57:45,158 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2025-03-09 07:57:45,160 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2025-03-09 07:57:45,160 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 446 transitions. [2025-03-09 07:57:45,160 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:45,160 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 446 transitions. [2025-03-09 07:57:45,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 446 transitions. [2025-03-09 07:57:45,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 314. [2025-03-09 07:57:45,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 314 states, 310 states have (on average 1.367741935483871) internal successors, (424), 309 states have internal predecessors, (424), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:45,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 314 states to 314 states and 430 transitions. [2025-03-09 07:57:45,166 INFO L240 hiAutomatonCegarLoop]: Abstraction has 314 states and 430 transitions. [2025-03-09 07:57:45,166 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-09 07:57:45,166 INFO L432 stractBuchiCegarLoop]: Abstraction has 314 states and 430 transitions. [2025-03-09 07:57:45,166 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-09 07:57:45,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 314 states and 430 transitions. [2025-03-09 07:57:45,167 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 306 [2025-03-09 07:57:45,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:45,167 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:45,168 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:45,168 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:45,168 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:45,169 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise39#1;assume main_#t~bitwise39#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise40#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:45,169 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:45,169 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 16 times [2025-03-09 07:57:45,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:45,169 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [852185301] [2025-03-09 07:57:45,169 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 07:57:45,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:45,175 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-09 07:57:45,176 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:45,176 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 07:57:45,176 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:45,176 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:45,177 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:45,178 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:45,178 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:45,178 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:45,181 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:45,182 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:45,182 INFO L85 PathProgramCache]: Analyzing trace with hash 1461612518, now seen corresponding path program 1 times [2025-03-09 07:57:45,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:45,182 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1984493482] [2025-03-09 07:57:45,182 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:45,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:45,211 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-09 07:57:45,257 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-09 07:57:45,257 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:45,257 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:45,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:45,413 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:45,413 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1984493482] [2025-03-09 07:57:45,413 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1984493482] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:45,414 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:45,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 07:57:45,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [636899632] [2025-03-09 07:57:45,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:45,414 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:45,414 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:45,414 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 07:57:45,414 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-09 07:57:45,415 INFO L87 Difference]: Start difference. First operand 314 states and 430 transitions. cyclomatic complexity: 120 Second operand has 9 states, 9 states have (on average 8.555555555555555) internal successors, (77), 9 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:46,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:46,035 INFO L93 Difference]: Finished difference Result 334 states and 456 transitions. [2025-03-09 07:57:46,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 334 states and 456 transitions. [2025-03-09 07:57:46,037 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 326 [2025-03-09 07:57:46,038 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 334 states to 334 states and 456 transitions. [2025-03-09 07:57:46,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 334 [2025-03-09 07:57:46,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 334 [2025-03-09 07:57:46,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 334 states and 456 transitions. [2025-03-09 07:57:46,038 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:46,039 INFO L218 hiAutomatonCegarLoop]: Abstraction has 334 states and 456 transitions. [2025-03-09 07:57:46,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 334 states and 456 transitions. [2025-03-09 07:57:46,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 334 to 314. [2025-03-09 07:57:46,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 314 states, 310 states have (on average 1.367741935483871) internal successors, (424), 309 states have internal predecessors, (424), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:46,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 314 states to 314 states and 430 transitions. [2025-03-09 07:57:46,042 INFO L240 hiAutomatonCegarLoop]: Abstraction has 314 states and 430 transitions. [2025-03-09 07:57:46,042 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 07:57:46,043 INFO L432 stractBuchiCegarLoop]: Abstraction has 314 states and 430 transitions. [2025-03-09 07:57:46,043 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-09 07:57:46,043 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 314 states and 430 transitions. [2025-03-09 07:57:46,043 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 306 [2025-03-09 07:57:46,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:46,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:46,044 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:46,044 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:46,044 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:46,044 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise39#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise40#1;assume main_#t~bitwise40#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise42#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:46,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:46,045 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 17 times [2025-03-09 07:57:46,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:46,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728945058] [2025-03-09 07:57:46,045 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 07:57:46,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:46,049 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:46,049 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:46,049 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:57:46,049 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:46,049 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:46,050 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:46,050 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:46,050 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:46,050 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:46,053 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:46,054 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:46,054 INFO L85 PathProgramCache]: Analyzing trace with hash 1100425876, now seen corresponding path program 1 times [2025-03-09 07:57:46,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:46,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1066784718] [2025-03-09 07:57:46,054 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:46,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:46,076 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-09 07:57:46,119 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-09 07:57:46,119 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:46,119 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:46,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:46,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:46,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1066784718] [2025-03-09 07:57:46,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1066784718] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:46,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:46,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 07:57:46,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1863825848] [2025-03-09 07:57:46,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:46,424 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:46,424 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:46,425 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 07:57:46,425 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-09 07:57:46,425 INFO L87 Difference]: Start difference. First operand 314 states and 430 transitions. cyclomatic complexity: 120 Second operand has 9 states, 9 states have (on average 8.666666666666666) internal successors, (78), 9 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:47,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:47,194 INFO L93 Difference]: Finished difference Result 328 states and 446 transitions. [2025-03-09 07:57:47,194 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 328 states and 446 transitions. [2025-03-09 07:57:47,196 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 320 [2025-03-09 07:57:47,197 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 328 states to 328 states and 446 transitions. [2025-03-09 07:57:47,197 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 328 [2025-03-09 07:57:47,197 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 328 [2025-03-09 07:57:47,197 INFO L73 IsDeterministic]: Start isDeterministic. Operand 328 states and 446 transitions. [2025-03-09 07:57:47,197 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:47,197 INFO L218 hiAutomatonCegarLoop]: Abstraction has 328 states and 446 transitions. [2025-03-09 07:57:47,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 328 states and 446 transitions. [2025-03-09 07:57:47,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 328 to 320. [2025-03-09 07:57:47,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 320 states, 316 states have (on average 1.3639240506329113) internal successors, (431), 315 states have internal predecessors, (431), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:47,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 320 states to 320 states and 437 transitions. [2025-03-09 07:57:47,201 INFO L240 hiAutomatonCegarLoop]: Abstraction has 320 states and 437 transitions. [2025-03-09 07:57:47,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 07:57:47,202 INFO L432 stractBuchiCegarLoop]: Abstraction has 320 states and 437 transitions. [2025-03-09 07:57:47,202 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-09 07:57:47,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 320 states and 437 transitions. [2025-03-09 07:57:47,202 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 312 [2025-03-09 07:57:47,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:47,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:47,203 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:47,203 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:47,203 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:47,203 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise39#1;assume main_#t~bitwise39#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise40#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise42#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:47,204 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:47,204 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 18 times [2025-03-09 07:57:47,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:47,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [328007550] [2025-03-09 07:57:47,204 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 07:57:47,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:47,208 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:47,208 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:47,208 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 07:57:47,208 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:47,208 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:47,209 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:47,210 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:47,210 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:47,210 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:47,213 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:47,213 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:47,213 INFO L85 PathProgramCache]: Analyzing trace with hash -1659718237, now seen corresponding path program 1 times [2025-03-09 07:57:47,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:47,213 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60201256] [2025-03-09 07:57:47,213 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:47,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:47,234 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-09 07:57:47,272 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-09 07:57:47,273 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:47,273 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:47,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:47,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:47,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60201256] [2025-03-09 07:57:47,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [60201256] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:47,467 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:47,467 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-09 07:57:47,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1454245651] [2025-03-09 07:57:47,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:47,467 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:47,467 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:47,467 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-09 07:57:47,467 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2025-03-09 07:57:47,468 INFO L87 Difference]: Start difference. First operand 320 states and 437 transitions. cyclomatic complexity: 121 Second operand has 10 states, 10 states have (on average 7.8) internal successors, (78), 10 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:48,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:48,167 INFO L93 Difference]: Finished difference Result 341 states and 466 transitions. [2025-03-09 07:57:48,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 341 states and 466 transitions. [2025-03-09 07:57:48,168 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 333 [2025-03-09 07:57:48,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 341 states to 341 states and 466 transitions. [2025-03-09 07:57:48,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 341 [2025-03-09 07:57:48,169 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 341 [2025-03-09 07:57:48,169 INFO L73 IsDeterministic]: Start isDeterministic. Operand 341 states and 466 transitions. [2025-03-09 07:57:48,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:48,170 INFO L218 hiAutomatonCegarLoop]: Abstraction has 341 states and 466 transitions. [2025-03-09 07:57:48,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 341 states and 466 transitions. [2025-03-09 07:57:48,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 341 to 333. [2025-03-09 07:57:48,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 333 states, 329 states have (on average 1.3617021276595744) internal successors, (448), 328 states have internal predecessors, (448), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:48,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 333 states to 333 states and 454 transitions. [2025-03-09 07:57:48,174 INFO L240 hiAutomatonCegarLoop]: Abstraction has 333 states and 454 transitions. [2025-03-09 07:57:48,174 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 07:57:48,175 INFO L432 stractBuchiCegarLoop]: Abstraction has 333 states and 454 transitions. [2025-03-09 07:57:48,175 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-09 07:57:48,175 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 333 states and 454 transitions. [2025-03-09 07:57:48,176 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 325 [2025-03-09 07:57:48,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:48,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:48,176 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:48,176 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:48,176 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:48,177 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise39#1;assume main_#t~bitwise39#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise40#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:48,177 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:48,177 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 19 times [2025-03-09 07:57:48,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:48,177 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [567905005] [2025-03-09 07:57:48,177 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 07:57:48,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:48,182 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:48,182 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:48,182 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:48,182 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:48,182 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:48,184 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:48,184 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:48,184 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:48,184 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:48,188 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:48,188 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:48,189 INFO L85 PathProgramCache]: Analyzing trace with hash -350884985, now seen corresponding path program 1 times [2025-03-09 07:57:48,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:48,189 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872454780] [2025-03-09 07:57:48,189 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:48,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:48,211 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-09 07:57:48,238 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-09 07:57:48,239 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:48,239 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:48,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:48,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:48,374 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1872454780] [2025-03-09 07:57:48,374 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1872454780] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:48,375 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:48,375 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-09 07:57:48,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [436127206] [2025-03-09 07:57:48,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:48,375 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:48,375 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:48,375 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-09 07:57:48,376 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-09 07:57:48,376 INFO L87 Difference]: Start difference. First operand 333 states and 454 transitions. cyclomatic complexity: 125 Second operand has 7 states, 7 states have (on average 11.142857142857142) internal successors, (78), 7 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:48,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:48,952 INFO L93 Difference]: Finished difference Result 338 states and 460 transitions. [2025-03-09 07:57:48,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 338 states and 460 transitions. [2025-03-09 07:57:48,953 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 330 [2025-03-09 07:57:48,954 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 338 states to 338 states and 460 transitions. [2025-03-09 07:57:48,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 338 [2025-03-09 07:57:48,955 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 338 [2025-03-09 07:57:48,955 INFO L73 IsDeterministic]: Start isDeterministic. Operand 338 states and 460 transitions. [2025-03-09 07:57:48,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:48,955 INFO L218 hiAutomatonCegarLoop]: Abstraction has 338 states and 460 transitions. [2025-03-09 07:57:48,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 338 states and 460 transitions. [2025-03-09 07:57:48,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 338 to 337. [2025-03-09 07:57:48,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 337 states, 333 states have (on average 1.3603603603603605) internal successors, (453), 332 states have internal predecessors, (453), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:48,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 337 states to 337 states and 459 transitions. [2025-03-09 07:57:48,959 INFO L240 hiAutomatonCegarLoop]: Abstraction has 337 states and 459 transitions. [2025-03-09 07:57:48,960 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-09 07:57:48,960 INFO L432 stractBuchiCegarLoop]: Abstraction has 337 states and 459 transitions. [2025-03-09 07:57:48,960 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-09 07:57:48,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 337 states and 459 transitions. [2025-03-09 07:57:48,961 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 329 [2025-03-09 07:57:48,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:48,961 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:48,961 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:48,961 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:48,962 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:48,962 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise39#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise40#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise42#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:48,962 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:48,962 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 20 times [2025-03-09 07:57:48,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:48,962 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151263166] [2025-03-09 07:57:48,962 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 07:57:48,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:48,966 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:48,967 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:48,967 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:57:48,967 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:48,967 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:48,970 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:48,994 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:48,994 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:48,994 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:48,997 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:48,998 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:48,998 INFO L85 PathProgramCache]: Analyzing trace with hash -929250582, now seen corresponding path program 1 times [2025-03-09 07:57:48,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:48,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [828801137] [2025-03-09 07:57:48,999 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:48,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:49,023 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-09 07:57:49,034 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-09 07:57:49,034 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:49,034 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:49,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:49,222 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:49,222 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [828801137] [2025-03-09 07:57:49,222 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [828801137] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:49,222 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:49,222 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-09 07:57:49,223 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1098259863] [2025-03-09 07:57:49,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:49,223 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:49,223 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:49,223 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-09 07:57:49,223 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2025-03-09 07:57:49,223 INFO L87 Difference]: Start difference. First operand 337 states and 459 transitions. cyclomatic complexity: 126 Second operand has 10 states, 10 states have (on average 7.8) internal successors, (78), 10 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:49,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:49,796 INFO L93 Difference]: Finished difference Result 347 states and 472 transitions. [2025-03-09 07:57:49,796 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 347 states and 472 transitions. [2025-03-09 07:57:49,797 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 339 [2025-03-09 07:57:49,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 347 states to 347 states and 472 transitions. [2025-03-09 07:57:49,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 347 [2025-03-09 07:57:49,798 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 347 [2025-03-09 07:57:49,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 347 states and 472 transitions. [2025-03-09 07:57:49,799 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:49,799 INFO L218 hiAutomatonCegarLoop]: Abstraction has 347 states and 472 transitions. [2025-03-09 07:57:49,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 347 states and 472 transitions. [2025-03-09 07:57:49,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 347 to 334. [2025-03-09 07:57:49,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 334 states, 330 states have (on average 1.3575757575757577) internal successors, (448), 329 states have internal predecessors, (448), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:49,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 334 states to 334 states and 454 transitions. [2025-03-09 07:57:49,803 INFO L240 hiAutomatonCegarLoop]: Abstraction has 334 states and 454 transitions. [2025-03-09 07:57:49,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 07:57:49,804 INFO L432 stractBuchiCegarLoop]: Abstraction has 334 states and 454 transitions. [2025-03-09 07:57:49,804 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-03-09 07:57:49,804 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 334 states and 454 transitions. [2025-03-09 07:57:49,805 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 326 [2025-03-09 07:57:49,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:49,805 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:49,805 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:49,805 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:49,805 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:49,806 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise39#1;assume main_#t~bitwise39#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise40#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:49,806 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:49,806 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 21 times [2025-03-09 07:57:49,807 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:49,807 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [169023612] [2025-03-09 07:57:49,807 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 07:57:49,807 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:49,811 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:49,811 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:49,811 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 07:57:49,811 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:49,811 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:49,813 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:49,813 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:49,813 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:49,813 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:49,816 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:49,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:49,817 INFO L85 PathProgramCache]: Analyzing trace with hash 622651459, now seen corresponding path program 1 times [2025-03-09 07:57:49,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:49,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [153121446] [2025-03-09 07:57:49,817 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:49,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:49,839 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-09 07:57:49,883 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-09 07:57:49,883 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:49,884 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:50,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:50,113 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:50,113 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [153121446] [2025-03-09 07:57:50,113 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [153121446] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:50,113 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:50,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-09 07:57:50,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1161018709] [2025-03-09 07:57:50,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:50,114 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:50,114 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:50,114 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-09 07:57:50,114 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-09 07:57:50,114 INFO L87 Difference]: Start difference. First operand 334 states and 454 transitions. cyclomatic complexity: 124 Second operand has 7 states, 7 states have (on average 11.142857142857142) internal successors, (78), 7 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:50,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:50,565 INFO L93 Difference]: Finished difference Result 341 states and 460 transitions. [2025-03-09 07:57:50,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 341 states and 460 transitions. [2025-03-09 07:57:50,566 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 333 [2025-03-09 07:57:50,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 341 states to 341 states and 460 transitions. [2025-03-09 07:57:50,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 341 [2025-03-09 07:57:50,569 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 341 [2025-03-09 07:57:50,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 341 states and 460 transitions. [2025-03-09 07:57:50,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:50,571 INFO L218 hiAutomatonCegarLoop]: Abstraction has 341 states and 460 transitions. [2025-03-09 07:57:50,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 341 states and 460 transitions. [2025-03-09 07:57:50,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 341 to 334. [2025-03-09 07:57:50,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 334 states, 330 states have (on average 1.3545454545454545) internal successors, (447), 329 states have internal predecessors, (447), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:50,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 334 states to 334 states and 453 transitions. [2025-03-09 07:57:50,576 INFO L240 hiAutomatonCegarLoop]: Abstraction has 334 states and 453 transitions. [2025-03-09 07:57:50,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-09 07:57:50,577 INFO L432 stractBuchiCegarLoop]: Abstraction has 334 states and 453 transitions. [2025-03-09 07:57:50,577 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-03-09 07:57:50,577 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 334 states and 453 transitions. [2025-03-09 07:57:50,578 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 326 [2025-03-09 07:57:50,579 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:50,579 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:50,580 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:50,580 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:50,580 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:50,581 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise39#1;assume main_#t~bitwise39#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise40#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise42#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise43#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:50,581 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:50,581 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 22 times [2025-03-09 07:57:50,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:50,581 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [314365678] [2025-03-09 07:57:50,581 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 07:57:50,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:50,589 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-09 07:57:50,589 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:50,590 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 07:57:50,590 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:50,590 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:50,592 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:50,592 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:50,592 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:50,592 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:50,597 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:50,598 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:50,598 INFO L85 PathProgramCache]: Analyzing trace with hash 882020447, now seen corresponding path program 1 times [2025-03-09 07:57:50,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:50,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892683421] [2025-03-09 07:57:50,598 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:50,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:50,627 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-09 07:57:50,671 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-09 07:57:50,671 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:50,671 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:50,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:50,857 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:50,857 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1892683421] [2025-03-09 07:57:50,857 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1892683421] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:50,857 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:50,857 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2025-03-09 07:57:50,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [474879728] [2025-03-09 07:57:50,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:50,857 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:50,857 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:50,857 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2025-03-09 07:57:50,857 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2025-03-09 07:57:50,858 INFO L87 Difference]: Start difference. First operand 334 states and 453 transitions. cyclomatic complexity: 123 Second operand has 11 states, 11 states have (on average 7.181818181818182) internal successors, (79), 11 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:51,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:51,517 INFO L93 Difference]: Finished difference Result 350 states and 473 transitions. [2025-03-09 07:57:51,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 350 states and 473 transitions. [2025-03-09 07:57:51,518 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 342 [2025-03-09 07:57:51,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 350 states to 350 states and 473 transitions. [2025-03-09 07:57:51,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350 [2025-03-09 07:57:51,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 350 [2025-03-09 07:57:51,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 350 states and 473 transitions. [2025-03-09 07:57:51,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:51,520 INFO L218 hiAutomatonCegarLoop]: Abstraction has 350 states and 473 transitions. [2025-03-09 07:57:51,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350 states and 473 transitions. [2025-03-09 07:57:51,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350 to 337. [2025-03-09 07:57:51,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 337 states, 333 states have (on average 1.3513513513513513) internal successors, (450), 332 states have internal predecessors, (450), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:51,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 337 states to 337 states and 456 transitions. [2025-03-09 07:57:51,523 INFO L240 hiAutomatonCegarLoop]: Abstraction has 337 states and 456 transitions. [2025-03-09 07:57:51,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 07:57:51,524 INFO L432 stractBuchiCegarLoop]: Abstraction has 337 states and 456 transitions. [2025-03-09 07:57:51,524 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-03-09 07:57:51,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 337 states and 456 transitions. [2025-03-09 07:57:51,525 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 329 [2025-03-09 07:57:51,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:51,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:51,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:51,525 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:51,525 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:51,525 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise39#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise40#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:51,526 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:51,526 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 23 times [2025-03-09 07:57:51,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:51,526 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061649403] [2025-03-09 07:57:51,526 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 07:57:51,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:51,532 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:51,533 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:51,533 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 07:57:51,533 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:51,533 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:51,535 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:51,538 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:51,538 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:51,538 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:51,541 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:51,542 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:51,542 INFO L85 PathProgramCache]: Analyzing trace with hash -1142815036, now seen corresponding path program 1 times [2025-03-09 07:57:51,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:51,542 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001709260] [2025-03-09 07:57:51,542 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:51,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:51,563 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-09 07:57:51,590 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-09 07:57:51,590 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:51,590 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 07:57:51,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 07:57:51,856 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 07:57:51,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2001709260] [2025-03-09 07:57:51,856 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2001709260] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 07:57:51,856 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 07:57:51,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-09 07:57:51,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601563607] [2025-03-09 07:57:51,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 07:57:51,856 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 07:57:51,857 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 07:57:51,857 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-09 07:57:51,857 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-03-09 07:57:51,857 INFO L87 Difference]: Start difference. First operand 337 states and 456 transitions. cyclomatic complexity: 123 Second operand has 10 states, 10 states have (on average 7.9) internal successors, (79), 10 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 07:57:52,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 07:57:52,602 INFO L93 Difference]: Finished difference Result 349 states and 473 transitions. [2025-03-09 07:57:52,603 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 349 states and 473 transitions. [2025-03-09 07:57:52,604 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 341 [2025-03-09 07:57:52,605 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 349 states to 349 states and 473 transitions. [2025-03-09 07:57:52,605 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 349 [2025-03-09 07:57:52,605 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 349 [2025-03-09 07:57:52,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 349 states and 473 transitions. [2025-03-09 07:57:52,606 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 07:57:52,606 INFO L218 hiAutomatonCegarLoop]: Abstraction has 349 states and 473 transitions. [2025-03-09 07:57:52,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 349 states and 473 transitions. [2025-03-09 07:57:52,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 349 to 341. [2025-03-09 07:57:52,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 341 states, 337 states have (on average 1.3501483679525224) internal successors, (455), 336 states have internal predecessors, (455), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 07:57:52,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 341 states to 341 states and 461 transitions. [2025-03-09 07:57:52,611 INFO L240 hiAutomatonCegarLoop]: Abstraction has 341 states and 461 transitions. [2025-03-09 07:57:52,612 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 07:57:52,612 INFO L432 stractBuchiCegarLoop]: Abstraction has 341 states and 461 transitions. [2025-03-09 07:57:52,612 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-03-09 07:57:52,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 341 states and 461 transitions. [2025-03-09 07:57:52,613 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 333 [2025-03-09 07:57:52,613 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 07:57:52,613 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 07:57:52,613 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 07:57:52,613 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 07:57:52,613 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int_int~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset, main_#t~mem7#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~bitwise18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~switch27#1, main_#t~mem28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~bitwise39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc48#1.base, main_#t~malloc48#1.offset, main_#t~mem49#1.base, main_#t~mem49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~memset~res51#1.base, main_#t~memset~res51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~malloc57#1.base, main_#t~malloc57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~memset~res64#1.base, main_#t~memset~res64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1, main_#t~post75#1, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~mem79#1.base, main_#t~mem79#1.offset, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~post82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem87#1, main_#t~mem86#1, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1, main_#t~short90#1, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1, main_#t~malloc93#1.base, main_#t~malloc93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~mem95#1, main_#t~memset~res96#1.base, main_#t~memset~res96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem101#1, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1, main_#t~bitwise102#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem106#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1, main_#t~bitwise107#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem117#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1, main_#t~bitwise118#1, main_#t~mem119#1, main_#t~pre120#1, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~post125#1, main_#t~mem129#1, main_#t~mem127#1, main_#t~mem126#1.base, main_#t~mem126#1.offset, main_#t~mem128#1, main_#t~mem130#1, main_#t~post131#1, main_#t~mem132#1.base, main_#t~mem132#1.offset, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~post142#1, main_#t~mem143#1.base, main_#t~mem143#1.offset, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem148#1, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1, main_#t~ite151#1, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1, main_#t~mem152#1.base, main_#t~mem152#1.offset, main_#t~mem153#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post155#1, main_#t~mem156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_#t~ite160#1.base, main_#t~ite160#1.offset, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem161#1.base, main_#t~mem161#1.offset, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~short163#1, main_#t~mem164#1.base, main_#t~mem164#1.offset, main_#t~mem165#1.base, main_#t~mem165#1.offset, main_#t~mem166#1.base, main_#t~mem166#1.offset, main_#t~mem167#1.base, main_#t~mem167#1.offset, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~mem171#1.base, main_#t~mem171#1.offset, main_#t~mem172#1, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1.base, main_#t~mem175#1.offset, main_#t~mem176#1, main_#t~mem177#1.base, main_#t~mem177#1.offset, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1.base, main_#t~mem179#1.offset, main_#t~mem180#1.base, main_#t~mem180#1.offset, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~bitwise187#1, main_#t~mem188#1.base, main_#t~mem188#1.offset, main_#t~mem189#1.base, main_#t~mem189#1.offset, main_#t~mem190#1, main_#t~post191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_#t~mem193#1.base, main_#t~mem193#1.offset, main_#t~mem194#1.base, main_#t~mem194#1.offset, main_#t~mem195#1.base, main_#t~mem195#1.offset, main_#t~mem196#1.base, main_#t~mem196#1.offset, main_#t~mem197#1.base, main_#t~mem197#1.offset, main_#t~mem198#1.base, main_#t~mem198#1.offset, main_#t~mem199#1.base, main_#t~mem199#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem200#1.base, main_#t~mem200#1.offset, main_#t~mem201#1, main_#t~post202#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~ite204#1.base, main_#t~ite204#1.offset, main_#t~mem203#1.base, main_#t~mem203#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~i~0#1 := 0;" [2025-03-09 07:57:52,614 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc5#1.base, main_#t~malloc5#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc5#1.base, main_#t~malloc5#1.offset;havoc main_#t~malloc5#1.base, main_#t~malloc5#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);call write~int#1(main_~i~0#1 * main_~i~0#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch27#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch27#1;" "main_#t~switch27#1 := main_#t~switch27#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch27#1 := main_#t~switch27#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch27#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~switch27#1;havoc main_#t~mem28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise39#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise39#1;havoc main_#t~bitwise39#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise40#1;assume main_#t~bitwise40#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise43#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise46#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem65#1.base, main_#t~mem65#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem65#1.base, main_#t~mem65#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem65#1.base, main_#t~mem65#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_#t~mem66#1.base, 16 + main_#t~mem66#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1 := read~int#1(main_#t~mem68#1.base, 20 + main_#t~mem68#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset - main_#t~mem69#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1;call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem71#1.base, 8 + main_#t~mem71#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem74#1 := read~int#1(main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);main_#t~post75#1 := main_#t~mem74#1;call write~int#1(1 + main_#t~post75#1, main_#t~mem73#1.base, 12 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;havoc main_#t~mem74#1;havoc main_#t~post75#1;" "assume true;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem77#1 := read~int#1(main_#t~mem76#1.base, 4 + main_#t~mem76#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem77#1 - 1) % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise78#1;havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;havoc main_#t~mem77#1;havoc main_#t~bitwise78#1;" "assume !false;" "assume true;call main_#t~mem79#1.base, main_#t~mem79#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_#t~mem79#1.base, main_#t~mem79#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem80#1.base, main_#t~mem80#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem79#1.base, main_#t~mem79#1.offset;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;call main_#t~mem81#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post82#1 := main_#t~mem81#1;call write~int#1(1 + main_#t~post82#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem81#1;havoc main_#t~post82#1;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem83#1.base, main_#t~mem83#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem84#1.base != 0 || main_#t~mem84#1.offset != 0;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem85#1.base, 12 + main_#t~mem85#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem86#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short90#1 := main_#t~mem87#1 % 4294967296 >= 10 * (1 + main_#t~mem86#1) % 4294967296;" "assume main_#t~short90#1;call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_#t~mem88#1.base, 36 + main_#t~mem88#1.offset, 4);main_#t~short90#1 := 0 == main_#t~mem89#1 % 4294967296;" "assume !main_#t~short90#1;havoc main_#t~mem87#1;havoc main_#t~mem86#1;havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;havoc main_#t~mem89#1;havoc main_#t~short90#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post155#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post155#1;havoc main_#t~post155#1;" [2025-03-09 07:57:52,614 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:52,614 INFO L85 PathProgramCache]: Analyzing trace with hash 17312, now seen corresponding path program 24 times [2025-03-09 07:57:52,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:52,614 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498549772] [2025-03-09 07:57:52,614 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 07:57:52,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:52,619 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:52,619 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:52,619 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 07:57:52,619 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:52,619 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 07:57:52,620 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 07:57:52,621 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 07:57:52,621 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:52,621 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 07:57:52,625 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 07:57:52,625 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 07:57:52,626 INFO L85 PathProgramCache]: Analyzing trace with hash 1647613018, now seen corresponding path program 1 times [2025-03-09 07:57:52,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 07:57:52,626 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023119968] [2025-03-09 07:57:52,626 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 07:57:52,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 07:57:52,648 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-09 07:57:52,890 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-09 07:57:52,890 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 07:57:52,890 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat