./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e2fb8bed Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ff5be3465740cb655882704e7eef418c95d0bbd56a2060e741c7d3e996e58af7 --- Real Ultimate output --- This is Ultimate 0.3.0-?-e2fb8be-m [2025-03-09 08:02:42,752 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-09 08:02:42,795 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-09 08:02:42,798 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-09 08:02:42,798 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-09 08:02:42,798 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-09 08:02:42,813 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-09 08:02:42,813 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-09 08:02:42,813 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-09 08:02:42,814 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-09 08:02:42,814 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-09 08:02:42,814 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-09 08:02:42,814 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-09 08:02:42,814 INFO L153 SettingsManager]: * Use SBE=true [2025-03-09 08:02:42,814 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-09 08:02:42,814 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-09 08:02:42,814 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-09 08:02:42,814 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-09 08:02:42,815 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-09 08:02:42,815 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-09 08:02:42,815 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-09 08:02:42,815 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-09 08:02:42,815 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-09 08:02:42,815 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-09 08:02:42,815 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-09 08:02:42,815 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-09 08:02:42,815 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-09 08:02:42,815 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-09 08:02:42,815 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-09 08:02:42,816 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-09 08:02:42,816 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-09 08:02:42,816 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-09 08:02:42,816 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-09 08:02:42,816 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-09 08:02:42,816 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-09 08:02:42,816 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-09 08:02:42,816 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-09 08:02:42,816 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-09 08:02:42,816 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-09 08:02:42,817 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-09 08:02:42,817 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ff5be3465740cb655882704e7eef418c95d0bbd56a2060e741c7d3e996e58af7 [2025-03-09 08:02:43,038 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-09 08:02:43,045 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-09 08:02:43,046 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-09 08:02:43,047 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-09 08:02:43,048 INFO L274 PluginConnector]: CDTParser initialized [2025-03-09 08:02:43,049 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i [2025-03-09 08:02:44,248 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2af27caa2/f40aa5cfdc024e51a408d65c1d4fd705/FLAG0c038d887 [2025-03-09 08:02:44,594 INFO L384 CDTParser]: Found 1 translation units. [2025-03-09 08:02:44,595 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/uthash-2.0.2/uthash_SAX_test6-1.i [2025-03-09 08:02:44,617 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2af27caa2/f40aa5cfdc024e51a408d65c1d4fd705/FLAG0c038d887 [2025-03-09 08:02:44,633 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2af27caa2/f40aa5cfdc024e51a408d65c1d4fd705 [2025-03-09 08:02:44,635 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-09 08:02:44,637 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-09 08:02:44,638 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-09 08:02:44,639 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-09 08:02:44,642 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-09 08:02:44,643 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 08:02:44" (1/1) ... [2025-03-09 08:02:44,644 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2e39e824 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:44, skipping insertion in model container [2025-03-09 08:02:44,644 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 08:02:44" (1/1) ... [2025-03-09 08:02:44,688 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-09 08:02:45,097 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 08:02:45,110 INFO L200 MainTranslator]: Completed pre-run [2025-03-09 08:02:45,219 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 08:02:45,258 INFO L204 MainTranslator]: Completed translation [2025-03-09 08:02:45,258 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45 WrapperNode [2025-03-09 08:02:45,259 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-09 08:02:45,259 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-09 08:02:45,260 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-09 08:02:45,260 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-09 08:02:45,264 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45" (1/1) ... [2025-03-09 08:02:45,289 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45" (1/1) ... [2025-03-09 08:02:45,339 INFO L138 Inliner]: procedures = 282, calls = 300, calls flagged for inlining = 23, calls inlined = 33, statements flattened = 1567 [2025-03-09 08:02:45,339 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-09 08:02:45,342 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-09 08:02:45,343 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-09 08:02:45,343 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-09 08:02:45,348 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45" (1/1) ... [2025-03-09 08:02:45,349 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45" (1/1) ... [2025-03-09 08:02:45,360 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45" (1/1) ... [2025-03-09 08:02:45,426 INFO L175 MemorySlicer]: Split 274 memory accesses to 4 slices as follows [2, 17, 34, 221]. 81 percent of accesses are in the largest equivalence class. The 12 initializations are split as follows [2, 10, 0, 0]. The 57 writes are split as follows [0, 3, 4, 50]. [2025-03-09 08:02:45,427 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45" (1/1) ... [2025-03-09 08:02:45,427 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45" (1/1) ... [2025-03-09 08:02:45,459 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45" (1/1) ... [2025-03-09 08:02:45,464 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45" (1/1) ... [2025-03-09 08:02:45,472 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45" (1/1) ... [2025-03-09 08:02:45,475 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45" (1/1) ... [2025-03-09 08:02:45,489 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-09 08:02:45,489 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-09 08:02:45,490 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-09 08:02:45,490 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-09 08:02:45,491 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45" (1/1) ... [2025-03-09 08:02:45,494 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 08:02:45,504 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 08:02:45,517 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 08:02:45,520 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-09 08:02:45,537 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#0 [2025-03-09 08:02:45,538 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#1 [2025-03-09 08:02:45,538 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#2 [2025-03-09 08:02:45,538 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#3 [2025-03-09 08:02:45,538 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#0 [2025-03-09 08:02:45,538 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#1 [2025-03-09 08:02:45,538 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#2 [2025-03-09 08:02:45,539 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#3 [2025-03-09 08:02:45,539 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-03-09 08:02:45,539 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#0 [2025-03-09 08:02:45,539 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#1 [2025-03-09 08:02:45,539 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#2 [2025-03-09 08:02:45,539 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#3 [2025-03-09 08:02:45,539 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-09 08:02:45,539 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-03-09 08:02:45,540 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-03-09 08:02:45,540 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2025-03-09 08:02:45,540 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#3 [2025-03-09 08:02:45,540 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-03-09 08:02:45,540 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-03-09 08:02:45,540 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2025-03-09 08:02:45,540 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#3 [2025-03-09 08:02:45,540 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2025-03-09 08:02:45,540 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-09 08:02:45,540 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#0 [2025-03-09 08:02:45,541 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#1 [2025-03-09 08:02:45,541 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#2 [2025-03-09 08:02:45,541 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#3 [2025-03-09 08:02:45,541 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-09 08:02:45,541 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-03-09 08:02:45,541 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#2 [2025-03-09 08:02:45,541 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#3 [2025-03-09 08:02:45,541 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-09 08:02:45,542 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-09 08:02:45,738 INFO L256 CfgBuilder]: Building ICFG [2025-03-09 08:02:45,740 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-09 08:02:46,858 INFO L1307 $ProcedureCfgBuilder]: dead code at ProgramPoint L969: havoc alt_memcmp_#t~nondet36#1; [2025-03-09 08:02:46,858 INFO L1307 $ProcedureCfgBuilder]: dead code at ProgramPoint L979: havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; [2025-03-09 08:02:46,858 INFO L1307 $ProcedureCfgBuilder]: dead code at ProgramPoint L987: call ULTIMATE.dealloc(main_~#i~0#1.base, main_~#i~0#1.offset);havoc main_~#i~0#1.base, main_~#i~0#1.offset; [2025-03-09 08:02:46,858 INFO L1307 $ProcedureCfgBuilder]: dead code at ProgramPoint L955: havoc alt_malloc_#t~malloc32#1.base, alt_malloc_#t~malloc32#1.offset; [2025-03-09 08:02:46,858 INFO L1307 $ProcedureCfgBuilder]: dead code at ProgramPoint L955-3: havoc alt_malloc_#t~malloc32#1.base, alt_malloc_#t~malloc32#1.offset; [2025-03-09 08:02:46,858 INFO L1307 $ProcedureCfgBuilder]: dead code at ProgramPoint L955-6: havoc alt_malloc_#t~malloc32#1.base, alt_malloc_#t~malloc32#1.offset; [2025-03-09 08:02:46,947 INFO L? ?]: Removed 433 outVars from TransFormulas that were not future-live. [2025-03-09 08:02:46,948 INFO L307 CfgBuilder]: Performing block encoding [2025-03-09 08:02:47,009 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-09 08:02:47,010 INFO L336 CfgBuilder]: Removed 1 assume(true) statements. [2025-03-09 08:02:47,011 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 08:02:47 BoogieIcfgContainer [2025-03-09 08:02:47,011 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-09 08:02:47,012 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-09 08:02:47,012 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-09 08:02:47,016 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-09 08:02:47,016 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 08:02:47,017 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.03 08:02:44" (1/3) ... [2025-03-09 08:02:47,018 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@82cbb43 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 08:02:47, skipping insertion in model container [2025-03-09 08:02:47,018 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 08:02:47,018 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:02:45" (2/3) ... [2025-03-09 08:02:47,019 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@82cbb43 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 08:02:47, skipping insertion in model container [2025-03-09 08:02:47,019 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 08:02:47,019 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 08:02:47" (3/3) ... [2025-03-09 08:02:47,020 INFO L363 chiAutomizerObserver]: Analyzing ICFG uthash_SAX_test6-1.i [2025-03-09 08:02:47,068 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-09 08:02:47,068 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-09 08:02:47,068 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-09 08:02:47,068 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-09 08:02:47,069 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-09 08:02:47,069 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-09 08:02:47,069 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-09 08:02:47,069 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-09 08:02:47,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 449 states, 444 states have (on average 1.587837837837838) internal successors, (705), 444 states have internal predecessors, (705), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:47,099 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 426 [2025-03-09 08:02:47,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:47,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:47,107 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:47,107 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:47,107 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-09 08:02:47,108 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 449 states, 444 states have (on average 1.587837837837838) internal successors, (705), 444 states have internal predecessors, (705), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:47,121 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 426 [2025-03-09 08:02:47,121 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:47,122 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:47,122 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:47,122 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:47,126 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:02:47,126 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume !true;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:02:47,130 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:47,130 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 1 times [2025-03-09 08:02:47,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:47,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1497289545] [2025-03-09 08:02:47,135 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:47,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:47,197 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:47,220 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:47,220 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:47,221 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:47,221 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:02:47,228 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:47,238 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:47,238 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:47,238 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:47,263 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:02:47,265 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:47,265 INFO L85 PathProgramCache]: Analyzing trace with hash 402515045, now seen corresponding path program 1 times [2025-03-09 08:02:47,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:47,265 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [255936383] [2025-03-09 08:02:47,265 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:47,266 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:47,279 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-03-09 08:02:47,284 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-03-09 08:02:47,285 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:47,285 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:02:47,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:02:47,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:02:47,318 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [255936383] [2025-03-09 08:02:47,318 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [255936383] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:02:47,318 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:02:47,318 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 08:02:47,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1371963126] [2025-03-09 08:02:47,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:02:47,321 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:02:47,322 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:02:47,343 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-09 08:02:47,343 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-09 08:02:47,345 INFO L87 Difference]: Start difference. First operand has 449 states, 444 states have (on average 1.587837837837838) internal successors, (705), 444 states have internal predecessors, (705), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:02:47,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:02:47,439 INFO L93 Difference]: Finished difference Result 433 states and 609 transitions. [2025-03-09 08:02:47,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 433 states and 609 transitions. [2025-03-09 08:02:47,447 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 404 [2025-03-09 08:02:47,457 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 433 states to 411 states and 587 transitions. [2025-03-09 08:02:47,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 411 [2025-03-09 08:02:47,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 411 [2025-03-09 08:02:47,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 411 states and 587 transitions. [2025-03-09 08:02:47,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:02:47,462 INFO L218 hiAutomatonCegarLoop]: Abstraction has 411 states and 587 transitions. [2025-03-09 08:02:47,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 411 states and 587 transitions. [2025-03-09 08:02:47,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 411 to 411. [2025-03-09 08:02:47,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 411 states, 407 states have (on average 1.4275184275184276) internal successors, (581), 406 states have internal predecessors, (581), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:47,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 411 states to 411 states and 587 transitions. [2025-03-09 08:02:47,499 INFO L240 hiAutomatonCegarLoop]: Abstraction has 411 states and 587 transitions. [2025-03-09 08:02:47,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-09 08:02:47,502 INFO L432 stractBuchiCegarLoop]: Abstraction has 411 states and 587 transitions. [2025-03-09 08:02:47,503 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-09 08:02:47,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 411 states and 587 transitions. [2025-03-09 08:02:47,504 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 404 [2025-03-09 08:02:47,504 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:47,504 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:47,505 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:47,505 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:47,505 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:02:47,506 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem68#1 := read~int#3(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem68#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem69#1 := read~int#3(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem69#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem70#1 := read~int#3(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem70#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem71#1 := read~int#3(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem71#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem72#1 := read~int#3(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem72#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem73#1 := read~int#3(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + (if main_#t~mem73#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem73#1 % 256 % 4294967296 else main_#t~mem73#1 % 256 % 4294967296 - 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:02:47,507 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:47,507 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 2 times [2025-03-09 08:02:47,507 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:47,507 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [436325986] [2025-03-09 08:02:47,507 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 08:02:47,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:47,516 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:47,528 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:47,529 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:02:47,529 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:47,529 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:02:47,536 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:47,545 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:47,545 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:47,545 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:47,558 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:02:47,558 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:47,559 INFO L85 PathProgramCache]: Analyzing trace with hash 1781823943, now seen corresponding path program 1 times [2025-03-09 08:02:47,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:47,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [965083277] [2025-03-09 08:02:47,559 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:47,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:47,596 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-09 08:02:47,615 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-09 08:02:47,615 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:47,616 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:02:47,963 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:02:47,963 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:02:47,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [965083277] [2025-03-09 08:02:47,964 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [965083277] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:02:47,964 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:02:47,964 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-09 08:02:47,964 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [59210474] [2025-03-09 08:02:47,964 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:02:47,964 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:02:47,964 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:02:47,965 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-09 08:02:47,965 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-09 08:02:47,965 INFO L87 Difference]: Start difference. First operand 411 states and 587 transitions. cyclomatic complexity: 179 Second operand has 5 states, 5 states have (on average 15.0) internal successors, (75), 5 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:02:48,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:02:48,164 INFO L93 Difference]: Finished difference Result 414 states and 583 transitions. [2025-03-09 08:02:48,164 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 414 states and 583 transitions. [2025-03-09 08:02:48,166 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 407 [2025-03-09 08:02:48,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 414 states to 414 states and 583 transitions. [2025-03-09 08:02:48,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 414 [2025-03-09 08:02:48,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 414 [2025-03-09 08:02:48,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 414 states and 583 transitions. [2025-03-09 08:02:48,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:02:48,173 INFO L218 hiAutomatonCegarLoop]: Abstraction has 414 states and 583 transitions. [2025-03-09 08:02:48,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 414 states and 583 transitions. [2025-03-09 08:02:48,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 414 to 411. [2025-03-09 08:02:48,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 411 states, 407 states have (on average 1.4103194103194103) internal successors, (574), 406 states have internal predecessors, (574), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:48,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 411 states to 411 states and 580 transitions. [2025-03-09 08:02:48,185 INFO L240 hiAutomatonCegarLoop]: Abstraction has 411 states and 580 transitions. [2025-03-09 08:02:48,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-09 08:02:48,186 INFO L432 stractBuchiCegarLoop]: Abstraction has 411 states and 580 transitions. [2025-03-09 08:02:48,186 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-09 08:02:48,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 411 states and 580 transitions. [2025-03-09 08:02:48,191 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 404 [2025-03-09 08:02:48,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:48,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:48,192 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:48,192 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:48,192 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:02:48,195 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:02:48,195 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:48,195 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 3 times [2025-03-09 08:02:48,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:48,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1497376514] [2025-03-09 08:02:48,196 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 08:02:48,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:48,204 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:48,213 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:48,213 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 08:02:48,213 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:48,213 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:02:48,217 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:48,221 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:48,222 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:48,222 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:48,226 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:02:48,227 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:48,228 INFO L85 PathProgramCache]: Analyzing trace with hash -979943027, now seen corresponding path program 1 times [2025-03-09 08:02:48,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:48,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504058692] [2025-03-09 08:02:48,228 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:48,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:48,257 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-09 08:02:48,402 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-09 08:02:48,402 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:48,402 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:02:48,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:02:48,756 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:02:48,756 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1504058692] [2025-03-09 08:02:48,756 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1504058692] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:02:48,756 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:02:48,756 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-09 08:02:48,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282609710] [2025-03-09 08:02:48,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:02:48,758 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:02:48,758 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:02:48,758 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-09 08:02:48,758 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-09 08:02:48,758 INFO L87 Difference]: Start difference. First operand 411 states and 580 transitions. cyclomatic complexity: 172 Second operand has 6 states, 6 states have (on average 12.5) internal successors, (75), 6 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:02:49,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:02:49,398 INFO L93 Difference]: Finished difference Result 445 states and 624 transitions. [2025-03-09 08:02:49,398 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 445 states and 624 transitions. [2025-03-09 08:02:49,401 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 438 [2025-03-09 08:02:49,404 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 445 states to 445 states and 624 transitions. [2025-03-09 08:02:49,404 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 445 [2025-03-09 08:02:49,404 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 445 [2025-03-09 08:02:49,405 INFO L73 IsDeterministic]: Start isDeterministic. Operand 445 states and 624 transitions. [2025-03-09 08:02:49,405 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:02:49,405 INFO L218 hiAutomatonCegarLoop]: Abstraction has 445 states and 624 transitions. [2025-03-09 08:02:49,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 445 states and 624 transitions. [2025-03-09 08:02:49,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 445 to 438. [2025-03-09 08:02:49,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 438 states, 434 states have (on average 1.3986175115207373) internal successors, (607), 433 states have internal predecessors, (607), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:49,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 438 states to 438 states and 613 transitions. [2025-03-09 08:02:49,419 INFO L240 hiAutomatonCegarLoop]: Abstraction has 438 states and 613 transitions. [2025-03-09 08:02:49,419 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-09 08:02:49,420 INFO L432 stractBuchiCegarLoop]: Abstraction has 438 states and 613 transitions. [2025-03-09 08:02:49,420 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-09 08:02:49,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 438 states and 613 transitions. [2025-03-09 08:02:49,421 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 431 [2025-03-09 08:02:49,421 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:49,421 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:49,422 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:49,422 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:49,422 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:02:49,423 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:02:49,424 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:49,425 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 4 times [2025-03-09 08:02:49,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:49,427 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368235068] [2025-03-09 08:02:49,427 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 08:02:49,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:49,435 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-09 08:02:49,439 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:49,439 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 08:02:49,439 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:49,440 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:02:49,446 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:49,449 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:49,450 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:49,450 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:49,455 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:02:49,456 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:49,456 INFO L85 PathProgramCache]: Analyzing trace with hash -1500245108, now seen corresponding path program 1 times [2025-03-09 08:02:49,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:49,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539381287] [2025-03-09 08:02:49,456 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:49,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:49,483 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-09 08:02:49,515 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-09 08:02:49,515 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:49,516 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:02:49,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:02:49,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:02:49,766 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539381287] [2025-03-09 08:02:49,766 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1539381287] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:02:49,766 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:02:49,766 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-09 08:02:49,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383585494] [2025-03-09 08:02:49,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:02:49,767 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:02:49,767 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:02:49,767 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-09 08:02:49,767 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-09 08:02:49,767 INFO L87 Difference]: Start difference. First operand 438 states and 613 transitions. cyclomatic complexity: 178 Second operand has 7 states, 7 states have (on average 10.857142857142858) internal successors, (76), 7 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:02:50,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:02:50,370 INFO L93 Difference]: Finished difference Result 451 states and 632 transitions. [2025-03-09 08:02:50,370 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 451 states and 632 transitions. [2025-03-09 08:02:50,372 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 444 [2025-03-09 08:02:50,375 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 451 states to 451 states and 632 transitions. [2025-03-09 08:02:50,376 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 451 [2025-03-09 08:02:50,377 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 451 [2025-03-09 08:02:50,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 451 states and 632 transitions. [2025-03-09 08:02:50,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:02:50,378 INFO L218 hiAutomatonCegarLoop]: Abstraction has 451 states and 632 transitions. [2025-03-09 08:02:50,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states and 632 transitions. [2025-03-09 08:02:50,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 448. [2025-03-09 08:02:50,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 448 states, 444 states have (on average 1.4009009009009008) internal successors, (622), 443 states have internal predecessors, (622), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:50,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 448 states to 448 states and 628 transitions. [2025-03-09 08:02:50,386 INFO L240 hiAutomatonCegarLoop]: Abstraction has 448 states and 628 transitions. [2025-03-09 08:02:50,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-09 08:02:50,387 INFO L432 stractBuchiCegarLoop]: Abstraction has 448 states and 628 transitions. [2025-03-09 08:02:50,387 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-09 08:02:50,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 448 states and 628 transitions. [2025-03-09 08:02:50,389 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 441 [2025-03-09 08:02:50,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:50,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:50,390 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:50,390 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:50,390 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:02:50,391 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:02:50,391 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:50,391 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 5 times [2025-03-09 08:02:50,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:50,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716005933] [2025-03-09 08:02:50,392 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 08:02:50,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:50,399 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:50,401 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:50,401 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:02:50,401 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:50,401 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:02:50,404 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:50,405 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:50,405 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:50,406 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:50,409 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:02:50,410 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:50,410 INFO L85 PathProgramCache]: Analyzing trace with hash 1152282995, now seen corresponding path program 1 times [2025-03-09 08:02:50,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:50,410 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671223537] [2025-03-09 08:02:50,410 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:50,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:50,435 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-09 08:02:50,508 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-09 08:02:50,508 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:50,508 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:02:50,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:02:50,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:02:50,750 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [671223537] [2025-03-09 08:02:50,750 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [671223537] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:02:50,750 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:02:50,750 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-09 08:02:50,750 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [681312246] [2025-03-09 08:02:50,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:02:50,750 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:02:50,750 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:02:50,751 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-09 08:02:50,751 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-09 08:02:50,751 INFO L87 Difference]: Start difference. First operand 448 states and 628 transitions. cyclomatic complexity: 183 Second operand has 4 states, 4 states have (on average 19.0) internal successors, (76), 4 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:02:51,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:02:51,001 INFO L93 Difference]: Finished difference Result 451 states and 631 transitions. [2025-03-09 08:02:51,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 451 states and 631 transitions. [2025-03-09 08:02:51,003 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 444 [2025-03-09 08:02:51,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 451 states to 451 states and 631 transitions. [2025-03-09 08:02:51,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 451 [2025-03-09 08:02:51,006 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 451 [2025-03-09 08:02:51,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 451 states and 631 transitions. [2025-03-09 08:02:51,006 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:02:51,006 INFO L218 hiAutomatonCegarLoop]: Abstraction has 451 states and 631 transitions. [2025-03-09 08:02:51,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states and 631 transitions. [2025-03-09 08:02:51,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 448. [2025-03-09 08:02:51,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 448 states, 444 states have (on average 1.3986486486486487) internal successors, (621), 443 states have internal predecessors, (621), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:51,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 448 states to 448 states and 627 transitions. [2025-03-09 08:02:51,013 INFO L240 hiAutomatonCegarLoop]: Abstraction has 448 states and 627 transitions. [2025-03-09 08:02:51,013 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-09 08:02:51,013 INFO L432 stractBuchiCegarLoop]: Abstraction has 448 states and 627 transitions. [2025-03-09 08:02:51,013 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-09 08:02:51,014 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 448 states and 627 transitions. [2025-03-09 08:02:51,015 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 441 [2025-03-09 08:02:51,015 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:51,015 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:51,015 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:51,016 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:51,016 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:02:51,016 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:02:51,016 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:51,017 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 6 times [2025-03-09 08:02:51,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:51,017 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040465383] [2025-03-09 08:02:51,017 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 08:02:51,017 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:51,024 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:51,027 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:51,027 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 08:02:51,027 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:51,027 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:02:51,030 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:51,034 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:51,035 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:51,035 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:51,040 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:02:51,041 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:51,041 INFO L85 PathProgramCache]: Analyzing trace with hash 571726090, now seen corresponding path program 1 times [2025-03-09 08:02:51,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:51,041 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783667419] [2025-03-09 08:02:51,041 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:51,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:51,068 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-09 08:02:51,206 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-09 08:02:51,207 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:51,207 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:02:51,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:02:51,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:02:51,575 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1783667419] [2025-03-09 08:02:51,575 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1783667419] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:02:51,575 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:02:51,575 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2025-03-09 08:02:51,575 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [300221776] [2025-03-09 08:02:51,575 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:02:51,575 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:02:51,575 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:02:51,576 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-09 08:02:51,576 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2025-03-09 08:02:51,576 INFO L87 Difference]: Start difference. First operand 448 states and 627 transitions. cyclomatic complexity: 182 Second operand has 8 states, 8 states have (on average 9.625) internal successors, (77), 8 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:02:52,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:02:52,201 INFO L93 Difference]: Finished difference Result 458 states and 639 transitions. [2025-03-09 08:02:52,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 458 states and 639 transitions. [2025-03-09 08:02:52,203 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 451 [2025-03-09 08:02:52,205 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 458 states to 458 states and 639 transitions. [2025-03-09 08:02:52,206 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 458 [2025-03-09 08:02:52,206 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 458 [2025-03-09 08:02:52,206 INFO L73 IsDeterministic]: Start isDeterministic. Operand 458 states and 639 transitions. [2025-03-09 08:02:52,207 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:02:52,207 INFO L218 hiAutomatonCegarLoop]: Abstraction has 458 states and 639 transitions. [2025-03-09 08:02:52,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 458 states and 639 transitions. [2025-03-09 08:02:52,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 458 to 453. [2025-03-09 08:02:52,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 453 states, 449 states have (on average 1.3964365256124722) internal successors, (627), 448 states have internal predecessors, (627), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:52,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 453 states to 453 states and 633 transitions. [2025-03-09 08:02:52,212 INFO L240 hiAutomatonCegarLoop]: Abstraction has 453 states and 633 transitions. [2025-03-09 08:02:52,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-09 08:02:52,213 INFO L432 stractBuchiCegarLoop]: Abstraction has 453 states and 633 transitions. [2025-03-09 08:02:52,213 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-09 08:02:52,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 453 states and 633 transitions. [2025-03-09 08:02:52,214 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 446 [2025-03-09 08:02:52,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:52,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:52,215 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:52,215 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:52,215 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:02:52,215 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:02:52,216 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:52,216 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 7 times [2025-03-09 08:02:52,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:52,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746979273] [2025-03-09 08:02:52,216 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 08:02:52,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:52,222 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:52,224 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:52,224 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:52,224 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:52,224 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:02:52,226 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:52,228 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:52,228 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:52,228 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:52,233 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:02:52,233 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:52,233 INFO L85 PathProgramCache]: Analyzing trace with hash 908599978, now seen corresponding path program 1 times [2025-03-09 08:02:52,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:52,235 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986778814] [2025-03-09 08:02:52,235 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:52,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:52,271 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-09 08:02:52,287 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-09 08:02:52,287 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:52,287 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:02:52,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:02:52,487 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:02:52,487 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986778814] [2025-03-09 08:02:52,487 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [986778814] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:02:52,488 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:02:52,488 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-09 08:02:52,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206300983] [2025-03-09 08:02:52,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:02:52,488 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:02:52,488 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:02:52,488 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-09 08:02:52,488 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-03-09 08:02:52,488 INFO L87 Difference]: Start difference. First operand 453 states and 633 transitions. cyclomatic complexity: 183 Second operand has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 6 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:02:53,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:02:53,001 INFO L93 Difference]: Finished difference Result 456 states and 636 transitions. [2025-03-09 08:02:53,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 456 states and 636 transitions. [2025-03-09 08:02:53,004 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 449 [2025-03-09 08:02:53,006 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 456 states to 456 states and 636 transitions. [2025-03-09 08:02:53,006 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 456 [2025-03-09 08:02:53,006 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 456 [2025-03-09 08:02:53,007 INFO L73 IsDeterministic]: Start isDeterministic. Operand 456 states and 636 transitions. [2025-03-09 08:02:53,007 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:02:53,007 INFO L218 hiAutomatonCegarLoop]: Abstraction has 456 states and 636 transitions. [2025-03-09 08:02:53,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 456 states and 636 transitions. [2025-03-09 08:02:53,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 456 to 456. [2025-03-09 08:02:53,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 456 states, 452 states have (on average 1.3938053097345133) internal successors, (630), 451 states have internal predecessors, (630), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:53,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 456 states to 456 states and 636 transitions. [2025-03-09 08:02:53,017 INFO L240 hiAutomatonCegarLoop]: Abstraction has 456 states and 636 transitions. [2025-03-09 08:02:53,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-09 08:02:53,018 INFO L432 stractBuchiCegarLoop]: Abstraction has 456 states and 636 transitions. [2025-03-09 08:02:53,018 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-09 08:02:53,018 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 456 states and 636 transitions. [2025-03-09 08:02:53,019 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 449 [2025-03-09 08:02:53,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:53,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:53,020 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:53,020 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:53,020 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:02:53,020 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:02:53,021 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:53,021 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 8 times [2025-03-09 08:02:53,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:53,021 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1903765160] [2025-03-09 08:02:53,021 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 08:02:53,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:53,027 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:53,028 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:53,029 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:02:53,029 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:53,029 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:02:53,031 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:53,043 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:53,043 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:53,044 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:53,047 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:02:53,048 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:53,048 INFO L85 PathProgramCache]: Analyzing trace with hash 1513698811, now seen corresponding path program 1 times [2025-03-09 08:02:53,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:53,048 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674265199] [2025-03-09 08:02:53,048 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:53,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:53,070 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-09 08:02:53,172 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-09 08:02:53,172 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:53,172 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:02:53,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:02:53,656 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:02:53,656 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [674265199] [2025-03-09 08:02:53,656 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [674265199] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:02:53,656 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:02:53,656 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-09 08:02:53,656 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [740895603] [2025-03-09 08:02:53,656 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:02:53,656 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:02:53,656 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:02:53,657 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-09 08:02:53,657 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-09 08:02:53,657 INFO L87 Difference]: Start difference. First operand 456 states and 636 transitions. cyclomatic complexity: 183 Second operand has 13 states, 13 states have (on average 6.0) internal successors, (78), 13 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:02:55,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:02:55,262 INFO L93 Difference]: Finished difference Result 567 states and 792 transitions. [2025-03-09 08:02:55,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 567 states and 792 transitions. [2025-03-09 08:02:55,265 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 560 [2025-03-09 08:02:55,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 567 states to 567 states and 792 transitions. [2025-03-09 08:02:55,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 567 [2025-03-09 08:02:55,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 567 [2025-03-09 08:02:55,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 567 states and 792 transitions. [2025-03-09 08:02:55,268 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:02:55,268 INFO L218 hiAutomatonCegarLoop]: Abstraction has 567 states and 792 transitions. [2025-03-09 08:02:55,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states and 792 transitions. [2025-03-09 08:02:55,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 465. [2025-03-09 08:02:55,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 465 states, 461 states have (on average 1.3926247288503253) internal successors, (642), 460 states have internal predecessors, (642), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:55,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 465 states to 465 states and 648 transitions. [2025-03-09 08:02:55,275 INFO L240 hiAutomatonCegarLoop]: Abstraction has 465 states and 648 transitions. [2025-03-09 08:02:55,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-09 08:02:55,278 INFO L432 stractBuchiCegarLoop]: Abstraction has 465 states and 648 transitions. [2025-03-09 08:02:55,278 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-09 08:02:55,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 465 states and 648 transitions. [2025-03-09 08:02:55,280 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 458 [2025-03-09 08:02:55,280 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:55,280 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:55,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:55,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:55,281 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:02:55,281 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:02:55,282 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:55,282 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 9 times [2025-03-09 08:02:55,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:55,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405434480] [2025-03-09 08:02:55,282 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 08:02:55,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:55,288 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:55,290 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:55,291 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 08:02:55,291 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:55,291 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:02:55,293 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:55,294 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:55,294 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:55,294 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:55,299 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:02:55,300 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:55,300 INFO L85 PathProgramCache]: Analyzing trace with hash 700987817, now seen corresponding path program 1 times [2025-03-09 08:02:55,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:55,300 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966277488] [2025-03-09 08:02:55,300 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:55,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:55,324 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-09 08:02:55,364 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-09 08:02:55,364 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:55,364 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:02:55,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:02:55,529 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:02:55,529 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1966277488] [2025-03-09 08:02:55,529 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1966277488] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:02:55,529 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:02:55,529 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-09 08:02:55,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171426651] [2025-03-09 08:02:55,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:02:55,530 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:02:55,530 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:02:55,530 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-09 08:02:55,530 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-09 08:02:55,530 INFO L87 Difference]: Start difference. First operand 465 states and 648 transitions. cyclomatic complexity: 186 Second operand has 7 states, 7 states have (on average 11.142857142857142) internal successors, (78), 7 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:02:56,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:02:56,125 INFO L93 Difference]: Finished difference Result 472 states and 657 transitions. [2025-03-09 08:02:56,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 472 states and 657 transitions. [2025-03-09 08:02:56,127 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 465 [2025-03-09 08:02:56,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 472 states to 472 states and 657 transitions. [2025-03-09 08:02:56,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 472 [2025-03-09 08:02:56,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 472 [2025-03-09 08:02:56,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 472 states and 657 transitions. [2025-03-09 08:02:56,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:02:56,130 INFO L218 hiAutomatonCegarLoop]: Abstraction has 472 states and 657 transitions. [2025-03-09 08:02:56,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 472 states and 657 transitions. [2025-03-09 08:02:56,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 472 to 465. [2025-03-09 08:02:56,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 465 states, 461 states have (on average 1.3926247288503253) internal successors, (642), 460 states have internal predecessors, (642), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:56,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 465 states to 465 states and 648 transitions. [2025-03-09 08:02:56,136 INFO L240 hiAutomatonCegarLoop]: Abstraction has 465 states and 648 transitions. [2025-03-09 08:02:56,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-09 08:02:56,138 INFO L432 stractBuchiCegarLoop]: Abstraction has 465 states and 648 transitions. [2025-03-09 08:02:56,138 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-09 08:02:56,138 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 465 states and 648 transitions. [2025-03-09 08:02:56,139 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 458 [2025-03-09 08:02:56,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:56,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:56,140 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:56,140 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:56,140 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:02:56,140 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:02:56,140 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:56,140 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 10 times [2025-03-09 08:02:56,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:56,141 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137317971] [2025-03-09 08:02:56,141 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 08:02:56,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:56,146 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-09 08:02:56,149 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:56,149 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 08:02:56,149 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:56,150 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:02:56,151 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:56,153 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:56,153 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:56,153 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:56,156 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:02:56,157 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:56,157 INFO L85 PathProgramCache]: Analyzing trace with hash 1351860232, now seen corresponding path program 1 times [2025-03-09 08:02:56,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:56,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192980039] [2025-03-09 08:02:56,158 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:56,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:56,182 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-09 08:02:56,198 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-09 08:02:56,198 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:56,198 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:02:56,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:02:56,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:02:56,470 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192980039] [2025-03-09 08:02:56,470 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192980039] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:02:56,470 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:02:56,471 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 08:02:56,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [979407671] [2025-03-09 08:02:56,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:02:56,471 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:02:56,471 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:02:56,471 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 08:02:56,471 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-09 08:02:56,471 INFO L87 Difference]: Start difference. First operand 465 states and 648 transitions. cyclomatic complexity: 186 Second operand has 9 states, 9 states have (on average 8.666666666666666) internal successors, (78), 9 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:02:57,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:02:57,278 INFO L93 Difference]: Finished difference Result 476 states and 663 transitions. [2025-03-09 08:02:57,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 476 states and 663 transitions. [2025-03-09 08:02:57,280 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 469 [2025-03-09 08:02:57,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 476 states to 476 states and 663 transitions. [2025-03-09 08:02:57,282 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 476 [2025-03-09 08:02:57,282 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 476 [2025-03-09 08:02:57,283 INFO L73 IsDeterministic]: Start isDeterministic. Operand 476 states and 663 transitions. [2025-03-09 08:02:57,283 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:02:57,283 INFO L218 hiAutomatonCegarLoop]: Abstraction has 476 states and 663 transitions. [2025-03-09 08:02:57,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 476 states and 663 transitions. [2025-03-09 08:02:57,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 476 to 470. [2025-03-09 08:02:57,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 470 states, 466 states have (on average 1.3927038626609443) internal successors, (649), 465 states have internal predecessors, (649), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:57,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 655 transitions. [2025-03-09 08:02:57,288 INFO L240 hiAutomatonCegarLoop]: Abstraction has 470 states and 655 transitions. [2025-03-09 08:02:57,289 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-09 08:02:57,289 INFO L432 stractBuchiCegarLoop]: Abstraction has 470 states and 655 transitions. [2025-03-09 08:02:57,289 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-09 08:02:57,289 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 470 states and 655 transitions. [2025-03-09 08:02:57,290 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 463 [2025-03-09 08:02:57,291 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:57,291 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:57,291 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:57,291 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:57,291 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:02:57,292 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 32 % 4294967296;main_#t~bitwise83#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:02:57,292 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:57,292 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 11 times [2025-03-09 08:02:57,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:57,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410172610] [2025-03-09 08:02:57,292 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 08:02:57,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:57,298 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:57,299 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:57,300 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:02:57,300 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:57,300 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:02:57,302 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:57,307 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:57,307 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:57,307 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:57,311 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:02:57,312 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:57,312 INFO L85 PathProgramCache]: Analyzing trace with hash -1309946942, now seen corresponding path program 1 times [2025-03-09 08:02:57,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:57,312 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108816743] [2025-03-09 08:02:57,312 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:57,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:57,335 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-09 08:02:57,398 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-09 08:02:57,398 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:57,398 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:02:57,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:02:57,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:02:57,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2108816743] [2025-03-09 08:02:57,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2108816743] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:02:57,996 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:02:57,996 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 08:02:57,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [814788818] [2025-03-09 08:02:57,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:02:57,996 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:02:57,996 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:02:57,997 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 08:02:57,997 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2025-03-09 08:02:57,997 INFO L87 Difference]: Start difference. First operand 470 states and 655 transitions. cyclomatic complexity: 188 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:02:58,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:02:58,681 INFO L93 Difference]: Finished difference Result 466 states and 649 transitions. [2025-03-09 08:02:58,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 466 states and 649 transitions. [2025-03-09 08:02:58,683 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 459 [2025-03-09 08:02:58,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 466 states to 466 states and 649 transitions. [2025-03-09 08:02:58,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 466 [2025-03-09 08:02:58,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 466 [2025-03-09 08:02:58,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 466 states and 649 transitions. [2025-03-09 08:02:58,687 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:02:58,687 INFO L218 hiAutomatonCegarLoop]: Abstraction has 466 states and 649 transitions. [2025-03-09 08:02:58,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states and 649 transitions. [2025-03-09 08:02:58,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 464. [2025-03-09 08:02:58,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 464 states, 460 states have (on average 1.391304347826087) internal successors, (640), 459 states have internal predecessors, (640), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:58,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 646 transitions. [2025-03-09 08:02:58,693 INFO L240 hiAutomatonCegarLoop]: Abstraction has 464 states and 646 transitions. [2025-03-09 08:02:58,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-09 08:02:58,694 INFO L432 stractBuchiCegarLoop]: Abstraction has 464 states and 646 transitions. [2025-03-09 08:02:58,695 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-09 08:02:58,695 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 464 states and 646 transitions. [2025-03-09 08:02:58,696 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 457 [2025-03-09 08:02:58,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:58,696 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:58,697 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:58,697 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:58,697 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:02:58,697 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:02:58,697 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:58,698 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 12 times [2025-03-09 08:02:58,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:58,698 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101075612] [2025-03-09 08:02:58,698 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 08:02:58,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:58,704 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:58,705 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:58,706 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 08:02:58,706 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:58,706 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:02:58,708 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:58,709 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:58,709 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:58,709 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:58,714 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:02:58,714 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:58,714 INFO L85 PathProgramCache]: Analyzing trace with hash 63262563, now seen corresponding path program 1 times [2025-03-09 08:02:58,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:58,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094872748] [2025-03-09 08:02:58,714 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:58,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:58,737 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-09 08:02:58,785 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-09 08:02:58,785 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:58,785 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:02:58,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:02:58,963 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:02:58,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1094872748] [2025-03-09 08:02:58,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1094872748] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:02:58,963 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:02:58,963 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-09 08:02:58,963 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1506675812] [2025-03-09 08:02:58,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:02:58,963 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:02:58,963 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:02:58,964 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-09 08:02:58,964 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-03-09 08:02:58,964 INFO L87 Difference]: Start difference. First operand 464 states and 646 transitions. cyclomatic complexity: 185 Second operand has 6 states, 6 states have (on average 13.166666666666666) internal successors, (79), 6 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:02:59,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:02:59,432 INFO L93 Difference]: Finished difference Result 461 states and 642 transitions. [2025-03-09 08:02:59,432 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 461 states and 642 transitions. [2025-03-09 08:02:59,434 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 454 [2025-03-09 08:02:59,436 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 461 states to 461 states and 642 transitions. [2025-03-09 08:02:59,436 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 461 [2025-03-09 08:02:59,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 461 [2025-03-09 08:02:59,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 461 states and 642 transitions. [2025-03-09 08:02:59,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:02:59,437 INFO L218 hiAutomatonCegarLoop]: Abstraction has 461 states and 642 transitions. [2025-03-09 08:02:59,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 461 states and 642 transitions. [2025-03-09 08:02:59,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 461 to 461. [2025-03-09 08:02:59,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 461 states, 457 states have (on average 1.3916849015317287) internal successors, (636), 456 states have internal predecessors, (636), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:02:59,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 642 transitions. [2025-03-09 08:02:59,442 INFO L240 hiAutomatonCegarLoop]: Abstraction has 461 states and 642 transitions. [2025-03-09 08:02:59,443 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-09 08:02:59,443 INFO L432 stractBuchiCegarLoop]: Abstraction has 461 states and 642 transitions. [2025-03-09 08:02:59,443 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-09 08:02:59,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 461 states and 642 transitions. [2025-03-09 08:02:59,445 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 454 [2025-03-09 08:02:59,445 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:02:59,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:02:59,446 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:02:59,446 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:02:59,446 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:02:59,446 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:02:59,446 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:59,446 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 13 times [2025-03-09 08:02:59,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:59,446 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127110573] [2025-03-09 08:02:59,447 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 08:02:59,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:59,454 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:59,455 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:59,455 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:59,455 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:59,455 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:02:59,457 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:02:59,458 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:02:59,458 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:59,458 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:02:59,463 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:02:59,463 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:02:59,463 INFO L85 PathProgramCache]: Analyzing trace with hash -336075869, now seen corresponding path program 1 times [2025-03-09 08:02:59,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:02:59,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1365818112] [2025-03-09 08:02:59,464 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:02:59,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:02:59,488 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-09 08:02:59,501 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-09 08:02:59,501 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:02:59,502 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:02:59,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:02:59,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:02:59,673 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1365818112] [2025-03-09 08:02:59,673 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1365818112] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:02:59,673 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:02:59,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 08:02:59,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [457763711] [2025-03-09 08:02:59,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:02:59,674 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:02:59,674 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:02:59,674 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 08:02:59,674 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2025-03-09 08:02:59,674 INFO L87 Difference]: Start difference. First operand 461 states and 642 transitions. cyclomatic complexity: 184 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:03:00,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:03:00,363 INFO L93 Difference]: Finished difference Result 474 states and 658 transitions. [2025-03-09 08:03:00,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 474 states and 658 transitions. [2025-03-09 08:03:00,365 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 467 [2025-03-09 08:03:00,366 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 474 states to 474 states and 658 transitions. [2025-03-09 08:03:00,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 474 [2025-03-09 08:03:00,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 474 [2025-03-09 08:03:00,367 INFO L73 IsDeterministic]: Start isDeterministic. Operand 474 states and 658 transitions. [2025-03-09 08:03:00,368 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:03:00,368 INFO L218 hiAutomatonCegarLoop]: Abstraction has 474 states and 658 transitions. [2025-03-09 08:03:00,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 474 states and 658 transitions. [2025-03-09 08:03:00,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 474 to 464. [2025-03-09 08:03:00,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 464 states, 460 states have (on average 1.391304347826087) internal successors, (640), 459 states have internal predecessors, (640), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:03:00,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 646 transitions. [2025-03-09 08:03:00,373 INFO L240 hiAutomatonCegarLoop]: Abstraction has 464 states and 646 transitions. [2025-03-09 08:03:00,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-09 08:03:00,375 INFO L432 stractBuchiCegarLoop]: Abstraction has 464 states and 646 transitions. [2025-03-09 08:03:00,375 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-09 08:03:00,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 464 states and 646 transitions. [2025-03-09 08:03:00,376 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 457 [2025-03-09 08:03:00,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:03:00,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:03:00,376 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:03:00,377 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:03:00,377 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:03:00,377 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:03:00,377 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:00,377 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 14 times [2025-03-09 08:03:00,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:00,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795990147] [2025-03-09 08:03:00,377 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 08:03:00,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:00,384 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:00,386 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:00,386 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:03:00,386 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:00,386 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:03:00,388 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:00,389 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:00,389 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:00,389 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:00,394 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:03:00,395 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:00,395 INFO L85 PathProgramCache]: Analyzing trace with hash 1064006473, now seen corresponding path program 1 times [2025-03-09 08:03:00,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:00,395 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2110366736] [2025-03-09 08:03:00,395 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:03:00,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:00,444 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-09 08:03:00,485 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-09 08:03:00,486 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:00,486 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:03:00,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:03:00,655 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:03:00,655 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2110366736] [2025-03-09 08:03:00,655 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2110366736] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:03:00,655 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:03:00,655 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 08:03:00,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [800937211] [2025-03-09 08:03:00,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:03:00,656 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:03:00,656 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:03:00,656 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 08:03:00,656 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-09 08:03:00,656 INFO L87 Difference]: Start difference. First operand 464 states and 646 transitions. cyclomatic complexity: 185 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:03:01,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:03:01,371 INFO L93 Difference]: Finished difference Result 484 states and 672 transitions. [2025-03-09 08:03:01,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 484 states and 672 transitions. [2025-03-09 08:03:01,376 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 477 [2025-03-09 08:03:01,377 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 484 states to 484 states and 672 transitions. [2025-03-09 08:03:01,377 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 484 [2025-03-09 08:03:01,378 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 484 [2025-03-09 08:03:01,378 INFO L73 IsDeterministic]: Start isDeterministic. Operand 484 states and 672 transitions. [2025-03-09 08:03:01,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:03:01,378 INFO L218 hiAutomatonCegarLoop]: Abstraction has 484 states and 672 transitions. [2025-03-09 08:03:01,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 484 states and 672 transitions. [2025-03-09 08:03:01,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 484 to 464. [2025-03-09 08:03:01,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 464 states, 460 states have (on average 1.391304347826087) internal successors, (640), 459 states have internal predecessors, (640), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:03:01,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 646 transitions. [2025-03-09 08:03:01,384 INFO L240 hiAutomatonCegarLoop]: Abstraction has 464 states and 646 transitions. [2025-03-09 08:03:01,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:03:01,385 INFO L432 stractBuchiCegarLoop]: Abstraction has 464 states and 646 transitions. [2025-03-09 08:03:01,385 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-09 08:03:01,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 464 states and 646 transitions. [2025-03-09 08:03:01,386 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 457 [2025-03-09 08:03:01,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:03:01,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:03:01,387 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:03:01,387 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:03:01,387 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:03:01,387 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:03:01,388 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:01,388 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 15 times [2025-03-09 08:03:01,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:01,388 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181892280] [2025-03-09 08:03:01,388 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 08:03:01,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:01,394 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:01,396 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:01,396 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 08:03:01,396 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:01,396 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:03:01,398 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:01,400 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:01,400 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:01,400 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:01,405 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:03:01,405 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:01,405 INFO L85 PathProgramCache]: Analyzing trace with hash -939052012, now seen corresponding path program 1 times [2025-03-09 08:03:01,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:01,406 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [399028739] [2025-03-09 08:03:01,406 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:03:01,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:01,446 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:03:01,511 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:03:01,511 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:01,512 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:03:01,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:03:01,858 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:03:01,858 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [399028739] [2025-03-09 08:03:01,858 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [399028739] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:03:01,858 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:03:01,858 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 08:03:01,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972769400] [2025-03-09 08:03:01,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:03:01,858 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:03:01,858 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:03:01,858 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 08:03:01,858 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-09 08:03:01,858 INFO L87 Difference]: Start difference. First operand 464 states and 646 transitions. cyclomatic complexity: 185 Second operand has 9 states, 9 states have (on average 8.88888888888889) internal successors, (80), 9 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:03:02,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:03:02,656 INFO L93 Difference]: Finished difference Result 475 states and 659 transitions. [2025-03-09 08:03:02,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 475 states and 659 transitions. [2025-03-09 08:03:02,658 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 468 [2025-03-09 08:03:02,660 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 475 states to 475 states and 659 transitions. [2025-03-09 08:03:02,660 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 475 [2025-03-09 08:03:02,660 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 475 [2025-03-09 08:03:02,660 INFO L73 IsDeterministic]: Start isDeterministic. Operand 475 states and 659 transitions. [2025-03-09 08:03:02,661 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:03:02,661 INFO L218 hiAutomatonCegarLoop]: Abstraction has 475 states and 659 transitions. [2025-03-09 08:03:02,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 475 states and 659 transitions. [2025-03-09 08:03:02,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 475 to 467. [2025-03-09 08:03:02,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 467 states, 463 states have (on average 1.388768898488121) internal successors, (643), 462 states have internal predecessors, (643), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:03:02,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 467 states to 467 states and 649 transitions. [2025-03-09 08:03:02,667 INFO L240 hiAutomatonCegarLoop]: Abstraction has 467 states and 649 transitions. [2025-03-09 08:03:02,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:03:02,670 INFO L432 stractBuchiCegarLoop]: Abstraction has 467 states and 649 transitions. [2025-03-09 08:03:02,670 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-09 08:03:02,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 467 states and 649 transitions. [2025-03-09 08:03:02,671 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 460 [2025-03-09 08:03:02,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:03:02,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:03:02,671 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:03:02,671 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:03:02,671 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:03:02,672 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:03:02,672 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:02,672 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 16 times [2025-03-09 08:03:02,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:02,672 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125757041] [2025-03-09 08:03:02,672 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 08:03:02,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:02,679 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-09 08:03:02,681 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:02,681 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 08:03:02,681 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:02,681 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:03:02,683 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:02,685 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:02,686 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:02,686 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:02,690 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:03:02,690 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:02,690 INFO L85 PathProgramCache]: Analyzing trace with hash -723149016, now seen corresponding path program 1 times [2025-03-09 08:03:02,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:02,690 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020255523] [2025-03-09 08:03:02,690 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:03:02,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:02,712 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:03:02,726 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:03:02,726 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:02,726 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:03:02,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:03:02,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:03:02,944 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2020255523] [2025-03-09 08:03:02,944 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2020255523] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:03:02,944 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:03:02,944 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-09 08:03:02,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [126436981] [2025-03-09 08:03:02,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:03:02,944 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:03:02,944 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:03:02,944 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-09 08:03:02,945 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2025-03-09 08:03:02,945 INFO L87 Difference]: Start difference. First operand 467 states and 649 transitions. cyclomatic complexity: 185 Second operand has 10 states, 10 states have (on average 8.0) internal successors, (80), 10 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:03:03,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:03:03,774 INFO L93 Difference]: Finished difference Result 483 states and 670 transitions. [2025-03-09 08:03:03,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 483 states and 670 transitions. [2025-03-09 08:03:03,777 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 476 [2025-03-09 08:03:03,780 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 483 states to 483 states and 670 transitions. [2025-03-09 08:03:03,782 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 483 [2025-03-09 08:03:03,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 483 [2025-03-09 08:03:03,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 483 states and 670 transitions. [2025-03-09 08:03:03,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:03:03,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 483 states and 670 transitions. [2025-03-09 08:03:03,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 483 states and 670 transitions. [2025-03-09 08:03:03,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 483 to 477. [2025-03-09 08:03:03,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 477 states, 473 states have (on average 1.3847780126849893) internal successors, (655), 472 states have internal predecessors, (655), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:03:03,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 477 states and 661 transitions. [2025-03-09 08:03:03,791 INFO L240 hiAutomatonCegarLoop]: Abstraction has 477 states and 661 transitions. [2025-03-09 08:03:03,791 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:03:03,791 INFO L432 stractBuchiCegarLoop]: Abstraction has 477 states and 661 transitions. [2025-03-09 08:03:03,791 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-09 08:03:03,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 477 states and 661 transitions. [2025-03-09 08:03:03,793 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 470 [2025-03-09 08:03:03,793 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:03:03,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:03:03,793 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:03:03,794 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:03:03,794 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:03:03,796 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:03:03,796 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:03,797 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 17 times [2025-03-09 08:03:03,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:03,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [494436357] [2025-03-09 08:03:03,797 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 08:03:03,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:03,802 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:03,804 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:03,804 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:03:03,804 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:03,804 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:03:03,805 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:03,806 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:03,807 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:03,807 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:03,812 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:03:03,812 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:03,812 INFO L85 PathProgramCache]: Analyzing trace with hash -198166440, now seen corresponding path program 1 times [2025-03-09 08:03:03,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:03,813 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369950614] [2025-03-09 08:03:03,813 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:03:03,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:03,856 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:03:03,970 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:03:03,971 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:03,971 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:03:04,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:03:04,393 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:03:04,393 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [369950614] [2025-03-09 08:03:04,393 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [369950614] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:03:04,393 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:03:04,393 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-09 08:03:04,393 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [423294446] [2025-03-09 08:03:04,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:03:04,393 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:03:04,393 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:03:04,393 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-09 08:03:04,393 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2025-03-09 08:03:04,393 INFO L87 Difference]: Start difference. First operand 477 states and 661 transitions. cyclomatic complexity: 187 Second operand has 13 states, 13 states have (on average 6.153846153846154) internal successors, (80), 13 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:03:05,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:03:05,183 INFO L93 Difference]: Finished difference Result 532 states and 742 transitions. [2025-03-09 08:03:05,183 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 742 transitions. [2025-03-09 08:03:05,185 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 525 [2025-03-09 08:03:05,186 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 742 transitions. [2025-03-09 08:03:05,186 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2025-03-09 08:03:05,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2025-03-09 08:03:05,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 742 transitions. [2025-03-09 08:03:05,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:03:05,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 532 states and 742 transitions. [2025-03-09 08:03:05,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 742 transitions. [2025-03-09 08:03:05,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 485. [2025-03-09 08:03:05,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 485 states, 481 states have (on average 1.3846153846153846) internal successors, (666), 480 states have internal predecessors, (666), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:03:05,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 485 states to 485 states and 672 transitions. [2025-03-09 08:03:05,193 INFO L240 hiAutomatonCegarLoop]: Abstraction has 485 states and 672 transitions. [2025-03-09 08:03:05,193 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-09 08:03:05,194 INFO L432 stractBuchiCegarLoop]: Abstraction has 485 states and 672 transitions. [2025-03-09 08:03:05,194 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-09 08:03:05,194 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 485 states and 672 transitions. [2025-03-09 08:03:05,195 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 478 [2025-03-09 08:03:05,195 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:03:05,195 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:03:05,196 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:03:05,196 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:03:05,196 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:03:05,196 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:03:05,197 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:05,197 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 18 times [2025-03-09 08:03:05,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:05,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935049361] [2025-03-09 08:03:05,197 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 08:03:05,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:05,202 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:05,204 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:05,204 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 08:03:05,204 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:05,204 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:03:05,205 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:05,208 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:05,208 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:05,208 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:05,212 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:03:05,213 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:05,213 INFO L85 PathProgramCache]: Analyzing trace with hash -270269374, now seen corresponding path program 1 times [2025-03-09 08:03:05,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:05,213 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082796665] [2025-03-09 08:03:05,213 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:03:05,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:05,238 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:03:05,274 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:03:05,274 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:05,274 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:03:05,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:03:05,521 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:03:05,521 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1082796665] [2025-03-09 08:03:05,522 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1082796665] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:03:05,522 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:03:05,522 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-09 08:03:05,522 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1124401130] [2025-03-09 08:03:05,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:03:05,522 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:03:05,522 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:03:05,522 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-09 08:03:05,522 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2025-03-09 08:03:05,523 INFO L87 Difference]: Start difference. First operand 485 states and 672 transitions. cyclomatic complexity: 190 Second operand has 10 states, 10 states have (on average 8.0) internal successors, (80), 10 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:03:06,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:03:06,404 INFO L93 Difference]: Finished difference Result 500 states and 693 transitions. [2025-03-09 08:03:06,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 500 states and 693 transitions. [2025-03-09 08:03:06,406 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 493 [2025-03-09 08:03:06,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 500 states to 500 states and 693 transitions. [2025-03-09 08:03:06,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 500 [2025-03-09 08:03:06,408 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 500 [2025-03-09 08:03:06,408 INFO L73 IsDeterministic]: Start isDeterministic. Operand 500 states and 693 transitions. [2025-03-09 08:03:06,408 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:03:06,408 INFO L218 hiAutomatonCegarLoop]: Abstraction has 500 states and 693 transitions. [2025-03-09 08:03:06,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 500 states and 693 transitions. [2025-03-09 08:03:06,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 500 to 485. [2025-03-09 08:03:06,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 485 states, 481 states have (on average 1.3846153846153846) internal successors, (666), 480 states have internal predecessors, (666), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:03:06,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 485 states to 485 states and 672 transitions. [2025-03-09 08:03:06,414 INFO L240 hiAutomatonCegarLoop]: Abstraction has 485 states and 672 transitions. [2025-03-09 08:03:06,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:03:06,415 INFO L432 stractBuchiCegarLoop]: Abstraction has 485 states and 672 transitions. [2025-03-09 08:03:06,415 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-09 08:03:06,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 485 states and 672 transitions. [2025-03-09 08:03:06,417 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 478 [2025-03-09 08:03:06,417 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:03:06,417 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:03:06,418 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:03:06,418 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:03:06,418 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:03:06,418 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:03:06,419 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:06,419 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 19 times [2025-03-09 08:03:06,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:06,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1358548405] [2025-03-09 08:03:06,419 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 08:03:06,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:06,426 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:06,427 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:06,427 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:06,427 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:06,428 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:03:06,429 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:06,430 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:06,430 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:06,431 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:06,435 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:03:06,436 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:06,436 INFO L85 PathProgramCache]: Analyzing trace with hash 1038563878, now seen corresponding path program 1 times [2025-03-09 08:03:06,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:06,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316835337] [2025-03-09 08:03:06,437 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:03:06,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:06,459 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:03:06,492 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:03:06,492 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:06,492 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:03:06,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:03:06,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:03:06,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1316835337] [2025-03-09 08:03:06,625 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1316835337] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:03:06,625 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:03:06,625 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-09 08:03:06,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1002184241] [2025-03-09 08:03:06,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:03:06,625 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:03:06,625 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:03:06,626 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-09 08:03:06,626 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-09 08:03:06,626 INFO L87 Difference]: Start difference. First operand 485 states and 672 transitions. cyclomatic complexity: 190 Second operand has 7 states, 7 states have (on average 11.428571428571429) internal successors, (80), 7 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:03:07,185 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:03:07,186 INFO L93 Difference]: Finished difference Result 490 states and 678 transitions. [2025-03-09 08:03:07,186 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 490 states and 678 transitions. [2025-03-09 08:03:07,187 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 483 [2025-03-09 08:03:07,189 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 490 states to 490 states and 678 transitions. [2025-03-09 08:03:07,189 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 490 [2025-03-09 08:03:07,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 490 [2025-03-09 08:03:07,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 490 states and 678 transitions. [2025-03-09 08:03:07,190 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:03:07,190 INFO L218 hiAutomatonCegarLoop]: Abstraction has 490 states and 678 transitions. [2025-03-09 08:03:07,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 490 states and 678 transitions. [2025-03-09 08:03:07,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 490 to 489. [2025-03-09 08:03:07,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 489 states, 485 states have (on average 1.3835051546391752) internal successors, (671), 484 states have internal predecessors, (671), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:03:07,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 489 states to 489 states and 677 transitions. [2025-03-09 08:03:07,197 INFO L240 hiAutomatonCegarLoop]: Abstraction has 489 states and 677 transitions. [2025-03-09 08:03:07,199 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-09 08:03:07,199 INFO L432 stractBuchiCegarLoop]: Abstraction has 489 states and 677 transitions. [2025-03-09 08:03:07,199 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-09 08:03:07,199 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 489 states and 677 transitions. [2025-03-09 08:03:07,201 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 482 [2025-03-09 08:03:07,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:03:07,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:03:07,201 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:03:07,201 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:03:07,201 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:03:07,202 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:03:07,202 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:07,202 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 20 times [2025-03-09 08:03:07,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:07,202 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759443220] [2025-03-09 08:03:07,202 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 08:03:07,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:07,210 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:07,211 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:07,211 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:03:07,211 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:07,211 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:03:07,213 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:07,214 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:07,214 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:07,214 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:07,225 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:03:07,225 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:07,226 INFO L85 PathProgramCache]: Analyzing trace with hash 2012100322, now seen corresponding path program 1 times [2025-03-09 08:03:07,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:07,226 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248632239] [2025-03-09 08:03:07,226 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:03:07,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:07,254 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:03:07,302 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:03:07,303 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:07,303 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:03:07,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:03:07,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:03:07,496 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248632239] [2025-03-09 08:03:07,496 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248632239] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:03:07,496 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:03:07,496 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-09 08:03:07,496 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1368326591] [2025-03-09 08:03:07,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:03:07,497 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:03:07,497 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:03:07,498 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-09 08:03:07,498 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-09 08:03:07,498 INFO L87 Difference]: Start difference. First operand 489 states and 677 transitions. cyclomatic complexity: 191 Second operand has 7 states, 7 states have (on average 11.428571428571429) internal successors, (80), 7 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:03:08,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:03:08,085 INFO L93 Difference]: Finished difference Result 495 states and 682 transitions. [2025-03-09 08:03:08,085 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 495 states and 682 transitions. [2025-03-09 08:03:08,087 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 488 [2025-03-09 08:03:08,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 495 states to 495 states and 682 transitions. [2025-03-09 08:03:08,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 495 [2025-03-09 08:03:08,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 495 [2025-03-09 08:03:08,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 495 states and 682 transitions. [2025-03-09 08:03:08,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:03:08,089 INFO L218 hiAutomatonCegarLoop]: Abstraction has 495 states and 682 transitions. [2025-03-09 08:03:08,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 495 states and 682 transitions. [2025-03-09 08:03:08,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 495 to 489. [2025-03-09 08:03:08,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 489 states, 485 states have (on average 1.3814432989690721) internal successors, (670), 484 states have internal predecessors, (670), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:03:08,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 489 states to 489 states and 676 transitions. [2025-03-09 08:03:08,094 INFO L240 hiAutomatonCegarLoop]: Abstraction has 489 states and 676 transitions. [2025-03-09 08:03:08,094 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-09 08:03:08,094 INFO L432 stractBuchiCegarLoop]: Abstraction has 489 states and 676 transitions. [2025-03-09 08:03:08,094 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-03-09 08:03:08,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 489 states and 676 transitions. [2025-03-09 08:03:08,095 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 482 [2025-03-09 08:03:08,095 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:03:08,095 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:03:08,096 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:03:08,096 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:03:08,096 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:03:08,097 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise80#1;assume main_#t~bitwise80#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:03:08,097 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:08,098 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 21 times [2025-03-09 08:03:08,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:08,098 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101001359] [2025-03-09 08:03:08,098 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 08:03:08,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:08,103 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:08,105 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:08,105 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 08:03:08,105 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:08,106 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:03:08,108 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:08,108 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:08,109 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:08,109 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:08,113 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:03:08,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:08,113 INFO L85 PathProgramCache]: Analyzing trace with hash 755482302, now seen corresponding path program 1 times [2025-03-09 08:03:08,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:08,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277607633] [2025-03-09 08:03:08,114 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:03:08,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:08,136 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-09 08:03:08,289 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-09 08:03:08,290 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:08,290 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:03:08,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:03:08,771 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:03:08,771 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277607633] [2025-03-09 08:03:08,771 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1277607633] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:03:08,771 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:03:08,771 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2025-03-09 08:03:08,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128699978] [2025-03-09 08:03:08,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:03:08,771 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:03:08,772 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:03:08,773 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2025-03-09 08:03:08,773 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=265, Unknown=0, NotChecked=0, Total=306 [2025-03-09 08:03:08,773 INFO L87 Difference]: Start difference. First operand 489 states and 676 transitions. cyclomatic complexity: 190 Second operand has 18 states, 18 states have (on average 4.5) internal successors, (81), 18 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:03:10,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:03:10,913 INFO L93 Difference]: Finished difference Result 610 states and 847 transitions. [2025-03-09 08:03:10,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 610 states and 847 transitions. [2025-03-09 08:03:10,915 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 603 [2025-03-09 08:03:10,916 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 610 states to 610 states and 847 transitions. [2025-03-09 08:03:10,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 610 [2025-03-09 08:03:10,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 610 [2025-03-09 08:03:10,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 610 states and 847 transitions. [2025-03-09 08:03:10,919 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:03:10,919 INFO L218 hiAutomatonCegarLoop]: Abstraction has 610 states and 847 transitions. [2025-03-09 08:03:10,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 610 states and 847 transitions. [2025-03-09 08:03:10,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 610 to 502. [2025-03-09 08:03:10,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 502 states, 498 states have (on average 1.3815261044176708) internal successors, (688), 497 states have internal predecessors, (688), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:03:10,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 502 states to 502 states and 694 transitions. [2025-03-09 08:03:10,926 INFO L240 hiAutomatonCegarLoop]: Abstraction has 502 states and 694 transitions. [2025-03-09 08:03:10,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2025-03-09 08:03:10,926 INFO L432 stractBuchiCegarLoop]: Abstraction has 502 states and 694 transitions. [2025-03-09 08:03:10,926 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-03-09 08:03:10,926 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 502 states and 694 transitions. [2025-03-09 08:03:10,927 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 495 [2025-03-09 08:03:10,927 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:03:10,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:03:10,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:03:10,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:03:10,928 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:03:10,930 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise82#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:03:10,931 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:10,931 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 22 times [2025-03-09 08:03:10,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:10,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [723558200] [2025-03-09 08:03:10,931 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 08:03:10,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:10,939 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-09 08:03:10,940 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:10,940 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 08:03:10,940 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:10,940 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:03:10,942 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:10,943 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:10,943 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:10,943 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:10,947 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:03:10,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:10,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1835596610, now seen corresponding path program 1 times [2025-03-09 08:03:10,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:10,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354071245] [2025-03-09 08:03:10,947 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:03:10,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:10,968 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-09 08:03:11,008 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-09 08:03:11,008 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:11,008 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:03:11,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:03:11,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:03:11,268 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [354071245] [2025-03-09 08:03:11,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [354071245] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:03:11,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:03:11,268 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2025-03-09 08:03:11,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [957545036] [2025-03-09 08:03:11,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:03:11,268 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:03:11,268 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:03:11,269 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2025-03-09 08:03:11,269 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2025-03-09 08:03:11,269 INFO L87 Difference]: Start difference. First operand 502 states and 694 transitions. cyclomatic complexity: 195 Second operand has 11 states, 11 states have (on average 7.363636363636363) internal successors, (81), 11 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:03:12,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:03:12,081 INFO L93 Difference]: Finished difference Result 518 states and 714 transitions. [2025-03-09 08:03:12,081 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 714 transitions. [2025-03-09 08:03:12,083 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 511 [2025-03-09 08:03:12,084 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 518 states and 714 transitions. [2025-03-09 08:03:12,084 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 518 [2025-03-09 08:03:12,084 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 518 [2025-03-09 08:03:12,085 INFO L73 IsDeterministic]: Start isDeterministic. Operand 518 states and 714 transitions. [2025-03-09 08:03:12,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:03:12,085 INFO L218 hiAutomatonCegarLoop]: Abstraction has 518 states and 714 transitions. [2025-03-09 08:03:12,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states and 714 transitions. [2025-03-09 08:03:12,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 505. [2025-03-09 08:03:12,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 505 states, 501 states have (on average 1.379241516966068) internal successors, (691), 500 states have internal predecessors, (691), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:03:12,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 505 states to 505 states and 697 transitions. [2025-03-09 08:03:12,091 INFO L240 hiAutomatonCegarLoop]: Abstraction has 505 states and 697 transitions. [2025-03-09 08:03:12,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:03:12,092 INFO L432 stractBuchiCegarLoop]: Abstraction has 505 states and 697 transitions. [2025-03-09 08:03:12,092 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-03-09 08:03:12,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 505 states and 697 transitions. [2025-03-09 08:03:12,093 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 498 [2025-03-09 08:03:12,093 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:03:12,093 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:03:12,093 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:03:12,094 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:03:12,094 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:03:12,094 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise80#1;assume main_#t~bitwise80#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:03:12,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:12,094 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 23 times [2025-03-09 08:03:12,095 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:12,095 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [258972135] [2025-03-09 08:03:12,095 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 08:03:12,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:12,102 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:12,104 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:12,104 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:03:12,104 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:12,104 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:03:12,106 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:12,107 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:12,107 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:12,107 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:12,111 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:03:12,112 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:12,112 INFO L85 PathProgramCache]: Analyzing trace with hash -1141459414, now seen corresponding path program 1 times [2025-03-09 08:03:12,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:12,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61725472] [2025-03-09 08:03:12,112 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:03:12,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:12,135 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-09 08:03:12,163 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-09 08:03:12,163 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:12,163 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:03:12,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:03:12,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:03:12,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [61725472] [2025-03-09 08:03:12,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [61725472] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:03:12,397 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:03:12,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-09 08:03:12,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [43535951] [2025-03-09 08:03:12,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:03:12,398 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:03:12,398 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:03:12,398 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-09 08:03:12,398 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-03-09 08:03:12,398 INFO L87 Difference]: Start difference. First operand 505 states and 697 transitions. cyclomatic complexity: 195 Second operand has 10 states, 10 states have (on average 8.1) internal successors, (81), 10 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:03:13,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:03:13,275 INFO L93 Difference]: Finished difference Result 517 states and 714 transitions. [2025-03-09 08:03:13,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 517 states and 714 transitions. [2025-03-09 08:03:13,277 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 510 [2025-03-09 08:03:13,278 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 517 states to 517 states and 714 transitions. [2025-03-09 08:03:13,278 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 517 [2025-03-09 08:03:13,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 517 [2025-03-09 08:03:13,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 517 states and 714 transitions. [2025-03-09 08:03:13,279 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:03:13,279 INFO L218 hiAutomatonCegarLoop]: Abstraction has 517 states and 714 transitions. [2025-03-09 08:03:13,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states and 714 transitions. [2025-03-09 08:03:13,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 509. [2025-03-09 08:03:13,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 509 states, 505 states have (on average 1.378217821782178) internal successors, (696), 504 states have internal predecessors, (696), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:03:13,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 509 states to 509 states and 702 transitions. [2025-03-09 08:03:13,285 INFO L240 hiAutomatonCegarLoop]: Abstraction has 509 states and 702 transitions. [2025-03-09 08:03:13,285 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:03:13,286 INFO L432 stractBuchiCegarLoop]: Abstraction has 509 states and 702 transitions. [2025-03-09 08:03:13,286 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-03-09 08:03:13,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 509 states and 702 transitions. [2025-03-09 08:03:13,286 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 502 [2025-03-09 08:03:13,287 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:03:13,287 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:03:13,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:03:13,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:03:13,287 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:03:13,288 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise80#1;assume main_#t~bitwise80#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:03:13,288 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:13,288 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 24 times [2025-03-09 08:03:13,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:13,288 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212428787] [2025-03-09 08:03:13,288 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 08:03:13,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:13,294 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:13,295 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:13,295 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 08:03:13,296 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:13,296 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:03:13,297 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:13,299 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:13,300 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:13,300 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:13,304 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:03:13,304 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:13,304 INFO L85 PathProgramCache]: Analyzing trace with hash 12907600, now seen corresponding path program 1 times [2025-03-09 08:03:13,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:13,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254080406] [2025-03-09 08:03:13,305 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:03:13,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:13,328 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-09 08:03:13,376 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-09 08:03:13,376 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:13,376 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:03:13,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:03:13,793 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:03:13,793 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254080406] [2025-03-09 08:03:13,793 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254080406] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:03:13,793 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:03:13,793 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-09 08:03:13,793 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104391857] [2025-03-09 08:03:13,793 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:03:13,793 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:03:13,793 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:03:13,794 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-09 08:03:13,794 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-03-09 08:03:13,794 INFO L87 Difference]: Start difference. First operand 509 states and 702 transitions. cyclomatic complexity: 196 Second operand has 10 states, 10 states have (on average 8.1) internal successors, (81), 10 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:03:18,801 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 4.33s for a HTC check with result VALID. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2025-03-09 08:03:19,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:03:19,282 INFO L93 Difference]: Finished difference Result 523 states and 719 transitions. [2025-03-09 08:03:19,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 523 states and 719 transitions. [2025-03-09 08:03:19,283 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 516 [2025-03-09 08:03:19,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 523 states to 523 states and 719 transitions. [2025-03-09 08:03:19,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 523 [2025-03-09 08:03:19,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 523 [2025-03-09 08:03:19,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 523 states and 719 transitions. [2025-03-09 08:03:19,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:03:19,285 INFO L218 hiAutomatonCegarLoop]: Abstraction has 523 states and 719 transitions. [2025-03-09 08:03:19,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 523 states and 719 transitions. [2025-03-09 08:03:19,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 523 to 510. [2025-03-09 08:03:19,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 510 states, 506 states have (on average 1.3774703557312253) internal successors, (697), 505 states have internal predecessors, (697), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:03:19,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 510 states to 510 states and 703 transitions. [2025-03-09 08:03:19,292 INFO L240 hiAutomatonCegarLoop]: Abstraction has 510 states and 703 transitions. [2025-03-09 08:03:19,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:03:19,293 INFO L432 stractBuchiCegarLoop]: Abstraction has 510 states and 703 transitions. [2025-03-09 08:03:19,293 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-03-09 08:03:19,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 510 states and 703 transitions. [2025-03-09 08:03:19,293 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 503 [2025-03-09 08:03:19,293 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:03:19,293 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:03:19,294 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:03:19,294 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:03:19,294 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#1(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#1(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:03:19,295 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#3(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#3(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#3(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#3(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#3(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#3(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#3(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#3(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#3(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#3(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#3(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#3(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#3(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#3(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#3(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#3(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#3(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#3(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#3(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#3(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0);havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;" "call write~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#3(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#3(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#3(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#3(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#2(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-09 08:03:19,295 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:19,295 INFO L85 PathProgramCache]: Analyzing trace with hash 25888, now seen corresponding path program 25 times [2025-03-09 08:03:19,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:19,295 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466405284] [2025-03-09 08:03:19,295 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 08:03:19,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:19,301 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:19,303 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:19,303 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:19,303 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:19,303 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:03:19,305 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:03:19,305 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:03:19,305 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:19,305 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:03:19,309 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:03:19,309 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:03:19,309 INFO L85 PathProgramCache]: Analyzing trace with hash -1194198945, now seen corresponding path program 1 times [2025-03-09 08:03:19,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:03:19,309 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817272983] [2025-03-09 08:03:19,309 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:03:19,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:03:19,331 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-09 08:03:19,424 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-09 08:03:19,424 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:03:19,424 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:03:26,150 WARN L286 SmtUtils]: Spent 6.47s on a formula simplification that was a NOOP. DAG size: 32 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2025-03-09 08:03:32,643 WARN L286 SmtUtils]: Spent 6.48s on a formula simplification that was a NOOP. DAG size: 10 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2025-03-09 08:03:48,392 WARN L286 SmtUtils]: Spent 15.40s on a formula simplification that was a NOOP. DAG size: 39 (called from [L 388] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2025-03-09 08:04:04,455 WARN L286 SmtUtils]: Spent 12.01s on a formula simplification that was a NOOP. DAG size: 10 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify)