./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e2fb8bed Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c2bb9f0c15e3c3296f863c26b4377b27546cf1c417a60e9663a6ff48eb617ef8 --- Real Ultimate output --- This is Ultimate 0.3.0-?-e2fb8be-m [2025-03-09 08:06:32,936 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-09 08:06:32,989 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-09 08:06:32,992 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-09 08:06:32,994 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-09 08:06:32,995 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-09 08:06:33,008 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-09 08:06:33,008 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-09 08:06:33,009 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-09 08:06:33,009 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-09 08:06:33,009 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-09 08:06:33,009 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-09 08:06:33,009 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-09 08:06:33,009 INFO L153 SettingsManager]: * Use SBE=true [2025-03-09 08:06:33,009 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-09 08:06:33,010 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-09 08:06:33,010 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-09 08:06:33,010 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-09 08:06:33,010 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-09 08:06:33,010 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-09 08:06:33,010 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-09 08:06:33,010 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-09 08:06:33,010 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-09 08:06:33,010 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-09 08:06:33,010 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-09 08:06:33,010 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-09 08:06:33,011 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-09 08:06:33,011 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-09 08:06:33,011 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-09 08:06:33,011 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-09 08:06:33,011 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-09 08:06:33,011 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-09 08:06:33,011 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-09 08:06:33,011 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-09 08:06:33,011 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-09 08:06:33,011 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-09 08:06:33,011 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-09 08:06:33,012 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-09 08:06:33,012 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-09 08:06:33,012 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-09 08:06:33,012 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c2bb9f0c15e3c3296f863c26b4377b27546cf1c417a60e9663a6ff48eb617ef8 [2025-03-09 08:06:33,227 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-09 08:06:33,235 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-09 08:06:33,236 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-09 08:06:33,237 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-09 08:06:33,238 INFO L274 PluginConnector]: CDTParser initialized [2025-03-09 08:06:33,239 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i [2025-03-09 08:06:34,338 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/04c965ca7/78f9601065fe4ab18fa05a3aa3a94dd0/FLAG53a951d27 [2025-03-09 08:06:34,594 INFO L384 CDTParser]: Found 1 translation units. [2025-03-09 08:06:34,596 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/uthash-2.0.2/uthash_SFH_test7-1.i [2025-03-09 08:06:34,609 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/04c965ca7/78f9601065fe4ab18fa05a3aa3a94dd0/FLAG53a951d27 [2025-03-09 08:06:34,895 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/04c965ca7/78f9601065fe4ab18fa05a3aa3a94dd0 [2025-03-09 08:06:34,898 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-09 08:06:34,899 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-09 08:06:34,900 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-09 08:06:34,900 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-09 08:06:34,904 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-09 08:06:34,904 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 08:06:34" (1/1) ... [2025-03-09 08:06:34,905 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3c86b5e4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:34, skipping insertion in model container [2025-03-09 08:06:34,905 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.03 08:06:34" (1/1) ... [2025-03-09 08:06:34,936 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-09 08:06:35,297 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 08:06:35,311 INFO L200 MainTranslator]: Completed pre-run [2025-03-09 08:06:35,383 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-09 08:06:35,405 INFO L204 MainTranslator]: Completed translation [2025-03-09 08:06:35,405 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35 WrapperNode [2025-03-09 08:06:35,405 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-09 08:06:35,406 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-09 08:06:35,406 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-09 08:06:35,406 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-09 08:06:35,410 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35" (1/1) ... [2025-03-09 08:06:35,430 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35" (1/1) ... [2025-03-09 08:06:35,473 INFO L138 Inliner]: procedures = 176, calls = 272, calls flagged for inlining = 5, calls inlined = 4, statements flattened = 1387 [2025-03-09 08:06:35,473 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-09 08:06:35,473 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-09 08:06:35,473 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-09 08:06:35,473 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-09 08:06:35,480 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35" (1/1) ... [2025-03-09 08:06:35,480 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35" (1/1) ... [2025-03-09 08:06:35,492 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35" (1/1) ... [2025-03-09 08:06:35,554 INFO L175 MemorySlicer]: Split 253 memory accesses to 3 slices as follows [2, 217, 34]. 86 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0, 0]. The 54 writes are split as follows [0, 50, 4]. [2025-03-09 08:06:35,555 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35" (1/1) ... [2025-03-09 08:06:35,555 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35" (1/1) ... [2025-03-09 08:06:35,581 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35" (1/1) ... [2025-03-09 08:06:35,584 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35" (1/1) ... [2025-03-09 08:06:35,587 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35" (1/1) ... [2025-03-09 08:06:35,590 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35" (1/1) ... [2025-03-09 08:06:35,597 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-09 08:06:35,601 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-09 08:06:35,601 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-09 08:06:35,601 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-09 08:06:35,603 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35" (1/1) ... [2025-03-09 08:06:35,607 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-09 08:06:35,617 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-09 08:06:35,634 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-09 08:06:35,639 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-09 08:06:35,658 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-03-09 08:06:35,658 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-03-09 08:06:35,658 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2025-03-09 08:06:35,658 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-03-09 08:06:35,658 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-03-09 08:06:35,658 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2025-03-09 08:06:35,658 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#0 [2025-03-09 08:06:35,658 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#1 [2025-03-09 08:06:35,658 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#2 [2025-03-09 08:06:35,658 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#0 [2025-03-09 08:06:35,658 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#1 [2025-03-09 08:06:35,658 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#2 [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#0 [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#1 [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#2 [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#0 [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#1 [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#2 [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#2 [2025-03-09 08:06:35,659 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-09 08:06:35,659 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-09 08:06:35,845 INFO L256 CfgBuilder]: Building ICFG [2025-03-09 08:06:35,847 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-09 08:06:37,036 INFO L1307 $ProcedureCfgBuilder]: dead code at ProgramPoint L713: call ULTIMATE.dealloc(main_~#i~0#1.base, main_~#i~0#1.offset);havoc main_~#i~0#1.base, main_~#i~0#1.offset; [2025-03-09 08:06:37,133 INFO L? ?]: Removed 310 outVars from TransFormulas that were not future-live. [2025-03-09 08:06:37,134 INFO L307 CfgBuilder]: Performing block encoding [2025-03-09 08:06:37,186 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-09 08:06:37,188 INFO L336 CfgBuilder]: Removed 1 assume(true) statements. [2025-03-09 08:06:37,189 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 08:06:37 BoogieIcfgContainer [2025-03-09 08:06:37,191 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-09 08:06:37,193 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-09 08:06:37,193 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-09 08:06:37,197 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-09 08:06:37,198 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 08:06:37,198 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.03 08:06:34" (1/3) ... [2025-03-09 08:06:37,199 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@216bfebf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 08:06:37, skipping insertion in model container [2025-03-09 08:06:37,199 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 08:06:37,199 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.03 08:06:35" (2/3) ... [2025-03-09 08:06:37,199 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@216bfebf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.03 08:06:37, skipping insertion in model container [2025-03-09 08:06:37,199 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-09 08:06:37,199 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 09.03 08:06:37" (3/3) ... [2025-03-09 08:06:37,200 INFO L363 chiAutomizerObserver]: Analyzing ICFG uthash_SFH_test7-1.i [2025-03-09 08:06:37,243 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-09 08:06:37,244 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-09 08:06:37,244 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-09 08:06:37,244 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-09 08:06:37,245 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-09 08:06:37,245 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-09 08:06:37,245 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-09 08:06:37,245 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-09 08:06:37,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 390 states, 385 states have (on average 1.6181818181818182) internal successors, (623), 385 states have internal predecessors, (623), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:37,279 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 379 [2025-03-09 08:06:37,282 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:37,282 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:37,286 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:37,286 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-03-09 08:06:37,286 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-09 08:06:37,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 390 states, 385 states have (on average 1.6181818181818182) internal successors, (623), 385 states have internal predecessors, (623), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:37,300 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 379 [2025-03-09 08:06:37,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:37,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:37,301 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:37,301 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-03-09 08:06:37,304 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:37,304 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false;" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume !true;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:37,308 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:37,308 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 1 times [2025-03-09 08:06:37,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:37,313 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454205631] [2025-03-09 08:06:37,313 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:37,313 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:37,369 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:37,381 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:37,382 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:37,382 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:37,382 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:37,391 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:37,395 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:37,397 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:37,397 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:37,417 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:37,420 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:37,420 INFO L85 PathProgramCache]: Analyzing trace with hash -501275750, now seen corresponding path program 1 times [2025-03-09 08:06:37,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:37,421 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945184363] [2025-03-09 08:06:37,421 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:37,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:37,432 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-09 08:06:37,438 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-09 08:06:37,438 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:37,438 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:37,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:37,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:37,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1945184363] [2025-03-09 08:06:37,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1945184363] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:37,481 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:37,481 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-09 08:06:37,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375905037] [2025-03-09 08:06:37,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:37,484 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:37,485 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:37,504 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-09 08:06:37,504 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-09 08:06:37,506 INFO L87 Difference]: Start difference. First operand has 390 states, 385 states have (on average 1.6181818181818182) internal successors, (623), 385 states have internal predecessors, (623), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 3.0) internal successors, (6), 2 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:37,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:37,598 INFO L93 Difference]: Finished difference Result 388 states and 561 transitions. [2025-03-09 08:06:37,598 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 388 states and 561 transitions. [2025-03-09 08:06:37,603 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 374 [2025-03-09 08:06:37,614 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 388 states to 381 states and 554 transitions. [2025-03-09 08:06:37,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 381 [2025-03-09 08:06:37,617 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 381 [2025-03-09 08:06:37,619 INFO L73 IsDeterministic]: Start isDeterministic. Operand 381 states and 554 transitions. [2025-03-09 08:06:37,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:37,622 INFO L218 hiAutomatonCegarLoop]: Abstraction has 381 states and 554 transitions. [2025-03-09 08:06:37,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 381 states and 554 transitions. [2025-03-09 08:06:37,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 381 to 381. [2025-03-09 08:06:37,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 381 states, 377 states have (on average 1.453580901856764) internal successors, (548), 376 states have internal predecessors, (548), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:37,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 554 transitions. [2025-03-09 08:06:37,651 INFO L240 hiAutomatonCegarLoop]: Abstraction has 381 states and 554 transitions. [2025-03-09 08:06:37,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-09 08:06:37,654 INFO L432 stractBuchiCegarLoop]: Abstraction has 381 states and 554 transitions. [2025-03-09 08:06:37,654 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-09 08:06:37,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 381 states and 554 transitions. [2025-03-09 08:06:37,656 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 374 [2025-03-09 08:06:37,656 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:37,656 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:37,657 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:37,657 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:37,657 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:37,658 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem30#1 := read~int#1(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem30#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem31#1 := read~int#1(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem31#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem32#1 := read~int#1(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem32#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem33#1 := read~int#1(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem33#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem34#1 := read~int#1(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem34#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise42#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:37,658 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:37,658 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 2 times [2025-03-09 08:06:37,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:37,658 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235906471] [2025-03-09 08:06:37,659 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 08:06:37,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:37,666 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:37,670 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:37,670 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:06:37,670 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:37,670 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:37,673 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:37,676 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:37,676 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:37,676 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:37,681 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:37,682 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:37,682 INFO L85 PathProgramCache]: Analyzing trace with hash 2117616262, now seen corresponding path program 1 times [2025-03-09 08:06:37,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:37,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113169077] [2025-03-09 08:06:37,682 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:37,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:37,730 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes. [2025-03-09 08:06:37,741 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements. [2025-03-09 08:06:37,741 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:37,741 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:38,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:38,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:38,016 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113169077] [2025-03-09 08:06:38,016 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1113169077] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:38,016 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:38,017 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-09 08:06:38,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175977909] [2025-03-09 08:06:38,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:38,017 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:38,017 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:38,017 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-09 08:06:38,017 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-09 08:06:38,018 INFO L87 Difference]: Start difference. First operand 381 states and 554 transitions. cyclomatic complexity: 176 Second operand has 4 states, 4 states have (on average 18.5) internal successors, (74), 4 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:38,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:38,182 INFO L93 Difference]: Finished difference Result 384 states and 550 transitions. [2025-03-09 08:06:38,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 384 states and 550 transitions. [2025-03-09 08:06:38,184 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 377 [2025-03-09 08:06:38,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 384 states to 384 states and 550 transitions. [2025-03-09 08:06:38,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 384 [2025-03-09 08:06:38,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2025-03-09 08:06:38,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 384 states and 550 transitions. [2025-03-09 08:06:38,190 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:38,190 INFO L218 hiAutomatonCegarLoop]: Abstraction has 384 states and 550 transitions. [2025-03-09 08:06:38,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 384 states and 550 transitions. [2025-03-09 08:06:38,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 384 to 381. [2025-03-09 08:06:38,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 381 states, 377 states have (on average 1.4350132625994696) internal successors, (541), 376 states have internal predecessors, (541), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:38,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 547 transitions. [2025-03-09 08:06:38,217 INFO L240 hiAutomatonCegarLoop]: Abstraction has 381 states and 547 transitions. [2025-03-09 08:06:38,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-09 08:06:38,217 INFO L432 stractBuchiCegarLoop]: Abstraction has 381 states and 547 transitions. [2025-03-09 08:06:38,217 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-09 08:06:38,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 381 states and 547 transitions. [2025-03-09 08:06:38,219 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 374 [2025-03-09 08:06:38,219 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:38,219 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:38,219 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:38,219 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:38,220 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:38,222 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise42#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:38,226 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:38,226 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 3 times [2025-03-09 08:06:38,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:38,226 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285033801] [2025-03-09 08:06:38,226 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 08:06:38,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:38,234 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:38,237 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:38,237 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 08:06:38,237 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:38,237 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:38,240 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:38,242 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:38,242 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:38,243 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:38,253 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:38,254 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:38,254 INFO L85 PathProgramCache]: Analyzing trace with hash -1945620276, now seen corresponding path program 1 times [2025-03-09 08:06:38,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:38,254 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094319921] [2025-03-09 08:06:38,254 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:38,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:38,295 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes. [2025-03-09 08:06:38,502 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements. [2025-03-09 08:06:38,503 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:38,503 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:38,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:38,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:38,942 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1094319921] [2025-03-09 08:06:38,942 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1094319921] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:38,942 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:38,943 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-09 08:06:38,943 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [527837503] [2025-03-09 08:06:38,943 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:38,943 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:38,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:38,943 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-09 08:06:38,944 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-09 08:06:38,944 INFO L87 Difference]: Start difference. First operand 381 states and 547 transitions. cyclomatic complexity: 169 Second operand has 6 states, 6 states have (on average 12.333333333333334) internal successors, (74), 6 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:39,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:39,645 INFO L93 Difference]: Finished difference Result 415 states and 590 transitions. [2025-03-09 08:06:39,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 415 states and 590 transitions. [2025-03-09 08:06:39,647 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 408 [2025-03-09 08:06:39,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 415 states to 415 states and 590 transitions. [2025-03-09 08:06:39,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 415 [2025-03-09 08:06:39,650 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 415 [2025-03-09 08:06:39,650 INFO L73 IsDeterministic]: Start isDeterministic. Operand 415 states and 590 transitions. [2025-03-09 08:06:39,651 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:39,651 INFO L218 hiAutomatonCegarLoop]: Abstraction has 415 states and 590 transitions. [2025-03-09 08:06:39,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 415 states and 590 transitions. [2025-03-09 08:06:39,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 415 to 410. [2025-03-09 08:06:39,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 410 states, 406 states have (on average 1.4211822660098523) internal successors, (577), 405 states have internal predecessors, (577), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:39,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 410 states to 410 states and 583 transitions. [2025-03-09 08:06:39,660 INFO L240 hiAutomatonCegarLoop]: Abstraction has 410 states and 583 transitions. [2025-03-09 08:06:39,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-09 08:06:39,663 INFO L432 stractBuchiCegarLoop]: Abstraction has 410 states and 583 transitions. [2025-03-09 08:06:39,663 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-09 08:06:39,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 410 states and 583 transitions. [2025-03-09 08:06:39,665 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 403 [2025-03-09 08:06:39,665 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:39,665 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:39,666 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:39,666 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:39,666 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:39,666 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:39,667 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:39,667 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 4 times [2025-03-09 08:06:39,667 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:39,667 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887989920] [2025-03-09 08:06:39,667 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 08:06:39,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:39,674 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-09 08:06:39,677 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:39,677 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 08:06:39,677 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:39,677 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:39,680 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:39,681 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:39,682 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:39,682 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:39,685 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:39,686 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:39,686 INFO L85 PathProgramCache]: Analyzing trace with hash -601365105, now seen corresponding path program 1 times [2025-03-09 08:06:39,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:39,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688616464] [2025-03-09 08:06:39,686 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:39,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:39,711 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-09 08:06:39,742 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-09 08:06:39,742 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:39,743 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:39,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:39,958 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:39,959 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688616464] [2025-03-09 08:06:39,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688616464] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:39,959 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:39,959 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-09 08:06:39,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [631996705] [2025-03-09 08:06:39,959 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:39,959 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:39,959 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:39,959 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-09 08:06:39,959 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-09 08:06:39,959 INFO L87 Difference]: Start difference. First operand 410 states and 583 transitions. cyclomatic complexity: 176 Second operand has 7 states, 7 states have (on average 10.714285714285714) internal successors, (75), 7 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:40,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:40,590 INFO L93 Difference]: Finished difference Result 423 states and 602 transitions. [2025-03-09 08:06:40,590 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 423 states and 602 transitions. [2025-03-09 08:06:40,593 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 416 [2025-03-09 08:06:40,594 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 423 states to 423 states and 602 transitions. [2025-03-09 08:06:40,595 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 423 [2025-03-09 08:06:40,595 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 423 [2025-03-09 08:06:40,595 INFO L73 IsDeterministic]: Start isDeterministic. Operand 423 states and 602 transitions. [2025-03-09 08:06:40,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:40,595 INFO L218 hiAutomatonCegarLoop]: Abstraction has 423 states and 602 transitions. [2025-03-09 08:06:40,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 423 states and 602 transitions. [2025-03-09 08:06:40,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 423 to 420. [2025-03-09 08:06:40,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 420 states, 416 states have (on average 1.4230769230769231) internal successors, (592), 415 states have internal predecessors, (592), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:40,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 420 states to 420 states and 598 transitions. [2025-03-09 08:06:40,608 INFO L240 hiAutomatonCegarLoop]: Abstraction has 420 states and 598 transitions. [2025-03-09 08:06:40,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-09 08:06:40,609 INFO L432 stractBuchiCegarLoop]: Abstraction has 420 states and 598 transitions. [2025-03-09 08:06:40,610 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-09 08:06:40,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 420 states and 598 transitions. [2025-03-09 08:06:40,611 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 413 [2025-03-09 08:06:40,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:40,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:40,614 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:40,614 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:40,614 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:40,615 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise42#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:40,615 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:40,615 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 5 times [2025-03-09 08:06:40,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:40,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761272661] [2025-03-09 08:06:40,615 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 08:06:40,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:40,622 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:40,625 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:40,625 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:06:40,625 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:40,625 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:40,627 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:40,629 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:40,629 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:40,629 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:40,635 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:40,635 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:40,635 INFO L85 PathProgramCache]: Analyzing trace with hash 2051162998, now seen corresponding path program 1 times [2025-03-09 08:06:40,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:40,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [682613848] [2025-03-09 08:06:40,635 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:40,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:40,666 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-09 08:06:40,726 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-09 08:06:40,726 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:40,727 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:40,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:40,944 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:40,944 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [682613848] [2025-03-09 08:06:40,944 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [682613848] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:40,944 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:40,945 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-09 08:06:40,945 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1019069120] [2025-03-09 08:06:40,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:40,945 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:40,946 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:40,946 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-09 08:06:40,946 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-09 08:06:40,946 INFO L87 Difference]: Start difference. First operand 420 states and 598 transitions. cyclomatic complexity: 181 Second operand has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:41,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:41,200 INFO L93 Difference]: Finished difference Result 423 states and 601 transitions. [2025-03-09 08:06:41,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 423 states and 601 transitions. [2025-03-09 08:06:41,202 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 416 [2025-03-09 08:06:41,204 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 423 states to 423 states and 601 transitions. [2025-03-09 08:06:41,204 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 423 [2025-03-09 08:06:41,205 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 423 [2025-03-09 08:06:41,205 INFO L73 IsDeterministic]: Start isDeterministic. Operand 423 states and 601 transitions. [2025-03-09 08:06:41,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:41,206 INFO L218 hiAutomatonCegarLoop]: Abstraction has 423 states and 601 transitions. [2025-03-09 08:06:41,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 423 states and 601 transitions. [2025-03-09 08:06:41,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 423 to 420. [2025-03-09 08:06:41,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 420 states, 416 states have (on average 1.4206730769230769) internal successors, (591), 415 states have internal predecessors, (591), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:41,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 420 states to 420 states and 597 transitions. [2025-03-09 08:06:41,213 INFO L240 hiAutomatonCegarLoop]: Abstraction has 420 states and 597 transitions. [2025-03-09 08:06:41,214 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-09 08:06:41,214 INFO L432 stractBuchiCegarLoop]: Abstraction has 420 states and 597 transitions. [2025-03-09 08:06:41,215 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-09 08:06:41,215 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 420 states and 597 transitions. [2025-03-09 08:06:41,216 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 413 [2025-03-09 08:06:41,216 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:41,216 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:41,216 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:41,216 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:41,217 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:41,217 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:41,218 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:41,219 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 6 times [2025-03-09 08:06:41,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:41,219 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108269927] [2025-03-09 08:06:41,219 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 08:06:41,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:41,225 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:41,227 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:41,227 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 08:06:41,227 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:41,227 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:41,231 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:41,233 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:41,233 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:41,233 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:41,240 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:41,240 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:41,240 INFO L85 PathProgramCache]: Analyzing trace with hash 115875205, now seen corresponding path program 1 times [2025-03-09 08:06:41,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:41,240 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210691116] [2025-03-09 08:06:41,240 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:41,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:41,269 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-09 08:06:41,298 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-09 08:06:41,298 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:41,298 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:41,596 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:41,596 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:41,596 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1210691116] [2025-03-09 08:06:41,596 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1210691116] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:41,596 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:41,596 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 08:06:41,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1555452466] [2025-03-09 08:06:41,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:41,596 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:41,596 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:41,596 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 08:06:41,596 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-09 08:06:41,597 INFO L87 Difference]: Start difference. First operand 420 states and 597 transitions. cyclomatic complexity: 180 Second operand has 9 states, 9 states have (on average 8.444444444444445) internal successors, (76), 9 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:42,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:42,494 INFO L93 Difference]: Finished difference Result 434 states and 615 transitions. [2025-03-09 08:06:42,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 434 states and 615 transitions. [2025-03-09 08:06:42,496 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 427 [2025-03-09 08:06:42,498 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 434 states to 434 states and 615 transitions. [2025-03-09 08:06:42,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 434 [2025-03-09 08:06:42,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 434 [2025-03-09 08:06:42,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 434 states and 615 transitions. [2025-03-09 08:06:42,499 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:42,499 INFO L218 hiAutomatonCegarLoop]: Abstraction has 434 states and 615 transitions. [2025-03-09 08:06:42,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 434 states and 615 transitions. [2025-03-09 08:06:42,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 434 to 428. [2025-03-09 08:06:42,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 428 states, 424 states have (on average 1.4174528301886793) internal successors, (601), 423 states have internal predecessors, (601), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:42,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 428 states to 428 states and 607 transitions. [2025-03-09 08:06:42,504 INFO L240 hiAutomatonCegarLoop]: Abstraction has 428 states and 607 transitions. [2025-03-09 08:06:42,510 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-09 08:06:42,510 INFO L432 stractBuchiCegarLoop]: Abstraction has 428 states and 607 transitions. [2025-03-09 08:06:42,510 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-09 08:06:42,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 428 states and 607 transitions. [2025-03-09 08:06:42,512 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 421 [2025-03-09 08:06:42,512 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:42,512 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:42,512 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:42,512 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:42,512 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:42,514 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise42#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:42,514 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:42,514 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 7 times [2025-03-09 08:06:42,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:42,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [639972656] [2025-03-09 08:06:42,515 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 08:06:42,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:42,521 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:42,522 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:42,523 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:42,523 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:42,523 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:42,526 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:42,527 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:42,527 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:42,527 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:42,531 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:42,532 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:42,532 INFO L85 PathProgramCache]: Analyzing trace with hash -520787351, now seen corresponding path program 1 times [2025-03-09 08:06:42,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:42,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956492186] [2025-03-09 08:06:42,533 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:42,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:42,577 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-09 08:06:42,593 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-09 08:06:42,594 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:42,594 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:42,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:42,776 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:42,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [956492186] [2025-03-09 08:06:42,776 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [956492186] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:42,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:42,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-09 08:06:42,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1189174369] [2025-03-09 08:06:42,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:42,776 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:42,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:42,777 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-09 08:06:42,777 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-03-09 08:06:42,777 INFO L87 Difference]: Start difference. First operand 428 states and 607 transitions. cyclomatic complexity: 182 Second operand has 6 states, 6 states have (on average 12.666666666666666) internal successors, (76), 6 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:43,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:43,167 INFO L93 Difference]: Finished difference Result 431 states and 610 transitions. [2025-03-09 08:06:43,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 431 states and 610 transitions. [2025-03-09 08:06:43,169 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 424 [2025-03-09 08:06:43,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 431 states to 431 states and 610 transitions. [2025-03-09 08:06:43,180 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 431 [2025-03-09 08:06:43,180 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 431 [2025-03-09 08:06:43,180 INFO L73 IsDeterministic]: Start isDeterministic. Operand 431 states and 610 transitions. [2025-03-09 08:06:43,181 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:43,181 INFO L218 hiAutomatonCegarLoop]: Abstraction has 431 states and 610 transitions. [2025-03-09 08:06:43,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431 states and 610 transitions. [2025-03-09 08:06:43,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431 to 431. [2025-03-09 08:06:43,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 431 states, 427 states have (on average 1.414519906323185) internal successors, (604), 426 states have internal predecessors, (604), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:43,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 431 states to 431 states and 610 transitions. [2025-03-09 08:06:43,190 INFO L240 hiAutomatonCegarLoop]: Abstraction has 431 states and 610 transitions. [2025-03-09 08:06:43,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-09 08:06:43,191 INFO L432 stractBuchiCegarLoop]: Abstraction has 431 states and 610 transitions. [2025-03-09 08:06:43,191 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-09 08:06:43,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 431 states and 610 transitions. [2025-03-09 08:06:43,192 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 424 [2025-03-09 08:06:43,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:43,192 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:43,193 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:43,193 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:43,193 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:43,193 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise42#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:43,194 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:43,194 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 8 times [2025-03-09 08:06:43,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:43,195 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670882686] [2025-03-09 08:06:43,195 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 08:06:43,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:43,201 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:43,203 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:43,203 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:06:43,204 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:43,204 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:43,206 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:43,207 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:43,207 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:43,207 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:43,211 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:43,211 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:43,211 INFO L85 PathProgramCache]: Analyzing trace with hash -718745081, now seen corresponding path program 1 times [2025-03-09 08:06:43,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:43,211 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856861858] [2025-03-09 08:06:43,211 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:43,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:43,240 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-09 08:06:43,303 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-09 08:06:43,304 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:43,304 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:43,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:43,489 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:43,489 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856861858] [2025-03-09 08:06:43,489 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856861858] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:43,490 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:43,490 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-09 08:06:43,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1120792527] [2025-03-09 08:06:43,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:43,490 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:43,490 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:43,490 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-09 08:06:43,490 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-09 08:06:43,490 INFO L87 Difference]: Start difference. First operand 431 states and 610 transitions. cyclomatic complexity: 182 Second operand has 7 states, 7 states have (on average 11.0) internal successors, (77), 7 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:44,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:44,109 INFO L93 Difference]: Finished difference Result 438 states and 619 transitions. [2025-03-09 08:06:44,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 438 states and 619 transitions. [2025-03-09 08:06:44,111 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 431 [2025-03-09 08:06:44,112 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 438 states to 438 states and 619 transitions. [2025-03-09 08:06:44,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 438 [2025-03-09 08:06:44,113 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 438 [2025-03-09 08:06:44,113 INFO L73 IsDeterministic]: Start isDeterministic. Operand 438 states and 619 transitions. [2025-03-09 08:06:44,113 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:44,113 INFO L218 hiAutomatonCegarLoop]: Abstraction has 438 states and 619 transitions. [2025-03-09 08:06:44,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 438 states and 619 transitions. [2025-03-09 08:06:44,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 438 to 431. [2025-03-09 08:06:44,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 431 states, 427 states have (on average 1.414519906323185) internal successors, (604), 426 states have internal predecessors, (604), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:44,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 431 states to 431 states and 610 transitions. [2025-03-09 08:06:44,119 INFO L240 hiAutomatonCegarLoop]: Abstraction has 431 states and 610 transitions. [2025-03-09 08:06:44,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-09 08:06:44,120 INFO L432 stractBuchiCegarLoop]: Abstraction has 431 states and 610 transitions. [2025-03-09 08:06:44,120 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-09 08:06:44,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 431 states and 610 transitions. [2025-03-09 08:06:44,121 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 424 [2025-03-09 08:06:44,121 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:44,121 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:44,121 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:44,121 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:44,122 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:44,122 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise42#1;assume main_#t~bitwise42#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:44,122 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:44,122 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 9 times [2025-03-09 08:06:44,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:44,122 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814802104] [2025-03-09 08:06:44,122 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 08:06:44,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:44,128 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:44,130 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:44,130 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 08:06:44,130 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:44,130 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:44,132 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:44,133 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:44,133 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:44,133 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:44,138 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:44,139 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:44,139 INFO L85 PathProgramCache]: Analyzing trace with hash 1666907704, now seen corresponding path program 1 times [2025-03-09 08:06:44,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:44,139 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2087337802] [2025-03-09 08:06:44,139 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:44,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:44,165 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-09 08:06:44,252 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-09 08:06:44,253 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:44,253 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:44,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:44,693 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:44,693 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2087337802] [2025-03-09 08:06:44,693 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2087337802] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:44,693 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:44,693 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-09 08:06:44,693 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [373166888] [2025-03-09 08:06:44,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:44,693 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:44,694 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:44,694 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-09 08:06:44,694 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-09 08:06:44,694 INFO L87 Difference]: Start difference. First operand 431 states and 610 transitions. cyclomatic complexity: 182 Second operand has 13 states, 13 states have (on average 5.923076923076923) internal successors, (77), 13 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:46,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:46,519 INFO L93 Difference]: Finished difference Result 529 states and 750 transitions. [2025-03-09 08:06:46,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 529 states and 750 transitions. [2025-03-09 08:06:46,521 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 522 [2025-03-09 08:06:46,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 529 states to 529 states and 750 transitions. [2025-03-09 08:06:46,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 529 [2025-03-09 08:06:46,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 529 [2025-03-09 08:06:46,524 INFO L73 IsDeterministic]: Start isDeterministic. Operand 529 states and 750 transitions. [2025-03-09 08:06:46,525 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:46,525 INFO L218 hiAutomatonCegarLoop]: Abstraction has 529 states and 750 transitions. [2025-03-09 08:06:46,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 529 states and 750 transitions. [2025-03-09 08:06:46,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 529 to 437. [2025-03-09 08:06:46,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 437 states, 433 states have (on average 1.4133949191685913) internal successors, (612), 432 states have internal predecessors, (612), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:46,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 437 states to 437 states and 618 transitions. [2025-03-09 08:06:46,531 INFO L240 hiAutomatonCegarLoop]: Abstraction has 437 states and 618 transitions. [2025-03-09 08:06:46,532 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-09 08:06:46,532 INFO L432 stractBuchiCegarLoop]: Abstraction has 437 states and 618 transitions. [2025-03-09 08:06:46,533 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-09 08:06:46,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 437 states and 618 transitions. [2025-03-09 08:06:46,534 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 430 [2025-03-09 08:06:46,534 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:46,534 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:46,534 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:46,534 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:46,535 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:46,535 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise42#1;assume main_#t~bitwise42#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise44#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:46,535 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:46,535 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 10 times [2025-03-09 08:06:46,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:46,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [923904386] [2025-03-09 08:06:46,535 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 08:06:46,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:46,541 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-09 08:06:46,542 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:46,542 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 08:06:46,543 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:46,543 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:46,545 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:46,546 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:46,546 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:46,546 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:46,550 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:46,550 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:46,551 INFO L85 PathProgramCache]: Analyzing trace with hash 2009903253, now seen corresponding path program 1 times [2025-03-09 08:06:46,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:46,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243388636] [2025-03-09 08:06:46,551 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:46,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:46,582 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-09 08:06:46,691 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-09 08:06:46,691 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:46,691 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:47,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:47,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:47,036 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243388636] [2025-03-09 08:06:47,036 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [243388636] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:47,036 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:47,037 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2025-03-09 08:06:47,037 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1611047291] [2025-03-09 08:06:47,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:47,037 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:47,037 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:47,037 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2025-03-09 08:06:47,037 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2025-03-09 08:06:47,038 INFO L87 Difference]: Start difference. First operand 437 states and 618 transitions. cyclomatic complexity: 184 Second operand has 11 states, 11 states have (on average 7.090909090909091) internal successors, (78), 11 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:48,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:48,281 INFO L93 Difference]: Finished difference Result 509 states and 716 transitions. [2025-03-09 08:06:48,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 509 states and 716 transitions. [2025-03-09 08:06:48,283 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 502 [2025-03-09 08:06:48,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 509 states to 509 states and 716 transitions. [2025-03-09 08:06:48,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 509 [2025-03-09 08:06:48,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 509 [2025-03-09 08:06:48,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 509 states and 716 transitions. [2025-03-09 08:06:48,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:48,286 INFO L218 hiAutomatonCegarLoop]: Abstraction has 509 states and 716 transitions. [2025-03-09 08:06:48,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 509 states and 716 transitions. [2025-03-09 08:06:48,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 509 to 440. [2025-03-09 08:06:48,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 440 states, 436 states have (on average 1.4128440366972477) internal successors, (616), 435 states have internal predecessors, (616), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:48,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 440 states to 440 states and 622 transitions. [2025-03-09 08:06:48,292 INFO L240 hiAutomatonCegarLoop]: Abstraction has 440 states and 622 transitions. [2025-03-09 08:06:48,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-09 08:06:48,293 INFO L432 stractBuchiCegarLoop]: Abstraction has 440 states and 622 transitions. [2025-03-09 08:06:48,293 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-09 08:06:48,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 440 states and 622 transitions. [2025-03-09 08:06:48,294 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 433 [2025-03-09 08:06:48,294 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:48,294 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:48,294 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:48,294 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:48,295 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:48,295 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise42#1;assume main_#t~bitwise42#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 32 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:48,295 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:48,295 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 11 times [2025-03-09 08:06:48,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:48,295 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1163227154] [2025-03-09 08:06:48,295 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 08:06:48,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:48,301 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:48,302 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:48,302 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:06:48,302 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:48,302 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:48,304 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:48,305 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:48,305 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:48,305 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:48,309 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:48,310 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:48,310 INFO L85 PathProgramCache]: Analyzing trace with hash -85334905, now seen corresponding path program 1 times [2025-03-09 08:06:48,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:48,310 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968286178] [2025-03-09 08:06:48,310 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:48,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:48,332 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-09 08:06:48,401 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-09 08:06:48,401 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:48,401 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:48,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:48,913 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:48,913 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [968286178] [2025-03-09 08:06:48,913 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [968286178] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:48,913 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:48,913 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 08:06:48,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [251780141] [2025-03-09 08:06:48,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:48,914 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:48,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:48,914 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 08:06:48,914 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2025-03-09 08:06:48,914 INFO L87 Difference]: Start difference. First operand 440 states and 622 transitions. cyclomatic complexity: 185 Second operand has 9 states, 9 states have (on average 8.666666666666666) internal successors, (78), 9 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:49,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:49,666 INFO L93 Difference]: Finished difference Result 433 states and 612 transitions. [2025-03-09 08:06:49,667 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 433 states and 612 transitions. [2025-03-09 08:06:49,668 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 426 [2025-03-09 08:06:49,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 433 states to 433 states and 612 transitions. [2025-03-09 08:06:49,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 433 [2025-03-09 08:06:49,670 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 433 [2025-03-09 08:06:49,670 INFO L73 IsDeterministic]: Start isDeterministic. Operand 433 states and 612 transitions. [2025-03-09 08:06:49,671 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:49,671 INFO L218 hiAutomatonCegarLoop]: Abstraction has 433 states and 612 transitions. [2025-03-09 08:06:49,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 433 states and 612 transitions. [2025-03-09 08:06:49,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 433 to 431. [2025-03-09 08:06:49,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 431 states, 427 states have (on average 1.4121779859484778) internal successors, (603), 426 states have internal predecessors, (603), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:49,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 431 states to 431 states and 609 transitions. [2025-03-09 08:06:49,677 INFO L240 hiAutomatonCegarLoop]: Abstraction has 431 states and 609 transitions. [2025-03-09 08:06:49,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-09 08:06:49,679 INFO L432 stractBuchiCegarLoop]: Abstraction has 431 states and 609 transitions. [2025-03-09 08:06:49,679 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-09 08:06:49,679 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 431 states and 609 transitions. [2025-03-09 08:06:49,680 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 424 [2025-03-09 08:06:49,682 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:49,682 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:49,682 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:49,682 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:49,682 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:49,683 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:49,683 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:49,683 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 12 times [2025-03-09 08:06:49,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:49,684 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452645990] [2025-03-09 08:06:49,684 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 08:06:49,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:49,689 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:49,691 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:49,691 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 08:06:49,691 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:49,691 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:49,694 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:49,695 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:49,695 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:49,695 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:49,700 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:49,701 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:49,701 INFO L85 PathProgramCache]: Analyzing trace with hash -714251294, now seen corresponding path program 1 times [2025-03-09 08:06:49,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:49,701 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2103058888] [2025-03-09 08:06:49,702 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:49,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:49,723 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-09 08:06:49,752 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-09 08:06:49,755 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:49,755 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:49,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:49,915 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:49,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2103058888] [2025-03-09 08:06:49,915 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2103058888] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:49,915 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:49,915 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 08:06:49,916 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [775985399] [2025-03-09 08:06:49,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:49,916 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:49,916 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:49,917 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 08:06:49,917 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2025-03-09 08:06:49,917 INFO L87 Difference]: Start difference. First operand 431 states and 609 transitions. cyclomatic complexity: 181 Second operand has 9 states, 9 states have (on average 8.666666666666666) internal successors, (78), 9 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:50,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:50,393 INFO L93 Difference]: Finished difference Result 444 states and 625 transitions. [2025-03-09 08:06:50,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 444 states and 625 transitions. [2025-03-09 08:06:50,395 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 437 [2025-03-09 08:06:50,397 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 444 states to 444 states and 625 transitions. [2025-03-09 08:06:50,397 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 444 [2025-03-09 08:06:50,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 444 [2025-03-09 08:06:50,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 444 states and 625 transitions. [2025-03-09 08:06:50,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:50,398 INFO L218 hiAutomatonCegarLoop]: Abstraction has 444 states and 625 transitions. [2025-03-09 08:06:50,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 444 states and 625 transitions. [2025-03-09 08:06:50,402 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 444 to 434. [2025-03-09 08:06:50,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 434 states, 430 states have (on average 1.4116279069767441) internal successors, (607), 429 states have internal predecessors, (607), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:50,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 434 states to 434 states and 613 transitions. [2025-03-09 08:06:50,404 INFO L240 hiAutomatonCegarLoop]: Abstraction has 434 states and 613 transitions. [2025-03-09 08:06:50,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-09 08:06:50,406 INFO L432 stractBuchiCegarLoop]: Abstraction has 434 states and 613 transitions. [2025-03-09 08:06:50,406 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-09 08:06:50,406 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 434 states and 613 transitions. [2025-03-09 08:06:50,407 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 427 [2025-03-09 08:06:50,407 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:50,407 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:50,408 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:50,408 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:50,408 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:50,408 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise42#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:50,409 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:50,409 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 13 times [2025-03-09 08:06:50,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:50,409 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850583813] [2025-03-09 08:06:50,409 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 08:06:50,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:50,414 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:50,415 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:50,416 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:50,416 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:50,416 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:50,418 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:50,419 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:50,419 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:50,419 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:50,423 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:50,423 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:50,423 INFO L85 PathProgramCache]: Analyzing trace with hash 772063245, now seen corresponding path program 1 times [2025-03-09 08:06:50,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:50,423 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840958689] [2025-03-09 08:06:50,424 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:50,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:50,448 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-09 08:06:50,499 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-09 08:06:50,499 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:50,499 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:50,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:50,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:50,668 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1840958689] [2025-03-09 08:06:50,668 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1840958689] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:50,668 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:50,668 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 08:06:50,668 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [551831167] [2025-03-09 08:06:50,668 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:50,668 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:50,668 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:50,668 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 08:06:50,668 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-09 08:06:50,669 INFO L87 Difference]: Start difference. First operand 434 states and 613 transitions. cyclomatic complexity: 182 Second operand has 9 states, 9 states have (on average 8.666666666666666) internal successors, (78), 9 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:51,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:51,438 INFO L93 Difference]: Finished difference Result 454 states and 639 transitions. [2025-03-09 08:06:51,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 639 transitions. [2025-03-09 08:06:51,440 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 447 [2025-03-09 08:06:51,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 639 transitions. [2025-03-09 08:06:51,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 [2025-03-09 08:06:51,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 [2025-03-09 08:06:51,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 639 transitions. [2025-03-09 08:06:51,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:51,443 INFO L218 hiAutomatonCegarLoop]: Abstraction has 454 states and 639 transitions. [2025-03-09 08:06:51,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 639 transitions. [2025-03-09 08:06:51,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 434. [2025-03-09 08:06:51,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 434 states, 430 states have (on average 1.4116279069767441) internal successors, (607), 429 states have internal predecessors, (607), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:51,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 434 states to 434 states and 613 transitions. [2025-03-09 08:06:51,448 INFO L240 hiAutomatonCegarLoop]: Abstraction has 434 states and 613 transitions. [2025-03-09 08:06:51,449 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:06:51,449 INFO L432 stractBuchiCegarLoop]: Abstraction has 434 states and 613 transitions. [2025-03-09 08:06:51,450 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-09 08:06:51,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 434 states and 613 transitions. [2025-03-09 08:06:51,450 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 427 [2025-03-09 08:06:51,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:51,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:51,451 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:51,451 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:51,451 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:51,451 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise42#1;assume main_#t~bitwise42#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise44#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:51,452 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:51,452 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 14 times [2025-03-09 08:06:51,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:51,452 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454527654] [2025-03-09 08:06:51,452 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 08:06:51,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:51,458 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:51,460 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:51,460 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:06:51,460 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:51,460 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:51,462 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:51,463 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:51,463 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:51,463 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:51,467 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:51,469 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:51,469 INFO L85 PathProgramCache]: Analyzing trace with hash -860680879, now seen corresponding path program 1 times [2025-03-09 08:06:51,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:51,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1838079044] [2025-03-09 08:06:51,470 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:51,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:51,503 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-09 08:06:51,606 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-09 08:06:51,606 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:51,606 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:52,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:52,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:52,005 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1838079044] [2025-03-09 08:06:52,005 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1838079044] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:52,005 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:52,005 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 08:06:52,005 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [430655633] [2025-03-09 08:06:52,005 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:52,006 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:52,006 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:52,006 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 08:06:52,006 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-09 08:06:52,006 INFO L87 Difference]: Start difference. First operand 434 states and 613 transitions. cyclomatic complexity: 182 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:52,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:52,903 INFO L93 Difference]: Finished difference Result 445 states and 626 transitions. [2025-03-09 08:06:52,903 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 445 states and 626 transitions. [2025-03-09 08:06:52,904 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 438 [2025-03-09 08:06:52,906 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 445 states to 445 states and 626 transitions. [2025-03-09 08:06:52,906 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 445 [2025-03-09 08:06:52,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 445 [2025-03-09 08:06:52,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 445 states and 626 transitions. [2025-03-09 08:06:52,907 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:52,907 INFO L218 hiAutomatonCegarLoop]: Abstraction has 445 states and 626 transitions. [2025-03-09 08:06:52,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 445 states and 626 transitions. [2025-03-09 08:06:52,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 445 to 437. [2025-03-09 08:06:52,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 437 states, 433 states have (on average 1.4087759815242493) internal successors, (610), 432 states have internal predecessors, (610), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:52,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 437 states to 437 states and 616 transitions. [2025-03-09 08:06:52,912 INFO L240 hiAutomatonCegarLoop]: Abstraction has 437 states and 616 transitions. [2025-03-09 08:06:52,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:06:52,914 INFO L432 stractBuchiCegarLoop]: Abstraction has 437 states and 616 transitions. [2025-03-09 08:06:52,914 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-09 08:06:52,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 437 states and 616 transitions. [2025-03-09 08:06:52,915 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 430 [2025-03-09 08:06:52,915 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:52,915 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:52,915 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:52,915 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:52,916 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:52,916 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise42#1;assume main_#t~bitwise42#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:52,916 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:52,916 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 15 times [2025-03-09 08:06:52,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:52,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [676415147] [2025-03-09 08:06:52,916 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 08:06:52,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:52,922 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:52,923 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:52,924 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 08:06:52,924 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:52,924 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:52,926 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:52,927 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:52,927 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:52,927 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:52,931 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:52,931 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:52,931 INFO L85 PathProgramCache]: Analyzing trace with hash -119795307, now seen corresponding path program 1 times [2025-03-09 08:06:52,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:52,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047341167] [2025-03-09 08:06:52,931 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:52,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:52,953 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-09 08:06:53,008 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-09 08:06:53,008 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:53,008 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:53,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:53,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:53,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2047341167] [2025-03-09 08:06:53,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2047341167] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:53,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:53,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-09 08:06:53,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385462917] [2025-03-09 08:06:53,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:53,390 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:53,390 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:53,390 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-09 08:06:53,390 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2025-03-09 08:06:53,390 INFO L87 Difference]: Start difference. First operand 437 states and 616 transitions. cyclomatic complexity: 182 Second operand has 13 states, 13 states have (on average 6.076923076923077) internal successors, (79), 13 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:54,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:54,214 INFO L93 Difference]: Finished difference Result 492 states and 697 transitions. [2025-03-09 08:06:54,214 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 492 states and 697 transitions. [2025-03-09 08:06:54,215 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 485 [2025-03-09 08:06:54,217 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 492 states to 492 states and 697 transitions. [2025-03-09 08:06:54,217 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 492 [2025-03-09 08:06:54,218 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 492 [2025-03-09 08:06:54,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 492 states and 697 transitions. [2025-03-09 08:06:54,219 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:54,219 INFO L218 hiAutomatonCegarLoop]: Abstraction has 492 states and 697 transitions. [2025-03-09 08:06:54,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 492 states and 697 transitions. [2025-03-09 08:06:54,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 492 to 445. [2025-03-09 08:06:54,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 445 states, 441 states have (on average 1.4081632653061225) internal successors, (621), 440 states have internal predecessors, (621), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:54,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 445 states to 445 states and 627 transitions. [2025-03-09 08:06:54,225 INFO L240 hiAutomatonCegarLoop]: Abstraction has 445 states and 627 transitions. [2025-03-09 08:06:54,225 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-09 08:06:54,226 INFO L432 stractBuchiCegarLoop]: Abstraction has 445 states and 627 transitions. [2025-03-09 08:06:54,226 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-09 08:06:54,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 445 states and 627 transitions. [2025-03-09 08:06:54,227 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 438 [2025-03-09 08:06:54,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:54,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:54,227 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:54,227 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:54,227 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:54,228 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise44#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:54,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:54,228 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 16 times [2025-03-09 08:06:54,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:54,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765821758] [2025-03-09 08:06:54,228 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 08:06:54,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:54,234 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-09 08:06:54,235 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:54,235 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 08:06:54,236 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:54,236 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:54,237 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:54,238 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:54,238 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:54,238 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:54,242 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:54,242 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:54,242 INFO L85 PathProgramCache]: Analyzing trace with hash 1208418347, now seen corresponding path program 1 times [2025-03-09 08:06:54,242 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:54,242 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129549635] [2025-03-09 08:06:54,242 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:54,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:54,263 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-09 08:06:54,274 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-09 08:06:54,275 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:54,275 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:54,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:54,460 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:54,460 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129549635] [2025-03-09 08:06:54,460 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1129549635] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:54,460 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:54,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-09 08:06:54,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [233967045] [2025-03-09 08:06:54,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:54,461 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:54,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:54,461 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-09 08:06:54,461 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2025-03-09 08:06:54,461 INFO L87 Difference]: Start difference. First operand 445 states and 627 transitions. cyclomatic complexity: 185 Second operand has 10 states, 10 states have (on average 7.9) internal successors, (79), 10 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:55,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:55,281 INFO L93 Difference]: Finished difference Result 461 states and 648 transitions. [2025-03-09 08:06:55,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 461 states and 648 transitions. [2025-03-09 08:06:55,283 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 454 [2025-03-09 08:06:55,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 461 states to 461 states and 648 transitions. [2025-03-09 08:06:55,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 461 [2025-03-09 08:06:55,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 461 [2025-03-09 08:06:55,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 461 states and 648 transitions. [2025-03-09 08:06:55,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:55,286 INFO L218 hiAutomatonCegarLoop]: Abstraction has 461 states and 648 transitions. [2025-03-09 08:06:55,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 461 states and 648 transitions. [2025-03-09 08:06:55,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 461 to 455. [2025-03-09 08:06:55,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 455 states, 451 states have (on average 1.4035476718403548) internal successors, (633), 450 states have internal predecessors, (633), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:55,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 455 states to 455 states and 639 transitions. [2025-03-09 08:06:55,291 INFO L240 hiAutomatonCegarLoop]: Abstraction has 455 states and 639 transitions. [2025-03-09 08:06:55,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:06:55,294 INFO L432 stractBuchiCegarLoop]: Abstraction has 455 states and 639 transitions. [2025-03-09 08:06:55,294 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-09 08:06:55,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 455 states and 639 transitions. [2025-03-09 08:06:55,295 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 448 [2025-03-09 08:06:55,295 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:55,295 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:55,295 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:55,295 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:55,296 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:55,296 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise42#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise44#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:55,296 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:55,296 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 17 times [2025-03-09 08:06:55,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:55,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8776828] [2025-03-09 08:06:55,312 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 08:06:55,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:55,318 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:55,319 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:55,319 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:06:55,319 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:55,319 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:55,322 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:55,323 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:55,323 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:55,323 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:55,327 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:55,327 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:55,327 INFO L85 PathProgramCache]: Analyzing trace with hash 39528800, now seen corresponding path program 1 times [2025-03-09 08:06:55,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:55,327 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733654643] [2025-03-09 08:06:55,327 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:55,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:55,350 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-09 08:06:55,409 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-09 08:06:55,409 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:55,409 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:55,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:55,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:55,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [733654643] [2025-03-09 08:06:55,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [733654643] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:55,591 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:55,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-09 08:06:55,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [63190266] [2025-03-09 08:06:55,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:55,591 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:55,591 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:55,592 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-09 08:06:55,592 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2025-03-09 08:06:55,592 INFO L87 Difference]: Start difference. First operand 455 states and 639 transitions. cyclomatic complexity: 187 Second operand has 10 states, 10 states have (on average 7.9) internal successors, (79), 10 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:56,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:56,387 INFO L93 Difference]: Finished difference Result 470 states and 660 transitions. [2025-03-09 08:06:56,387 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 470 states and 660 transitions. [2025-03-09 08:06:56,388 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 463 [2025-03-09 08:06:56,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 470 states to 470 states and 660 transitions. [2025-03-09 08:06:56,390 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 470 [2025-03-09 08:06:56,390 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 470 [2025-03-09 08:06:56,390 INFO L73 IsDeterministic]: Start isDeterministic. Operand 470 states and 660 transitions. [2025-03-09 08:06:56,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:56,391 INFO L218 hiAutomatonCegarLoop]: Abstraction has 470 states and 660 transitions. [2025-03-09 08:06:56,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 470 states and 660 transitions. [2025-03-09 08:06:56,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 470 to 455. [2025-03-09 08:06:56,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 455 states, 451 states have (on average 1.4035476718403548) internal successors, (633), 450 states have internal predecessors, (633), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:56,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 455 states to 455 states and 639 transitions. [2025-03-09 08:06:56,401 INFO L240 hiAutomatonCegarLoop]: Abstraction has 455 states and 639 transitions. [2025-03-09 08:06:56,401 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:06:56,402 INFO L432 stractBuchiCegarLoop]: Abstraction has 455 states and 639 transitions. [2025-03-09 08:06:56,402 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-09 08:06:56,402 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 455 states and 639 transitions. [2025-03-09 08:06:56,418 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 448 [2025-03-09 08:06:56,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:56,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:56,419 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:56,419 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:56,419 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:56,420 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise42#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:56,421 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:56,421 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 18 times [2025-03-09 08:06:56,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:56,421 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120848327] [2025-03-09 08:06:56,421 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 08:06:56,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:56,431 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:56,434 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:56,434 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 08:06:56,434 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:56,434 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:56,436 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:56,437 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:56,437 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:56,437 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:56,441 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:56,442 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:56,442 INFO L85 PathProgramCache]: Analyzing trace with hash 1348362052, now seen corresponding path program 1 times [2025-03-09 08:06:56,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:56,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1275290850] [2025-03-09 08:06:56,442 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:56,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:56,462 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-09 08:06:56,499 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-09 08:06:56,499 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:56,499 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:56,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:56,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:56,636 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1275290850] [2025-03-09 08:06:56,636 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1275290850] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:56,636 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:56,637 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-09 08:06:56,637 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [884954705] [2025-03-09 08:06:56,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:56,637 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:56,638 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:56,638 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-09 08:06:56,638 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-09 08:06:56,638 INFO L87 Difference]: Start difference. First operand 455 states and 639 transitions. cyclomatic complexity: 187 Second operand has 7 states, 7 states have (on average 11.285714285714286) internal successors, (79), 7 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:57,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:57,189 INFO L93 Difference]: Finished difference Result 460 states and 645 transitions. [2025-03-09 08:06:57,189 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 460 states and 645 transitions. [2025-03-09 08:06:57,190 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 453 [2025-03-09 08:06:57,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 460 states to 460 states and 645 transitions. [2025-03-09 08:06:57,192 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 460 [2025-03-09 08:06:57,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 460 [2025-03-09 08:06:57,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 460 states and 645 transitions. [2025-03-09 08:06:57,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:57,192 INFO L218 hiAutomatonCegarLoop]: Abstraction has 460 states and 645 transitions. [2025-03-09 08:06:57,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 460 states and 645 transitions. [2025-03-09 08:06:57,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 460 to 459. [2025-03-09 08:06:57,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 459 states, 455 states have (on average 1.402197802197802) internal successors, (638), 454 states have internal predecessors, (638), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:57,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 459 states to 459 states and 644 transitions. [2025-03-09 08:06:57,200 INFO L240 hiAutomatonCegarLoop]: Abstraction has 459 states and 644 transitions. [2025-03-09 08:06:57,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-09 08:06:57,201 INFO L432 stractBuchiCegarLoop]: Abstraction has 459 states and 644 transitions. [2025-03-09 08:06:57,201 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-09 08:06:57,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 459 states and 644 transitions. [2025-03-09 08:06:57,202 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 452 [2025-03-09 08:06:57,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:57,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:57,203 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:57,203 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:57,203 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:57,203 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:57,203 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:57,203 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 19 times [2025-03-09 08:06:57,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:57,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267737153] [2025-03-09 08:06:57,204 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 08:06:57,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:57,209 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:57,210 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:57,210 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:57,211 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:57,211 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:57,213 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:57,213 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:57,213 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:57,213 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:57,217 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:57,218 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:57,218 INFO L85 PathProgramCache]: Analyzing trace with hash -1973068800, now seen corresponding path program 1 times [2025-03-09 08:06:57,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:57,219 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1933274046] [2025-03-09 08:06:57,219 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:57,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:57,239 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-09 08:06:57,306 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-09 08:06:57,306 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:57,306 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:57,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:57,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:57,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1933274046] [2025-03-09 08:06:57,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1933274046] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:57,520 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:57,520 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-09 08:06:57,520 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1196733213] [2025-03-09 08:06:57,520 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:57,521 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:57,521 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:57,522 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-09 08:06:57,522 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-09 08:06:57,522 INFO L87 Difference]: Start difference. First operand 459 states and 644 transitions. cyclomatic complexity: 188 Second operand has 7 states, 7 states have (on average 11.285714285714286) internal successors, (79), 7 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:06:58,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:06:58,048 INFO L93 Difference]: Finished difference Result 465 states and 649 transitions. [2025-03-09 08:06:58,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 465 states and 649 transitions. [2025-03-09 08:06:58,049 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 458 [2025-03-09 08:06:58,050 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 465 states to 465 states and 649 transitions. [2025-03-09 08:06:58,050 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 465 [2025-03-09 08:06:58,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 465 [2025-03-09 08:06:58,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 465 states and 649 transitions. [2025-03-09 08:06:58,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:06:58,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 465 states and 649 transitions. [2025-03-09 08:06:58,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 465 states and 649 transitions. [2025-03-09 08:06:58,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 465 to 459. [2025-03-09 08:06:58,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 459 states, 455 states have (on average 1.4) internal successors, (637), 454 states have internal predecessors, (637), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:06:58,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 459 states to 459 states and 643 transitions. [2025-03-09 08:06:58,056 INFO L240 hiAutomatonCegarLoop]: Abstraction has 459 states and 643 transitions. [2025-03-09 08:06:58,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-09 08:06:58,057 INFO L432 stractBuchiCegarLoop]: Abstraction has 459 states and 643 transitions. [2025-03-09 08:06:58,057 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-09 08:06:58,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 459 states and 643 transitions. [2025-03-09 08:06:58,058 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 452 [2025-03-09 08:06:58,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:06:58,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:06:58,058 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:06:58,058 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:06:58,058 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:06:58,059 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise42#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:06:58,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:58,060 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 20 times [2025-03-09 08:06:58,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:58,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [784976434] [2025-03-09 08:06:58,060 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 08:06:58,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:58,066 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:58,067 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:58,067 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:06:58,067 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:58,067 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:06:58,069 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:06:58,070 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:06:58,070 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:58,070 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:06:58,074 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:06:58,075 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:06:58,075 INFO L85 PathProgramCache]: Analyzing trace with hash 514785455, now seen corresponding path program 1 times [2025-03-09 08:06:58,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:06:58,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [826519998] [2025-03-09 08:06:58,075 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:06:58,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:06:58,097 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:06:58,140 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:06:58,140 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:06:58,140 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:06:58,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:06:58,451 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:06:58,451 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [826519998] [2025-03-09 08:06:58,451 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [826519998] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:06:58,451 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:06:58,451 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-09 08:06:58,451 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1772187380] [2025-03-09 08:06:58,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:06:58,451 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:06:58,451 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:06:58,452 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-09 08:06:58,452 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-03-09 08:06:58,452 INFO L87 Difference]: Start difference. First operand 459 states and 643 transitions. cyclomatic complexity: 187 Second operand has 10 states, 10 states have (on average 8.0) internal successors, (80), 10 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:07:00,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:07:00,174 INFO L93 Difference]: Finished difference Result 477 states and 665 transitions. [2025-03-09 08:07:00,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 477 states and 665 transitions. [2025-03-09 08:07:00,175 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 470 [2025-03-09 08:07:00,177 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 477 states to 477 states and 665 transitions. [2025-03-09 08:07:00,177 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 477 [2025-03-09 08:07:00,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 477 [2025-03-09 08:07:00,177 INFO L73 IsDeterministic]: Start isDeterministic. Operand 477 states and 665 transitions. [2025-03-09 08:07:00,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:07:00,177 INFO L218 hiAutomatonCegarLoop]: Abstraction has 477 states and 665 transitions. [2025-03-09 08:07:00,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 477 states and 665 transitions. [2025-03-09 08:07:00,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 477 to 461. [2025-03-09 08:07:00,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 461 states, 457 states have (on average 1.3982494529540481) internal successors, (639), 456 states have internal predecessors, (639), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:07:00,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 645 transitions. [2025-03-09 08:07:00,182 INFO L240 hiAutomatonCegarLoop]: Abstraction has 461 states and 645 transitions. [2025-03-09 08:07:00,183 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:07:00,183 INFO L432 stractBuchiCegarLoop]: Abstraction has 461 states and 645 transitions. [2025-03-09 08:07:00,183 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-03-09 08:07:00,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 461 states and 645 transitions. [2025-03-09 08:07:00,184 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 454 [2025-03-09 08:07:00,184 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:07:00,184 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:07:00,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:07:00,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:07:00,185 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:07:00,185 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise42#1;assume main_#t~bitwise42#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:07:00,186 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:00,186 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 21 times [2025-03-09 08:07:00,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:00,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2045468708] [2025-03-09 08:07:00,186 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 08:07:00,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:00,191 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:07:00,193 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:00,193 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 08:07:00,193 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:00,193 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:07:00,194 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:07:00,196 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:00,196 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:00,196 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:00,202 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:07:00,203 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:00,203 INFO L85 PathProgramCache]: Analyzing trace with hash -1319538255, now seen corresponding path program 1 times [2025-03-09 08:07:00,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:00,203 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416322547] [2025-03-09 08:07:00,203 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:07:00,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:00,224 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:07:00,267 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:07:00,267 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:00,267 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:07:00,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:07:00,576 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:07:00,576 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416322547] [2025-03-09 08:07:00,576 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416322547] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:07:00,576 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:07:00,576 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-09 08:07:00,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1974298455] [2025-03-09 08:07:00,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:07:00,576 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:07:00,577 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:07:00,577 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-09 08:07:00,577 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-09 08:07:00,577 INFO L87 Difference]: Start difference. First operand 461 states and 645 transitions. cyclomatic complexity: 187 Second operand has 13 states, 13 states have (on average 6.153846153846154) internal successors, (80), 13 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:07:01,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:07:01,353 INFO L93 Difference]: Finished difference Result 473 states and 660 transitions. [2025-03-09 08:07:01,353 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 473 states and 660 transitions. [2025-03-09 08:07:01,354 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 466 [2025-03-09 08:07:01,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 473 states to 473 states and 660 transitions. [2025-03-09 08:07:01,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 473 [2025-03-09 08:07:01,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 473 [2025-03-09 08:07:01,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 473 states and 660 transitions. [2025-03-09 08:07:01,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:07:01,357 INFO L218 hiAutomatonCegarLoop]: Abstraction has 473 states and 660 transitions. [2025-03-09 08:07:01,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 473 states and 660 transitions. [2025-03-09 08:07:01,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 473 to 466. [2025-03-09 08:07:01,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 466 states, 462 states have (on average 1.3982683982683983) internal successors, (646), 461 states have internal predecessors, (646), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:07:01,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 466 states to 466 states and 652 transitions. [2025-03-09 08:07:01,361 INFO L240 hiAutomatonCegarLoop]: Abstraction has 466 states and 652 transitions. [2025-03-09 08:07:01,361 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-09 08:07:01,361 INFO L432 stractBuchiCegarLoop]: Abstraction has 466 states and 652 transitions. [2025-03-09 08:07:01,361 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-03-09 08:07:01,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 466 states and 652 transitions. [2025-03-09 08:07:01,362 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 459 [2025-03-09 08:07:01,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:07:01,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:07:01,363 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:07:01,363 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:07:01,363 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:07:01,363 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise42#1;assume main_#t~bitwise42#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 32 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:07:01,363 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:01,364 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 22 times [2025-03-09 08:07:01,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:01,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278538486] [2025-03-09 08:07:01,364 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-09 08:07:01,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:01,369 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-09 08:07:01,369 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:01,370 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-09 08:07:01,370 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:01,370 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:07:01,371 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:07:01,371 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:01,372 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:01,372 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:01,375 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:07:01,376 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:01,376 INFO L85 PathProgramCache]: Analyzing trace with hash 361446602, now seen corresponding path program 1 times [2025-03-09 08:07:01,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:01,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850873204] [2025-03-09 08:07:01,376 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:07:01,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:01,404 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:07:01,557 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:07:01,558 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:01,558 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:07:02,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:07:02,162 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:07:02,162 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1850873204] [2025-03-09 08:07:02,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1850873204] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:07:02,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:07:02,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2025-03-09 08:07:02,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2133553772] [2025-03-09 08:07:02,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:07:02,163 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:07:02,163 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:07:02,163 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2025-03-09 08:07:02,163 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2025-03-09 08:07:02,163 INFO L87 Difference]: Start difference. First operand 466 states and 652 transitions. cyclomatic complexity: 189 Second operand has 17 states, 17 states have (on average 4.705882352941177) internal successors, (80), 17 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:07:03,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:07:03,708 INFO L93 Difference]: Finished difference Result 485 states and 679 transitions. [2025-03-09 08:07:03,708 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 485 states and 679 transitions. [2025-03-09 08:07:03,709 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 478 [2025-03-09 08:07:03,711 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 485 states to 485 states and 679 transitions. [2025-03-09 08:07:03,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 485 [2025-03-09 08:07:03,711 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 485 [2025-03-09 08:07:03,711 INFO L73 IsDeterministic]: Start isDeterministic. Operand 485 states and 679 transitions. [2025-03-09 08:07:03,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:07:03,711 INFO L218 hiAutomatonCegarLoop]: Abstraction has 485 states and 679 transitions. [2025-03-09 08:07:03,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 485 states and 679 transitions. [2025-03-09 08:07:03,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 485 to 471. [2025-03-09 08:07:03,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 471 states, 467 states have (on average 1.3982869379014988) internal successors, (653), 466 states have internal predecessors, (653), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:07:03,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 659 transitions. [2025-03-09 08:07:03,715 INFO L240 hiAutomatonCegarLoop]: Abstraction has 471 states and 659 transitions. [2025-03-09 08:07:03,716 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2025-03-09 08:07:03,716 INFO L432 stractBuchiCegarLoop]: Abstraction has 471 states and 659 transitions. [2025-03-09 08:07:03,716 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-03-09 08:07:03,716 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 471 states and 659 transitions. [2025-03-09 08:07:03,717 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 464 [2025-03-09 08:07:03,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:07:03,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:07:03,717 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:07:03,717 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:07:03,718 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:07:03,718 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise42#1;assume main_#t~bitwise42#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:07:03,718 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:03,718 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 23 times [2025-03-09 08:07:03,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:03,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [939497677] [2025-03-09 08:07:03,719 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-09 08:07:03,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:03,724 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:07:03,726 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:03,726 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:07:03,726 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:03,726 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:07:03,727 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:07:03,728 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:03,728 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:03,728 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:03,731 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:07:03,731 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:03,731 INFO L85 PathProgramCache]: Analyzing trace with hash -1621910818, now seen corresponding path program 1 times [2025-03-09 08:07:03,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:03,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [128656250] [2025-03-09 08:07:03,732 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:07:03,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:03,752 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:07:03,859 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:07:03,859 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:03,859 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:07:04,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:07:04,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:07:04,295 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [128656250] [2025-03-09 08:07:04,295 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [128656250] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:07:04,295 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:07:04,295 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2025-03-09 08:07:04,295 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [603572678] [2025-03-09 08:07:04,295 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:07:04,296 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:07:04,296 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:07:04,296 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2025-03-09 08:07:04,296 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=265, Unknown=0, NotChecked=0, Total=306 [2025-03-09 08:07:04,296 INFO L87 Difference]: Start difference. First operand 471 states and 659 transitions. cyclomatic complexity: 191 Second operand has 18 states, 18 states have (on average 4.444444444444445) internal successors, (80), 18 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:07:07,342 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.03s for a HTC check with result INVALID. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2025-03-09 08:07:07,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:07:07,564 INFO L93 Difference]: Finished difference Result 583 states and 820 transitions. [2025-03-09 08:07:07,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 583 states and 820 transitions. [2025-03-09 08:07:07,565 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 576 [2025-03-09 08:07:07,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 583 states to 583 states and 820 transitions. [2025-03-09 08:07:07,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 583 [2025-03-09 08:07:07,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 583 [2025-03-09 08:07:07,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 583 states and 820 transitions. [2025-03-09 08:07:07,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:07:07,567 INFO L218 hiAutomatonCegarLoop]: Abstraction has 583 states and 820 transitions. [2025-03-09 08:07:07,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 583 states and 820 transitions. [2025-03-09 08:07:07,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 583 to 484. [2025-03-09 08:07:07,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 484 states, 480 states have (on average 1.3979166666666667) internal successors, (671), 479 states have internal predecessors, (671), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:07:07,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 484 states to 484 states and 677 transitions. [2025-03-09 08:07:07,572 INFO L240 hiAutomatonCegarLoop]: Abstraction has 484 states and 677 transitions. [2025-03-09 08:07:07,572 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2025-03-09 08:07:07,572 INFO L432 stractBuchiCegarLoop]: Abstraction has 484 states and 677 transitions. [2025-03-09 08:07:07,572 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-03-09 08:07:07,573 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 484 states and 677 transitions. [2025-03-09 08:07:07,573 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 477 [2025-03-09 08:07:07,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:07:07,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:07:07,574 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:07:07,574 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:07:07,574 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:07:07,574 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise41#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:07:07,574 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:07,575 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 24 times [2025-03-09 08:07:07,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:07,575 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965777599] [2025-03-09 08:07:07,575 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-09 08:07:07,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:07,580 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:07:07,580 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:07,581 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-09 08:07:07,581 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:07,581 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:07:07,582 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:07:07,582 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:07,583 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:07,583 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:07,586 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:07:07,586 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:07,586 INFO L85 PathProgramCache]: Analyzing trace with hash -1904344252, now seen corresponding path program 1 times [2025-03-09 08:07:07,586 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:07,586 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811748899] [2025-03-09 08:07:07,586 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:07:07,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:07,606 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:07:07,652 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:07:07,652 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:07,653 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:07:07,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:07:07,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:07:07,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [811748899] [2025-03-09 08:07:07,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [811748899] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:07:07,995 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:07:07,995 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-09 08:07:07,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414682077] [2025-03-09 08:07:07,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:07:07,996 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:07:07,996 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:07:07,996 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-09 08:07:07,996 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-03-09 08:07:07,996 INFO L87 Difference]: Start difference. First operand 484 states and 677 transitions. cyclomatic complexity: 196 Second operand has 10 states, 10 states have (on average 8.0) internal successors, (80), 10 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:07:08,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:07:08,760 INFO L93 Difference]: Finished difference Result 491 states and 687 transitions. [2025-03-09 08:07:08,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 491 states and 687 transitions. [2025-03-09 08:07:08,762 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 484 [2025-03-09 08:07:08,763 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 491 states to 491 states and 687 transitions. [2025-03-09 08:07:08,763 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 491 [2025-03-09 08:07:08,763 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 491 [2025-03-09 08:07:08,763 INFO L73 IsDeterministic]: Start isDeterministic. Operand 491 states and 687 transitions. [2025-03-09 08:07:08,764 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:07:08,764 INFO L218 hiAutomatonCegarLoop]: Abstraction has 491 states and 687 transitions. [2025-03-09 08:07:08,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 491 states and 687 transitions. [2025-03-09 08:07:08,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 491 to 484. [2025-03-09 08:07:08,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 484 states, 480 states have (on average 1.3979166666666667) internal successors, (671), 479 states have internal predecessors, (671), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:07:08,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 484 states to 484 states and 677 transitions. [2025-03-09 08:07:08,768 INFO L240 hiAutomatonCegarLoop]: Abstraction has 484 states and 677 transitions. [2025-03-09 08:07:08,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:07:08,770 INFO L432 stractBuchiCegarLoop]: Abstraction has 484 states and 677 transitions. [2025-03-09 08:07:08,770 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-03-09 08:07:08,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 484 states and 677 transitions. [2025-03-09 08:07:08,771 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 477 [2025-03-09 08:07:08,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:07:08,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:07:08,772 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:07:08,772 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:07:08,772 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:07:08,772 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise41#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise42#1;assume main_#t~bitwise42#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise44#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:07:08,773 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:08,773 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 25 times [2025-03-09 08:07:08,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:08,773 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021930733] [2025-03-09 08:07:08,773 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-09 08:07:08,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:08,779 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:07:08,780 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:08,780 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:08,780 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:08,780 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:07:08,782 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:07:08,782 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:08,783 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:08,783 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:08,787 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:07:08,787 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:08,788 INFO L85 PathProgramCache]: Analyzing trace with hash -1838282536, now seen corresponding path program 1 times [2025-03-09 08:07:08,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:08,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328812009] [2025-03-09 08:07:08,788 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:07:08,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:08,820 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:07:08,885 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:07:08,886 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:08,886 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:07:09,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:07:09,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:07:09,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328812009] [2025-03-09 08:07:09,055 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328812009] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:07:09,055 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:07:09,055 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2025-03-09 08:07:09,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375669904] [2025-03-09 08:07:09,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:07:09,056 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:07:09,056 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:07:09,056 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-09 08:07:09,056 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2025-03-09 08:07:09,056 INFO L87 Difference]: Start difference. First operand 484 states and 677 transitions. cyclomatic complexity: 196 Second operand has 8 states, 8 states have (on average 10.0) internal successors, (80), 8 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:07:21,388 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 12.00s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2025-03-09 08:07:21,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:07:21,581 INFO L93 Difference]: Finished difference Result 580 states and 813 transitions. [2025-03-09 08:07:21,581 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 580 states and 813 transitions. [2025-03-09 08:07:21,583 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 573 [2025-03-09 08:07:21,585 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 580 states to 580 states and 813 transitions. [2025-03-09 08:07:21,585 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 580 [2025-03-09 08:07:21,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 580 [2025-03-09 08:07:21,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 580 states and 813 transitions. [2025-03-09 08:07:21,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:07:21,586 INFO L218 hiAutomatonCegarLoop]: Abstraction has 580 states and 813 transitions. [2025-03-09 08:07:21,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 580 states and 813 transitions. [2025-03-09 08:07:21,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 580 to 490. [2025-03-09 08:07:21,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 490 states, 486 states have (on average 1.397119341563786) internal successors, (679), 485 states have internal predecessors, (679), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:07:21,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 490 states to 490 states and 685 transitions. [2025-03-09 08:07:21,591 INFO L240 hiAutomatonCegarLoop]: Abstraction has 490 states and 685 transitions. [2025-03-09 08:07:21,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-09 08:07:21,591 INFO L432 stractBuchiCegarLoop]: Abstraction has 490 states and 685 transitions. [2025-03-09 08:07:21,591 INFO L338 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2025-03-09 08:07:21,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 490 states and 685 transitions. [2025-03-09 08:07:21,593 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 483 [2025-03-09 08:07:21,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:07:21,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:07:21,593 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:07:21,593 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:07:21,594 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:07:21,594 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise42#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:07:21,594 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:21,594 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 26 times [2025-03-09 08:07:21,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:21,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843234273] [2025-03-09 08:07:21,594 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-09 08:07:21,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:21,600 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:07:21,601 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:21,601 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-09 08:07:21,601 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:21,601 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:07:21,602 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:07:21,603 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:21,603 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:21,603 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:21,607 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:07:21,608 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:21,608 INFO L85 PathProgramCache]: Analyzing trace with hash 427874928, now seen corresponding path program 1 times [2025-03-09 08:07:21,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:21,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793593376] [2025-03-09 08:07:21,608 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:07:21,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:21,629 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:07:21,696 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:07:21,696 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:21,697 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:07:21,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-09 08:07:21,901 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-09 08:07:21,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793593376] [2025-03-09 08:07:21,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1793593376] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-09 08:07:21,901 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-09 08:07:21,901 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-09 08:07:21,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [487761010] [2025-03-09 08:07:21,902 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-09 08:07:21,902 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-09 08:07:21,902 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-09 08:07:21,902 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-09 08:07:21,902 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-09 08:07:21,902 INFO L87 Difference]: Start difference. First operand 490 states and 685 transitions. cyclomatic complexity: 198 Second operand has 9 states, 9 states have (on average 8.88888888888889) internal successors, (80), 9 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-09 08:07:22,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-09 08:07:22,685 INFO L93 Difference]: Finished difference Result 504 states and 703 transitions. [2025-03-09 08:07:22,685 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 703 transitions. [2025-03-09 08:07:22,686 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 497 [2025-03-09 08:07:22,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 703 transitions. [2025-03-09 08:07:22,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2025-03-09 08:07:22,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2025-03-09 08:07:22,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 703 transitions. [2025-03-09 08:07:22,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-09 08:07:22,689 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 703 transitions. [2025-03-09 08:07:22,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 703 transitions. [2025-03-09 08:07:22,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 493. [2025-03-09 08:07:22,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 493 states, 489 states have (on average 1.3967280163599183) internal successors, (683), 488 states have internal predecessors, (683), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-09 08:07:22,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 493 states to 493 states and 689 transitions. [2025-03-09 08:07:22,693 INFO L240 hiAutomatonCegarLoop]: Abstraction has 493 states and 689 transitions. [2025-03-09 08:07:22,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-09 08:07:22,693 INFO L432 stractBuchiCegarLoop]: Abstraction has 493 states and 689 transitions. [2025-03-09 08:07:22,693 INFO L338 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2025-03-09 08:07:22,693 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 493 states and 689 transitions. [2025-03-09 08:07:22,694 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 486 [2025-03-09 08:07:22,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-09 08:07:22,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-09 08:07:22,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-09 08:07:22,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-09 08:07:22,695 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem3#1, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem8#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem12#1, main_#t~mem14#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem16#1, main_#t~mem18#1, main_#t~mem19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~switch29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc50#1.base, main_#t~malloc50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~mem52#1.base, main_#t~mem52#1.offset, main_#t~memset~res53#1.base, main_#t~memset~res53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~malloc59#1.base, main_#t~malloc59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~memset~res66#1.base, main_#t~memset~res66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1, main_#t~post77#1, main_#t~mem78#1.base, main_#t~mem78#1.offset, main_#t~mem79#1, main_#t~bitwise80#1, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1.base, main_#t~mem82#1.offset, main_#t~mem83#1, main_#t~post84#1, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem89#1, main_#t~mem88#1, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1, main_#t~short92#1, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1, main_#t~malloc95#1.base, main_#t~malloc95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1, main_#t~memset~res98#1.base, main_#t~memset~res98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem103#1, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1, main_#t~bitwise104#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem108#1, main_#t~mem106#1.base, main_#t~mem106#1.offset, main_#t~mem107#1, main_#t~bitwise109#1, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1.base, main_#t~mem111#1.offset, main_#t~mem112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem119#1, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~bitwise120#1, main_#t~mem121#1, main_#t~pre122#1, main_#t~mem123#1.base, main_#t~mem123#1.offset, main_#t~mem124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~post127#1, main_#t~mem131#1, main_#t~mem129#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem130#1, main_#t~mem132#1, main_#t~post133#1, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~post137#1, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~post144#1, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem150#1, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1, main_#t~ite153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~mem154#1.base, main_#t~mem154#1.offset, main_#t~mem155#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem157#1, main_#t~post158#1, main_#t~mem159#1, main_#t~mem161#1, main_#t~mem160#1, main_#t~mem162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~bitwise172#1, main_#t~bitwise173#1, main_#t~bitwise174#1, main_#t~bitwise175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~switch181#1, main_#t~mem182#1, main_#t~mem183#1, main_#t~mem184#1, main_#t~mem185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~bitwise193#1, main_#t~bitwise194#1, main_#t~bitwise195#1, main_#t~bitwise196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem202#1.base, main_#t~mem202#1.offset, main_#t~mem203#1, main_#t~bitwise204#1, main_#t~mem205#1.base, main_#t~mem205#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1.base, main_#t~mem207#1.offset, main_#t~mem208#1.base, main_#t~mem208#1.offset, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1, main_#t~mem213#1, main_#t~mem214#1, main_#t~short215#1, main_#t~mem216#1.base, main_#t~mem216#1.offset, main_#t~nondet217#1, main_#t~mem218#1.base, main_#t~mem218#1.offset, main_#t~mem219#1.base, main_#t~mem219#1.offset, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~mem221#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~short224#1, main_#t~mem225#1.base, main_#t~mem225#1.offset, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~mem228#1.base, main_#t~mem228#1.offset, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem247#1, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1, main_#t~bitwise248#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1.base, main_#t~mem250#1.offset, main_#t~mem251#1, main_#t~post252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1, main_#t~post263#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem264#1, main_#t~post265#1, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-09 08:07:22,695 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem3#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem3#1 < 1000;havoc main_#t~mem3#1;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem5#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#1(main_#t~mem6#1 * main_#t~mem7#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem6#1;havoc main_#t~mem7#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch29#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch29#1;" "main_#t~switch29#1 := main_#t~switch29#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch29#1 := main_#t~switch29#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch29#1;call main_#t~mem40#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem40#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem40#1 % 256 % 4294967296 else main_#t~mem40#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~switch29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise42#1;assume main_#t~bitwise42#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise44#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise45#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise47#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise48#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem67#1.base, main_#t~mem67#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_#t~mem68#1.base, 16 + main_#t~mem68#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1 := read~int#1(main_#t~mem70#1.base, 20 + main_#t~mem70#1.offset, 4);call write~$Pointer$#1(main_#t~mem69#1.base, main_#t~mem69#1.offset - main_#t~mem71#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1;call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_#t~mem72#1.base, 16 + main_#t~mem72#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem73#1.base, 8 + main_#t~mem73#1.offset, 4);havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem76#1 := read~int#1(main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);main_#t~post77#1 := main_#t~mem76#1;call write~int#1(1 + main_#t~post77#1, main_#t~mem75#1.base, 12 + main_#t~mem75#1.offset, 4);havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;havoc main_#t~mem76#1;havoc main_#t~post77#1;" "assume true;call main_#t~mem78#1.base, main_#t~mem78#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem79#1 := read~int#1(main_#t~mem78#1.base, 4 + main_#t~mem78#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem79#1 - 1) % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise80#1;havoc main_#t~mem78#1.base, main_#t~mem78#1.offset;havoc main_#t~mem79#1;havoc main_#t~bitwise80#1;" "assume !false;" "assume true;call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem82#1.base, main_#t~mem82#1.offset := read~$Pointer$#1(main_#t~mem81#1.base, main_#t~mem81#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem82#1.base, main_#t~mem82#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;havoc main_#t~mem82#1.base, main_#t~mem82#1.offset;call main_#t~mem83#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post84#1 := main_#t~mem83#1;call write~int#1(1 + main_#t~post84#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem83#1;havoc main_#t~post84#1;call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem85#1.base, main_#t~mem85#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem86#1.base != 0 || main_#t~mem86#1.offset != 0;havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem87#1.base, 12 + main_#t~mem87#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem89#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short92#1 := main_#t~mem89#1 % 4294967296 >= 10 * (1 + main_#t~mem88#1) % 4294967296;" "assume !main_#t~short92#1;" "assume !main_#t~short92#1;havoc main_#t~mem89#1;havoc main_#t~mem88#1;havoc main_#t~mem90#1.base, main_#t~mem90#1.offset;havoc main_#t~mem91#1;havoc main_#t~short92#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem157#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post158#1 := main_#t~mem157#1;call write~int#2(1 + main_#t~post158#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem157#1;havoc main_#t~post158#1;" [2025-03-09 08:07:22,696 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:22,696 INFO L85 PathProgramCache]: Analyzing trace with hash 22784, now seen corresponding path program 27 times [2025-03-09 08:07:22,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:22,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1214204973] [2025-03-09 08:07:22,696 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-09 08:07:22,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:22,701 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:07:22,702 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:22,702 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-09 08:07:22,702 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:22,703 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-09 08:07:22,704 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-09 08:07:22,704 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-09 08:07:22,704 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:22,704 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-09 08:07:22,708 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-09 08:07:22,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-09 08:07:22,708 INFO L85 PathProgramCache]: Analyzing trace with hash 1334152989, now seen corresponding path program 1 times [2025-03-09 08:07:22,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-09 08:07:22,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179065050] [2025-03-09 08:07:22,708 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-09 08:07:22,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-09 08:07:22,744 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-09 08:07:22,794 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-09 08:07:22,794 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-09 08:07:22,794 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-09 08:07:35,031 WARN L286 SmtUtils]: Spent 12.00s on a formula simplification that was a NOOP. DAG size: 32 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2025-03-09 08:07:49,565 WARN L286 SmtUtils]: Spent 12.10s on a formula simplification that was a NOOP. DAG size: 39 (called from [L 388] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2025-03-09 08:08:03,066 WARN L286 SmtUtils]: Spent 12.13s on a formula simplification that was a NOOP. DAG size: 10 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify)