./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.01.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 551b0097 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.01.cil.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe --- Real Ultimate output --- This is Ultimate 0.3.0-?-551b009-m [2025-01-10 07:53:25,635 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-01-10 07:53:25,669 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-01-10 07:53:25,672 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-01-10 07:53:25,672 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-01-10 07:53:25,685 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-01-10 07:53:25,685 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-01-10 07:53:25,685 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-01-10 07:53:25,685 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-01-10 07:53:25,686 INFO L153 SettingsManager]: * Use memory slicer=true [2025-01-10 07:53:25,686 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-01-10 07:53:25,686 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-01-10 07:53:25,686 INFO L153 SettingsManager]: * Use SBE=true [2025-01-10 07:53:25,686 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-01-10 07:53:25,686 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-01-10 07:53:25,686 INFO L153 SettingsManager]: * Use old map elimination=false [2025-01-10 07:53:25,686 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-01-10 07:53:25,686 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-01-10 07:53:25,686 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-01-10 07:53:25,687 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-01-10 07:53:25,687 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-01-10 07:53:25,687 INFO L153 SettingsManager]: * sizeof long=4 [2025-01-10 07:53:25,687 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-01-10 07:53:25,687 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-01-10 07:53:25,687 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-01-10 07:53:25,687 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-01-10 07:53:25,687 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-01-10 07:53:25,687 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-01-10 07:53:25,687 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-01-10 07:53:25,687 INFO L153 SettingsManager]: * sizeof long double=12 [2025-01-10 07:53:25,688 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-01-10 07:53:25,688 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-01-10 07:53:25,688 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-01-10 07:53:25,688 INFO L153 SettingsManager]: * Use constant arrays=true [2025-01-10 07:53:25,688 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2025-01-10 07:53:25,688 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-01-10 07:53:25,688 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-01-10 07:53:25,688 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-01-10 07:53:25,688 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-01-10 07:53:25,689 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe [2025-01-10 07:53:25,879 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-01-10 07:53:25,885 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-01-10 07:53:25,886 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-01-10 07:53:25,887 INFO L270 PluginConnector]: Initializing CDTParser... [2025-01-10 07:53:25,887 INFO L274 PluginConnector]: CDTParser initialized [2025-01-10 07:53:25,888 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.01.cil.c [2025-01-10 07:53:27,052 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/cc9c79c39/5fcc5da196354d5e98eabb95b06d97b7/FLAG5c77dc0c0 [2025-01-10 07:53:27,340 INFO L384 CDTParser]: Found 1 translation units. [2025-01-10 07:53:27,346 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.01.cil.c [2025-01-10 07:53:27,358 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/cc9c79c39/5fcc5da196354d5e98eabb95b06d97b7/FLAG5c77dc0c0 [2025-01-10 07:53:27,376 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/cc9c79c39/5fcc5da196354d5e98eabb95b06d97b7 [2025-01-10 07:53:27,391 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-01-10 07:53:27,393 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-01-10 07:53:27,396 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-01-10 07:53:27,397 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-01-10 07:53:27,401 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-01-10 07:53:27,402 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,403 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4f72e7f0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27, skipping insertion in model container [2025-01-10 07:53:27,403 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,425 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-01-10 07:53:27,612 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:53:27,632 INFO L200 MainTranslator]: Completed pre-run [2025-01-10 07:53:27,676 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:53:27,691 INFO L204 MainTranslator]: Completed translation [2025-01-10 07:53:27,692 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27 WrapperNode [2025-01-10 07:53:27,692 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-01-10 07:53:27,693 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-01-10 07:53:27,693 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-01-10 07:53:27,693 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-01-10 07:53:27,697 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,701 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,714 INFO L138 Inliner]: procedures = 30, calls = 34, calls flagged for inlining = 29, calls inlined = 35, statements flattened = 346 [2025-01-10 07:53:27,715 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-01-10 07:53:27,715 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-01-10 07:53:27,715 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-01-10 07:53:27,715 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-01-10 07:53:27,721 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,721 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,723 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,729 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-01-10 07:53:27,729 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,729 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,732 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,732 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,735 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,736 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,740 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,741 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-01-10 07:53:27,742 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2025-01-10 07:53:27,742 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2025-01-10 07:53:27,742 INFO L274 PluginConnector]: RCFGBuilder initialized [2025-01-10 07:53:27,743 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,746 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:27,756 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:27,766 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:27,770 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-01-10 07:53:27,783 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-01-10 07:53:27,783 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-01-10 07:53:27,784 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-01-10 07:53:27,784 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-01-10 07:53:27,825 INFO L234 CfgBuilder]: Building ICFG [2025-01-10 07:53:27,828 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2025-01-10 07:53:28,033 INFO L? ?]: Removed 60 outVars from TransFormulas that were not future-live. [2025-01-10 07:53:28,033 INFO L283 CfgBuilder]: Performing block encoding [2025-01-10 07:53:28,047 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-01-10 07:53:28,054 INFO L312 CfgBuilder]: Removed 5 assume(true) statements. [2025-01-10 07:53:28,054 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:53:28 BoogieIcfgContainer [2025-01-10 07:53:28,054 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2025-01-10 07:53:28,055 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-01-10 07:53:28,055 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-01-10 07:53:28,064 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-01-10 07:53:28,064 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:53:28,065 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.01 07:53:27" (1/3) ... [2025-01-10 07:53:28,066 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@716a8bd2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:53:28, skipping insertion in model container [2025-01-10 07:53:28,067 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:53:28,067 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (2/3) ... [2025-01-10 07:53:28,067 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@716a8bd2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:53:28, skipping insertion in model container [2025-01-10 07:53:28,067 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:53:28,067 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:53:28" (3/3) ... [2025-01-10 07:53:28,068 INFO L363 chiAutomizerObserver]: Analyzing ICFG transmitter.01.cil.c [2025-01-10 07:53:28,110 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-01-10 07:53:28,110 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-01-10 07:53:28,110 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-01-10 07:53:28,110 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-01-10 07:53:28,110 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-01-10 07:53:28,110 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-01-10 07:53:28,111 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-01-10 07:53:28,111 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-01-10 07:53:28,114 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 131 states, 130 states have (on average 1.4923076923076923) internal successors, (194), 130 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:28,129 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2025-01-10 07:53:28,129 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:28,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:28,134 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,134 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,134 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-01-10 07:53:28,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 131 states, 130 states have (on average 1.4923076923076923) internal successors, (194), 130 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:28,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2025-01-10 07:53:28,138 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:28,138 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:28,139 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,139 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,143 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:28,144 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:28,147 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:28,147 INFO L85 PathProgramCache]: Analyzing trace with hash 920294251, now seen corresponding path program 1 times [2025-01-10 07:53:28,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:28,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842696303] [2025-01-10 07:53:28,152 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:28,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:28,204 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:53:28,213 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:53:28,214 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:28,214 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:28,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:28,293 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:28,293 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842696303] [2025-01-10 07:53:28,293 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1842696303] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:28,293 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:28,294 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:28,295 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886717748] [2025-01-10 07:53:28,295 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:28,298 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:28,299 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:28,299 INFO L85 PathProgramCache]: Analyzing trace with hash -665983702, now seen corresponding path program 1 times [2025-01-10 07:53:28,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:28,300 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321799340] [2025-01-10 07:53:28,300 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:28,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:28,310 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-01-10 07:53:28,311 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-01-10 07:53:28,312 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:28,312 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:28,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:28,331 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:28,331 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1321799340] [2025-01-10 07:53:28,331 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1321799340] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:28,331 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:28,331 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:53:28,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1397001763] [2025-01-10 07:53:28,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:28,332 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:28,333 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:28,357 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:28,358 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:28,360 INFO L87 Difference]: Start difference. First operand has 131 states, 130 states have (on average 1.4923076923076923) internal successors, (194), 130 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:28,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:28,389 INFO L93 Difference]: Finished difference Result 129 states and 185 transitions. [2025-01-10 07:53:28,390 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 129 states and 185 transitions. [2025-01-10 07:53:28,394 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2025-01-10 07:53:28,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 129 states to 123 states and 179 transitions. [2025-01-10 07:53:28,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123 [2025-01-10 07:53:28,402 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123 [2025-01-10 07:53:28,402 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 179 transitions. [2025-01-10 07:53:28,403 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:28,403 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123 states and 179 transitions. [2025-01-10 07:53:28,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 179 transitions. [2025-01-10 07:53:28,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 123. [2025-01-10 07:53:28,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123 states, 123 states have (on average 1.4552845528455285) internal successors, (179), 122 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:28,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 179 transitions. [2025-01-10 07:53:28,433 INFO L240 hiAutomatonCegarLoop]: Abstraction has 123 states and 179 transitions. [2025-01-10 07:53:28,434 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:28,436 INFO L432 stractBuchiCegarLoop]: Abstraction has 123 states and 179 transitions. [2025-01-10 07:53:28,437 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-01-10 07:53:28,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123 states and 179 transitions. [2025-01-10 07:53:28,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2025-01-10 07:53:28,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:28,441 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:28,442 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,442 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,442 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:28,442 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:28,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:28,443 INFO L85 PathProgramCache]: Analyzing trace with hash -1569234711, now seen corresponding path program 1 times [2025-01-10 07:53:28,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:28,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1292337440] [2025-01-10 07:53:28,443 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:28,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:28,452 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:53:28,462 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:53:28,462 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:28,463 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:28,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:28,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:28,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1292337440] [2025-01-10 07:53:28,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1292337440] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:28,523 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:28,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:53:28,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1111956326] [2025-01-10 07:53:28,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:28,523 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:28,524 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:28,525 INFO L85 PathProgramCache]: Analyzing trace with hash 1027723871, now seen corresponding path program 1 times [2025-01-10 07:53:28,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:28,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391522889] [2025-01-10 07:53:28,526 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:28,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:28,537 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:53:28,548 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:53:28,550 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:28,550 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:28,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:28,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:28,627 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1391522889] [2025-01-10 07:53:28,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1391522889] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:28,627 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:28,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:53:28,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928278879] [2025-01-10 07:53:28,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:28,628 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:28,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:28,628 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:28,628 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:28,629 INFO L87 Difference]: Start difference. First operand 123 states and 179 transitions. cyclomatic complexity: 57 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:28,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:28,667 INFO L93 Difference]: Finished difference Result 212 states and 303 transitions. [2025-01-10 07:53:28,667 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 212 states and 303 transitions. [2025-01-10 07:53:28,673 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 182 [2025-01-10 07:53:28,674 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 212 states to 212 states and 303 transitions. [2025-01-10 07:53:28,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 212 [2025-01-10 07:53:28,674 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 212 [2025-01-10 07:53:28,674 INFO L73 IsDeterministic]: Start isDeterministic. Operand 212 states and 303 transitions. [2025-01-10 07:53:28,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:28,675 INFO L218 hiAutomatonCegarLoop]: Abstraction has 212 states and 303 transitions. [2025-01-10 07:53:28,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states and 303 transitions. [2025-01-10 07:53:28,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 209. [2025-01-10 07:53:28,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 209 states, 209 states have (on average 1.430622009569378) internal successors, (299), 208 states have internal predecessors, (299), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:28,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209 states to 209 states and 299 transitions. [2025-01-10 07:53:28,686 INFO L240 hiAutomatonCegarLoop]: Abstraction has 209 states and 299 transitions. [2025-01-10 07:53:28,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:28,689 INFO L432 stractBuchiCegarLoop]: Abstraction has 209 states and 299 transitions. [2025-01-10 07:53:28,689 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-01-10 07:53:28,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 209 states and 299 transitions. [2025-01-10 07:53:28,690 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 181 [2025-01-10 07:53:28,690 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:28,690 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:28,691 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,691 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,691 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:28,691 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:28,695 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:28,695 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 1 times [2025-01-10 07:53:28,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:28,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798331836] [2025-01-10 07:53:28,695 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:28,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:28,706 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:53:28,710 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:53:28,710 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:28,710 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:28,710 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:28,713 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:53:28,717 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:53:28,717 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:28,717 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:28,733 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:28,734 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:28,734 INFO L85 PathProgramCache]: Analyzing trace with hash 914337214, now seen corresponding path program 1 times [2025-01-10 07:53:28,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:28,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1871688331] [2025-01-10 07:53:28,734 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:28,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:28,740 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-01-10 07:53:28,745 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-01-10 07:53:28,746 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:28,746 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:28,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:28,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:28,811 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1871688331] [2025-01-10 07:53:28,811 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1871688331] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:28,811 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:28,811 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:53:28,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780724082] [2025-01-10 07:53:28,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:28,811 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:28,811 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:28,812 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-10 07:53:28,812 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-10 07:53:28,812 INFO L87 Difference]: Start difference. First operand 209 states and 299 transitions. cyclomatic complexity: 92 Second operand has 5 states, 5 states have (on average 8.0) internal successors, (40), 5 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:28,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:28,869 INFO L93 Difference]: Finished difference Result 223 states and 313 transitions. [2025-01-10 07:53:28,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 223 states and 313 transitions. [2025-01-10 07:53:28,871 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 195 [2025-01-10 07:53:28,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 223 states to 223 states and 313 transitions. [2025-01-10 07:53:28,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 223 [2025-01-10 07:53:28,873 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 223 [2025-01-10 07:53:28,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223 states and 313 transitions. [2025-01-10 07:53:28,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:28,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 223 states and 313 transitions. [2025-01-10 07:53:28,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states and 313 transitions. [2025-01-10 07:53:28,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 215. [2025-01-10 07:53:28,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 215 states, 215 states have (on average 1.4186046511627908) internal successors, (305), 214 states have internal predecessors, (305), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:28,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 305 transitions. [2025-01-10 07:53:28,886 INFO L240 hiAutomatonCegarLoop]: Abstraction has 215 states and 305 transitions. [2025-01-10 07:53:28,886 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:53:28,887 INFO L432 stractBuchiCegarLoop]: Abstraction has 215 states and 305 transitions. [2025-01-10 07:53:28,887 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-01-10 07:53:28,887 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 215 states and 305 transitions. [2025-01-10 07:53:28,889 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 187 [2025-01-10 07:53:28,889 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:28,889 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:28,889 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,889 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,890 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:28,890 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:28,890 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:28,890 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 2 times [2025-01-10 07:53:28,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:28,891 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409167958] [2025-01-10 07:53:28,891 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:53:28,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:28,897 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:53:28,900 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:53:28,900 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:53:28,900 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:28,900 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:28,902 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:53:28,905 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:53:28,905 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:28,905 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:28,909 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:28,909 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:28,909 INFO L85 PathProgramCache]: Analyzing trace with hash -2127275707, now seen corresponding path program 1 times [2025-01-10 07:53:28,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:28,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183314404] [2025-01-10 07:53:28,910 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:28,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:28,915 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:53:28,921 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:53:28,921 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:28,921 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:28,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:28,987 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:28,987 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1183314404] [2025-01-10 07:53:28,987 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1183314404] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:28,987 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:28,987 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:53:28,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1111779932] [2025-01-10 07:53:28,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:28,988 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:28,988 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:28,988 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-10 07:53:28,988 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-10 07:53:28,989 INFO L87 Difference]: Start difference. First operand 215 states and 305 transitions. cyclomatic complexity: 92 Second operand has 5 states, 5 states have (on average 8.2) internal successors, (41), 5 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:29,068 INFO L93 Difference]: Finished difference Result 236 states and 326 transitions. [2025-01-10 07:53:29,068 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 236 states and 326 transitions. [2025-01-10 07:53:29,070 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 205 [2025-01-10 07:53:29,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 236 states to 236 states and 326 transitions. [2025-01-10 07:53:29,075 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 236 [2025-01-10 07:53:29,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 236 [2025-01-10 07:53:29,076 INFO L73 IsDeterministic]: Start isDeterministic. Operand 236 states and 326 transitions. [2025-01-10 07:53:29,076 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:29,076 INFO L218 hiAutomatonCegarLoop]: Abstraction has 236 states and 326 transitions. [2025-01-10 07:53:29,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states and 326 transitions. [2025-01-10 07:53:29,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 236. [2025-01-10 07:53:29,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 236 states, 236 states have (on average 1.38135593220339) internal successors, (326), 235 states have internal predecessors, (326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 326 transitions. [2025-01-10 07:53:29,083 INFO L240 hiAutomatonCegarLoop]: Abstraction has 236 states and 326 transitions. [2025-01-10 07:53:29,087 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:53:29,088 INFO L432 stractBuchiCegarLoop]: Abstraction has 236 states and 326 transitions. [2025-01-10 07:53:29,088 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-01-10 07:53:29,088 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 236 states and 326 transitions. [2025-01-10 07:53:29,093 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 205 [2025-01-10 07:53:29,094 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:29,094 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:29,095 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,095 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,095 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:29,095 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:29,096 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,096 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 3 times [2025-01-10 07:53:29,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,096 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [915793772] [2025-01-10 07:53:29,096 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:53:29,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,102 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:53:29,105 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:53:29,105 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:53:29,105 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:29,106 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:29,107 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:53:29,110 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:53:29,110 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,110 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:29,113 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:29,114 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,114 INFO L85 PathProgramCache]: Analyzing trace with hash 2033678083, now seen corresponding path program 1 times [2025-01-10 07:53:29,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1628304840] [2025-01-10 07:53:29,114 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,119 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:53:29,121 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:53:29,122 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,122 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,142 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,143 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1628304840] [2025-01-10 07:53:29,143 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1628304840] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,143 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,143 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:29,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1513405739] [2025-01-10 07:53:29,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,143 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:29,143 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:29,144 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:29,144 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:29,144 INFO L87 Difference]: Start difference. First operand 236 states and 326 transitions. cyclomatic complexity: 92 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:29,177 INFO L93 Difference]: Finished difference Result 371 states and 500 transitions. [2025-01-10 07:53:29,177 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 371 states and 500 transitions. [2025-01-10 07:53:29,184 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 340 [2025-01-10 07:53:29,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 371 states to 371 states and 500 transitions. [2025-01-10 07:53:29,190 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 371 [2025-01-10 07:53:29,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 371 [2025-01-10 07:53:29,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 371 states and 500 transitions. [2025-01-10 07:53:29,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:29,191 INFO L218 hiAutomatonCegarLoop]: Abstraction has 371 states and 500 transitions. [2025-01-10 07:53:29,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 371 states and 500 transitions. [2025-01-10 07:53:29,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 371 to 352. [2025-01-10 07:53:29,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 352 states, 352 states have (on average 1.3551136363636365) internal successors, (477), 351 states have internal predecessors, (477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 352 states to 352 states and 477 transitions. [2025-01-10 07:53:29,212 INFO L240 hiAutomatonCegarLoop]: Abstraction has 352 states and 477 transitions. [2025-01-10 07:53:29,212 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:29,213 INFO L432 stractBuchiCegarLoop]: Abstraction has 352 states and 477 transitions. [2025-01-10 07:53:29,213 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-01-10 07:53:29,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 352 states and 477 transitions. [2025-01-10 07:53:29,215 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 321 [2025-01-10 07:53:29,215 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:29,215 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:29,216 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,216 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,216 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:29,217 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:29,217 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,217 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 4 times [2025-01-10 07:53:29,217 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,217 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889747231] [2025-01-10 07:53:29,218 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:53:29,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,223 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 27 statements into 2 equivalence classes. [2025-01-10 07:53:29,227 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:53:29,227 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:53:29,227 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:29,230 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:29,232 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:53:29,234 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:53:29,234 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,234 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:29,238 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:29,238 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,238 INFO L85 PathProgramCache]: Analyzing trace with hash -1818836698, now seen corresponding path program 1 times [2025-01-10 07:53:29,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,238 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [216611265] [2025-01-10 07:53:29,239 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,248 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:53:29,254 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:53:29,254 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,254 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [216611265] [2025-01-10 07:53:29,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [216611265] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,335 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,335 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:53:29,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [835284113] [2025-01-10 07:53:29,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,336 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:29,336 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:29,336 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-10 07:53:29,336 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-10 07:53:29,336 INFO L87 Difference]: Start difference. First operand 352 states and 477 transitions. cyclomatic complexity: 127 Second operand has 5 states, 5 states have (on average 8.2) internal successors, (41), 5 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:29,392 INFO L93 Difference]: Finished difference Result 367 states and 486 transitions. [2025-01-10 07:53:29,392 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 367 states and 486 transitions. [2025-01-10 07:53:29,394 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 336 [2025-01-10 07:53:29,396 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 367 states to 367 states and 486 transitions. [2025-01-10 07:53:29,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 367 [2025-01-10 07:53:29,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 367 [2025-01-10 07:53:29,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 367 states and 486 transitions. [2025-01-10 07:53:29,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:29,397 INFO L218 hiAutomatonCegarLoop]: Abstraction has 367 states and 486 transitions. [2025-01-10 07:53:29,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367 states and 486 transitions. [2025-01-10 07:53:29,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367 to 367. [2025-01-10 07:53:29,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 367 states, 367 states have (on average 1.32425068119891) internal successors, (486), 366 states have internal predecessors, (486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 367 states to 367 states and 486 transitions. [2025-01-10 07:53:29,402 INFO L240 hiAutomatonCegarLoop]: Abstraction has 367 states and 486 transitions. [2025-01-10 07:53:29,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:53:29,402 INFO L432 stractBuchiCegarLoop]: Abstraction has 367 states and 486 transitions. [2025-01-10 07:53:29,402 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-01-10 07:53:29,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 367 states and 486 transitions. [2025-01-10 07:53:29,404 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 336 [2025-01-10 07:53:29,404 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:29,404 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:29,404 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,404 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,405 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:29,405 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:29,405 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,405 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 5 times [2025-01-10 07:53:29,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774211135] [2025-01-10 07:53:29,405 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:53:29,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,408 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:53:29,410 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:53:29,410 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:53:29,410 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:29,410 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:29,411 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:53:29,412 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:53:29,412 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,412 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:29,413 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:29,414 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,414 INFO L85 PathProgramCache]: Analyzing trace with hash 481985892, now seen corresponding path program 1 times [2025-01-10 07:53:29,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,414 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [700215745] [2025-01-10 07:53:29,414 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,416 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:53:29,418 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:53:29,418 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,418 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:29,418 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:29,419 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:53:29,421 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:53:29,421 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,421 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:29,423 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:29,424 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,424 INFO L85 PathProgramCache]: Analyzing trace with hash -1769013635, now seen corresponding path program 1 times [2025-01-10 07:53:29,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,424 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [357240331] [2025-01-10 07:53:29,424 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,428 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 68 statements into 1 equivalence classes. [2025-01-10 07:53:29,429 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 68 of 68 statements. [2025-01-10 07:53:29,429 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,429 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,445 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [357240331] [2025-01-10 07:53:29,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [357240331] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:29,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083764807] [2025-01-10 07:53:29,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,785 INFO L204 LassoAnalysis]: Preferences: [2025-01-10 07:53:29,785 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-01-10 07:53:29,785 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-01-10 07:53:29,786 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-01-10 07:53:29,786 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2025-01-10 07:53:29,786 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:29,786 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-01-10 07:53:29,786 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-01-10 07:53:29,786 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.01.cil.c_Iteration7_Loop [2025-01-10 07:53:29,786 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-01-10 07:53:29,786 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-01-10 07:53:29,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,801 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,803 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,804 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,806 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,808 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,809 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,811 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,813 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,817 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,819 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,821 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,822 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,824 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,826 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,827 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,831 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,833 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,835 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,836 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,838 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,840 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,842 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,845 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,847 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,851 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,852 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,854 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,856 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:29,860 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,004 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-01-10 07:53:30,005 INFO L365 LassoAnalysis]: Checking for nontermination... [2025-01-10 07:53:30,006 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,006 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,008 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,010 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-01-10 07:53:30,011 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:30,011 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:30,026 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:30,026 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:30,034 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:30,034 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,034 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,036 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,037 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-01-10 07:53:30,039 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:30,039 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:30,050 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:30,050 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:30,056 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:30,056 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,056 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,059 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,060 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-01-10 07:53:30,062 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:30,062 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:30,074 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:30,075 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_master_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:30,080 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:30,080 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,080 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,082 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,083 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-01-10 07:53:30,085 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:30,085 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:30,096 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:30,096 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:30,103 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2025-01-10 07:53:30,104 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,104 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,105 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,107 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-01-10 07:53:30,108 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:30,108 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:30,119 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:30,120 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:30,127 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2025-01-10 07:53:30,127 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,127 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,129 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,130 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-01-10 07:53:30,131 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:30,131 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:30,143 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:30,143 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_~__retres1~2#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_~__retres1~2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:30,152 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2025-01-10 07:53:30,153 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,153 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,154 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,155 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-01-10 07:53:30,157 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:30,157 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:30,168 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:30,168 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:30,173 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:30,174 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,174 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,176 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,177 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-01-10 07:53:30,178 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:30,178 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:30,196 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:30,196 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:30,202 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:30,202 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,202 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,207 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,208 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2025-01-10 07:53:30,209 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:30,209 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:30,225 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2025-01-10 07:53:30,226 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,226 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,228 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,229 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2025-01-10 07:53:30,231 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2025-01-10 07:53:30,231 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:30,243 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2025-01-10 07:53:30,253 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:30,253 INFO L204 LassoAnalysis]: Preferences: [2025-01-10 07:53:30,253 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-01-10 07:53:30,253 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-01-10 07:53:30,253 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-01-10 07:53:30,253 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-01-10 07:53:30,253 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,253 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-01-10 07:53:30,253 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-01-10 07:53:30,253 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.01.cil.c_Iteration7_Loop [2025-01-10 07:53:30,254 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-01-10 07:53:30,254 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-01-10 07:53:30,255 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,257 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,259 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,261 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,262 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,264 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,266 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,267 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,270 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,274 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,275 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,277 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,279 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,280 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,282 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,286 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,288 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,289 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,291 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,292 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,294 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,296 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,298 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,300 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,301 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,303 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,305 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,306 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,310 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,312 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,315 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:30,426 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-01-10 07:53:30,430 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-01-10 07:53:30,431 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,431 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,433 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,435 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2025-01-10 07:53:30,437 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:30,447 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:30,448 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:30,448 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:30,448 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:30,448 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:30,451 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:30,451 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:30,453 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:30,459 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:30,459 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,459 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,461 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,462 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2025-01-10 07:53:30,464 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:30,474 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:30,474 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:30,474 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:30,474 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:30,474 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:30,475 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:30,475 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:30,476 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:30,482 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:30,482 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,482 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,484 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,485 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2025-01-10 07:53:30,486 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:30,496 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:30,497 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:30,497 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:30,497 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:30,497 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:30,498 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:30,499 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:30,500 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:30,507 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:30,507 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,507 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,509 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,509 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2025-01-10 07:53:30,511 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:30,521 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:30,521 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:30,521 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:30,521 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:30,521 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:30,522 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:30,522 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:30,523 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:30,528 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2025-01-10 07:53:30,529 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,529 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,531 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,532 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2025-01-10 07:53:30,533 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:30,543 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:30,543 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:30,543 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:30,543 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:30,543 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:30,545 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:30,545 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:30,546 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:30,552 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:30,553 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,553 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,554 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,555 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2025-01-10 07:53:30,558 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:30,568 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:30,568 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:30,568 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:30,568 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:30,568 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:30,569 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:30,569 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:30,571 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:30,580 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2025-01-10 07:53:30,581 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,581 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,583 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,584 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2025-01-10 07:53:30,589 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:30,604 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:30,604 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:30,604 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:30,605 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:30,605 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:30,605 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:30,605 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:30,607 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:30,612 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:30,612 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,613 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,615 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,616 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2025-01-10 07:53:30,617 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:30,627 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:30,627 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:30,627 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:30,627 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2025-01-10 07:53:30,627 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:30,628 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2025-01-10 07:53:30,628 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:30,633 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:30,643 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2025-01-10 07:53:30,643 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,643 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,646 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,647 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2025-01-10 07:53:30,648 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:30,660 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:30,660 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:30,661 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:30,661 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:30,661 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:30,664 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:30,664 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:30,669 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-01-10 07:53:30,672 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2025-01-10 07:53:30,676 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2025-01-10 07:53:30,677 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:30,677 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:30,683 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:30,685 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2025-01-10 07:53:30,686 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-01-10 07:53:30,686 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2025-01-10 07:53:30,686 INFO L474 LassoAnalysis]: Proved termination. [2025-01-10 07:53:30,687 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2025-01-10 07:53:30,694 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2025-01-10 07:53:30,697 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-01-10 07:53:30,734 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,752 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-01-10 07:53:30,762 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-01-10 07:53:30,762 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,762 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:30,764 INFO L256 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-01-10 07:53:30,765 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:53:30,811 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:53:30,824 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:53:30,825 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,825 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:30,826 INFO L256 TraceCheckSpWp]: Trace formula consists of 96 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-01-10 07:53:30,827 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:53:30,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:30,988 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2025-01-10 07:53:30,989 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 367 states and 486 transitions. cyclomatic complexity: 121 Second operand has 5 states, 5 states have (on average 13.6) internal successors, (68), 5 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:31,099 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 367 states and 486 transitions. cyclomatic complexity: 121. Second operand has 5 states, 5 states have (on average 13.6) internal successors, (68), 5 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 869 states and 1161 transitions. Complement of second has 5 states. [2025-01-10 07:53:31,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-01-10 07:53:31,105 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2025-01-10 07:53:31,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 13.6) internal successors, (68), 5 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:31,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 151 transitions. [2025-01-10 07:53:31,110 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 151 transitions. Stem has 27 letters. Loop has 41 letters. [2025-01-10 07:53:31,111 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-01-10 07:53:31,111 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 151 transitions. Stem has 68 letters. Loop has 41 letters. [2025-01-10 07:53:31,112 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-01-10 07:53:31,112 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 151 transitions. Stem has 27 letters. Loop has 82 letters. [2025-01-10 07:53:31,113 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-01-10 07:53:31,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 869 states and 1161 transitions. [2025-01-10 07:53:31,120 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 580 [2025-01-10 07:53:31,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 869 states to 869 states and 1161 transitions. [2025-01-10 07:53:31,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 612 [2025-01-10 07:53:31,127 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 619 [2025-01-10 07:53:31,128 INFO L73 IsDeterministic]: Start isDeterministic. Operand 869 states and 1161 transitions. [2025-01-10 07:53:31,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:53:31,128 INFO L218 hiAutomatonCegarLoop]: Abstraction has 869 states and 1161 transitions. [2025-01-10 07:53:31,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 869 states and 1161 transitions. [2025-01-10 07:53:31,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 869 to 862. [2025-01-10 07:53:31,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 862 states, 862 states have (on average 1.331786542923434) internal successors, (1148), 861 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:31,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 862 states to 862 states and 1148 transitions. [2025-01-10 07:53:31,146 INFO L240 hiAutomatonCegarLoop]: Abstraction has 862 states and 1148 transitions. [2025-01-10 07:53:31,146 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:31,147 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:31,147 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:31,147 INFO L87 Difference]: Start difference. First operand 862 states and 1148 transitions. Second operand has 3 states, 3 states have (on average 22.666666666666668) internal successors, (68), 3 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:31,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:31,178 INFO L93 Difference]: Finished difference Result 928 states and 1199 transitions. [2025-01-10 07:53:31,179 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 928 states and 1199 transitions. [2025-01-10 07:53:31,185 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 624 [2025-01-10 07:53:31,190 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 928 states to 928 states and 1199 transitions. [2025-01-10 07:53:31,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 656 [2025-01-10 07:53:31,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 656 [2025-01-10 07:53:31,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 928 states and 1199 transitions. [2025-01-10 07:53:31,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:53:31,192 INFO L218 hiAutomatonCegarLoop]: Abstraction has 928 states and 1199 transitions. [2025-01-10 07:53:31,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 928 states and 1199 transitions. [2025-01-10 07:53:31,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 928 to 862. [2025-01-10 07:53:31,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 862 states, 862 states have (on average 1.3039443155452437) internal successors, (1124), 861 states have internal predecessors, (1124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:31,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 862 states to 862 states and 1124 transitions. [2025-01-10 07:53:31,209 INFO L240 hiAutomatonCegarLoop]: Abstraction has 862 states and 1124 transitions. [2025-01-10 07:53:31,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:31,210 INFO L432 stractBuchiCegarLoop]: Abstraction has 862 states and 1124 transitions. [2025-01-10 07:53:31,210 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-01-10 07:53:31,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 862 states and 1124 transitions. [2025-01-10 07:53:31,214 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 580 [2025-01-10 07:53:31,215 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:31,215 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:31,215 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:31,215 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:31,216 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-01-10 07:53:31,216 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" [2025-01-10 07:53:31,216 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:31,216 INFO L85 PathProgramCache]: Analyzing trace with hash 2020492968, now seen corresponding path program 1 times [2025-01-10 07:53:31,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:31,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398464594] [2025-01-10 07:53:31,217 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:31,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:31,222 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-01-10 07:53:31,225 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-01-10 07:53:31,225 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,225 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,225 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:31,227 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-01-10 07:53:31,229 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-01-10 07:53:31,229 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,229 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,233 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:31,233 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:31,233 INFO L85 PathProgramCache]: Analyzing trace with hash -129024738, now seen corresponding path program 1 times [2025-01-10 07:53:31,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:31,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467080695] [2025-01-10 07:53:31,234 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:31,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:31,236 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-01-10 07:53:31,237 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-01-10 07:53:31,237 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,237 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,237 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:31,238 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-01-10 07:53:31,239 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-01-10 07:53:31,239 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,240 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,241 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:31,241 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:31,241 INFO L85 PathProgramCache]: Analyzing trace with hash -1938259369, now seen corresponding path program 1 times [2025-01-10 07:53:31,242 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:31,242 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312900970] [2025-01-10 07:53:31,242 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:31,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:31,246 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-01-10 07:53:31,248 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:53:31,248 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,249 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:31,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:31,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:31,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312900970] [2025-01-10 07:53:31,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312900970] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:31,269 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:31,269 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:53:31,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1466613275] [2025-01-10 07:53:31,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:31,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:31,301 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:31,301 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:31,301 INFO L87 Difference]: Start difference. First operand 862 states and 1124 transitions. cyclomatic complexity: 268 Second operand has 3 states, 2 states have (on average 18.5) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:31,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:31,334 INFO L93 Difference]: Finished difference Result 1374 states and 1756 transitions. [2025-01-10 07:53:31,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1374 states and 1756 transitions. [2025-01-10 07:53:31,344 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 820 [2025-01-10 07:53:31,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1374 states to 1374 states and 1756 transitions. [2025-01-10 07:53:31,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 991 [2025-01-10 07:53:31,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 991 [2025-01-10 07:53:31,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1374 states and 1756 transitions. [2025-01-10 07:53:31,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:53:31,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1374 states and 1756 transitions. [2025-01-10 07:53:31,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1374 states and 1756 transitions. [2025-01-10 07:53:31,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1374 to 1275. [2025-01-10 07:53:31,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1275 states, 1275 states have (on average 1.292549019607843) internal successors, (1648), 1274 states have internal predecessors, (1648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:31,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1275 states to 1275 states and 1648 transitions. [2025-01-10 07:53:31,377 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1275 states and 1648 transitions. [2025-01-10 07:53:31,378 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:31,379 INFO L432 stractBuchiCegarLoop]: Abstraction has 1275 states and 1648 transitions. [2025-01-10 07:53:31,379 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-01-10 07:53:31,379 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1275 states and 1648 transitions. [2025-01-10 07:53:31,385 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 800 [2025-01-10 07:53:31,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:31,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:31,386 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:31,386 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:31,387 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-01-10 07:53:31,387 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" [2025-01-10 07:53:31,387 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:31,387 INFO L85 PathProgramCache]: Analyzing trace with hash 215054634, now seen corresponding path program 1 times [2025-01-10 07:53:31,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:31,388 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370774675] [2025-01-10 07:53:31,388 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:31,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:31,392 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-01-10 07:53:31,394 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-01-10 07:53:31,394 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,394 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:31,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:31,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:31,409 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370774675] [2025-01-10 07:53:31,409 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [370774675] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:31,409 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:31,409 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:31,410 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1233334706] [2025-01-10 07:53:31,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:31,410 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:31,410 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:31,410 INFO L85 PathProgramCache]: Analyzing trace with hash -129024738, now seen corresponding path program 2 times [2025-01-10 07:53:31,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:31,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556748522] [2025-01-10 07:53:31,411 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:53:31,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:31,413 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 9 statements into 1 equivalence classes. [2025-01-10 07:53:31,417 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-01-10 07:53:31,417 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:53:31,417 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,417 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:31,418 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-01-10 07:53:31,418 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-01-10 07:53:31,418 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,418 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,419 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:31,444 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:31,444 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:31,444 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:31,444 INFO L87 Difference]: Start difference. First operand 1275 states and 1648 transitions. cyclomatic complexity: 382 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:31,451 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:31,451 INFO L93 Difference]: Finished difference Result 826 states and 1072 transitions. [2025-01-10 07:53:31,451 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 826 states and 1072 transitions. [2025-01-10 07:53:31,455 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 537 [2025-01-10 07:53:31,457 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 826 states to 826 states and 1072 transitions. [2025-01-10 07:53:31,458 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 583 [2025-01-10 07:53:31,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 583 [2025-01-10 07:53:31,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 826 states and 1072 transitions. [2025-01-10 07:53:31,458 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:53:31,458 INFO L218 hiAutomatonCegarLoop]: Abstraction has 826 states and 1072 transitions. [2025-01-10 07:53:31,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 826 states and 1072 transitions. [2025-01-10 07:53:31,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 826 to 826. [2025-01-10 07:53:31,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 826 states, 826 states have (on average 1.297820823244552) internal successors, (1072), 825 states have internal predecessors, (1072), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:31,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 826 states to 826 states and 1072 transitions. [2025-01-10 07:53:31,469 INFO L240 hiAutomatonCegarLoop]: Abstraction has 826 states and 1072 transitions. [2025-01-10 07:53:31,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:31,469 INFO L432 stractBuchiCegarLoop]: Abstraction has 826 states and 1072 transitions. [2025-01-10 07:53:31,469 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-01-10 07:53:31,469 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 826 states and 1072 transitions. [2025-01-10 07:53:31,472 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 537 [2025-01-10 07:53:31,472 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:31,472 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:31,472 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:31,472 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:31,473 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-01-10 07:53:31,473 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" [2025-01-10 07:53:31,473 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:31,473 INFO L85 PathProgramCache]: Analyzing trace with hash 2020492968, now seen corresponding path program 2 times [2025-01-10 07:53:31,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:31,473 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978031574] [2025-01-10 07:53:31,473 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:53:31,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:31,476 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 28 statements into 1 equivalence classes. [2025-01-10 07:53:31,477 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-01-10 07:53:31,477 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:53:31,478 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,478 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:31,482 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-01-10 07:53:31,483 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-01-10 07:53:31,483 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,483 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,485 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:31,485 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:31,485 INFO L85 PathProgramCache]: Analyzing trace with hash 561251259, now seen corresponding path program 1 times [2025-01-10 07:53:31,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:31,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1712612220] [2025-01-10 07:53:31,485 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:31,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:31,486 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-01-10 07:53:31,487 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-01-10 07:53:31,487 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,487 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,487 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:31,488 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-01-10 07:53:31,488 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-01-10 07:53:31,488 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,488 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,489 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:31,489 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:31,489 INFO L85 PathProgramCache]: Analyzing trace with hash 1348525748, now seen corresponding path program 1 times [2025-01-10 07:53:31,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:31,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1103286908] [2025-01-10 07:53:31,489 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:31,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:31,492 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-01-10 07:53:31,499 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-01-10 07:53:31,499 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,499 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,499 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:31,500 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-01-10 07:53:31,505 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-01-10 07:53:31,505 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,505 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,507 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:31,786 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-01-10 07:53:31,789 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-01-10 07:53:31,789 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,789 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,789 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:31,793 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-01-10 07:53:31,796 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-01-10 07:53:31,796 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,796 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,835 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 10.01 07:53:31 BoogieIcfgContainer [2025-01-10 07:53:31,835 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-01-10 07:53:31,835 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-01-10 07:53:31,835 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-01-10 07:53:31,835 INFO L274 PluginConnector]: Witness Printer initialized [2025-01-10 07:53:31,836 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:53:28" (3/4) ... [2025-01-10 07:53:31,837 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-01-10 07:53:31,876 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-01-10 07:53:31,876 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-01-10 07:53:31,876 INFO L158 Benchmark]: Toolchain (without parser) took 4483.62ms. Allocated memory was 142.6MB in the beginning and 276.8MB in the end (delta: 134.2MB). Free memory was 111.0MB in the beginning and 117.9MB in the end (delta: -6.9MB). Peak memory consumption was 125.4MB. Max. memory is 16.1GB. [2025-01-10 07:53:31,877 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 201.3MB. Free memory is still 126.8MB. There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:53:31,877 INFO L158 Benchmark]: CACSL2BoogieTranslator took 296.45ms. Allocated memory is still 142.6MB. Free memory was 111.0MB in the beginning and 98.3MB in the end (delta: 12.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-01-10 07:53:31,877 INFO L158 Benchmark]: Boogie Procedure Inliner took 21.95ms. Allocated memory is still 142.6MB. Free memory was 98.3MB in the beginning and 96.6MB in the end (delta: 1.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-01-10 07:53:31,877 INFO L158 Benchmark]: Boogie Preprocessor took 26.54ms. Allocated memory is still 142.6MB. Free memory was 96.6MB in the beginning and 94.1MB in the end (delta: 2.5MB). There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:53:31,877 INFO L158 Benchmark]: RCFGBuilder took 312.12ms. Allocated memory is still 142.6MB. Free memory was 94.1MB in the beginning and 73.0MB in the end (delta: 21.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-01-10 07:53:31,877 INFO L158 Benchmark]: BuchiAutomizer took 3779.85ms. Allocated memory was 142.6MB in the beginning and 276.8MB in the end (delta: 134.2MB). Free memory was 73.0MB in the beginning and 122.1MB in the end (delta: -49.1MB). Peak memory consumption was 91.8MB. Max. memory is 16.1GB. [2025-01-10 07:53:31,878 INFO L158 Benchmark]: Witness Printer took 40.78ms. Allocated memory is still 276.8MB. Free memory was 122.1MB in the beginning and 117.9MB in the end (delta: 4.2MB). There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:53:31,879 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 201.3MB. Free memory is still 126.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 296.45ms. Allocated memory is still 142.6MB. Free memory was 111.0MB in the beginning and 98.3MB in the end (delta: 12.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 21.95ms. Allocated memory is still 142.6MB. Free memory was 98.3MB in the beginning and 96.6MB in the end (delta: 1.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 26.54ms. Allocated memory is still 142.6MB. Free memory was 96.6MB in the beginning and 94.1MB in the end (delta: 2.5MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 312.12ms. Allocated memory is still 142.6MB. Free memory was 94.1MB in the beginning and 73.0MB in the end (delta: 21.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 3779.85ms. Allocated memory was 142.6MB in the beginning and 276.8MB in the end (delta: 134.2MB). Free memory was 73.0MB in the beginning and 122.1MB in the end (delta: -49.1MB). Peak memory consumption was 91.8MB. Max. memory is 16.1GB. * Witness Printer took 40.78ms. Allocated memory is still 276.8MB. Free memory was 122.1MB in the beginning and 117.9MB in the end (delta: 4.2MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (9 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * M_E) + 1) and consists of 3 locations. 9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 826 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.7s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 2.5s. Construction of modules took 0.2s. Büchi inclusion checks took 0.8s. Highest rank in rank-based complementation 3. Minimization of det autom 6. Minimization of nondet autom 4. Automata minimization 0.1s AutomataMinimizationTime, 10 MinimizatonAttempts, 202 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 939 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 938 mSDsluCounter, 4030 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2149 mSDsCounter, 67 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 267 IncrementalHoareTripleChecker+Invalid, 334 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 67 mSolverCounterUnsat, 1881 mSDtfsCounter, 267 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc1 concLT1 SILN1 SILU0 SILI2 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital38 mio100 ax100 hnf100 lsp23 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq188 hnf94 smp100 dnf137 smp100 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 20ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 8 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 1]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 1]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-01-10 07:53:31,891 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)