./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 551b0097 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 --- Real Ultimate output --- This is Ultimate 0.3.0-?-551b009-m [2025-01-10 07:53:25,848 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-01-10 07:53:25,906 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-01-10 07:53:25,912 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-01-10 07:53:25,912 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-01-10 07:53:25,931 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-01-10 07:53:25,932 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-01-10 07:53:25,932 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-01-10 07:53:25,932 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-01-10 07:53:25,933 INFO L153 SettingsManager]: * Use memory slicer=true [2025-01-10 07:53:25,933 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-01-10 07:53:25,933 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-01-10 07:53:25,934 INFO L153 SettingsManager]: * Use SBE=true [2025-01-10 07:53:25,934 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-01-10 07:53:25,934 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-01-10 07:53:25,934 INFO L153 SettingsManager]: * Use old map elimination=false [2025-01-10 07:53:25,934 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-01-10 07:53:25,934 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-01-10 07:53:25,934 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-01-10 07:53:25,935 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * sizeof long=4 [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * sizeof long double=12 [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-01-10 07:53:25,935 INFO L153 SettingsManager]: * Use constant arrays=true [2025-01-10 07:53:25,936 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2025-01-10 07:53:25,936 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-01-10 07:53:25,936 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-01-10 07:53:25,936 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-01-10 07:53:25,936 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-01-10 07:53:25,936 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 [2025-01-10 07:53:26,141 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-01-10 07:53:26,149 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-01-10 07:53:26,151 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-01-10 07:53:26,152 INFO L270 PluginConnector]: Initializing CDTParser... [2025-01-10 07:53:26,152 INFO L274 PluginConnector]: CDTParser initialized [2025-01-10 07:53:26,153 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.03.cil.c [2025-01-10 07:53:27,262 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/5f6164e5a/5c8e27030cf14b9ca4fb34d07236ef8c/FLAGbc9ad354d [2025-01-10 07:53:27,512 INFO L384 CDTParser]: Found 1 translation units. [2025-01-10 07:53:27,513 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.03.cil.c [2025-01-10 07:53:27,527 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/5f6164e5a/5c8e27030cf14b9ca4fb34d07236ef8c/FLAGbc9ad354d [2025-01-10 07:53:27,543 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/5f6164e5a/5c8e27030cf14b9ca4fb34d07236ef8c [2025-01-10 07:53:27,545 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-01-10 07:53:27,546 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-01-10 07:53:27,547 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-01-10 07:53:27,547 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-01-10 07:53:27,550 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-01-10 07:53:27,552 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,552 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@60592373 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27, skipping insertion in model container [2025-01-10 07:53:27,553 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,575 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-01-10 07:53:27,731 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:53:27,744 INFO L200 MainTranslator]: Completed pre-run [2025-01-10 07:53:27,786 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:53:27,805 INFO L204 MainTranslator]: Completed translation [2025-01-10 07:53:27,807 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27 WrapperNode [2025-01-10 07:53:27,807 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-01-10 07:53:27,808 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-01-10 07:53:27,809 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-01-10 07:53:27,809 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-01-10 07:53:27,813 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,818 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,853 INFO L138 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 57, statements flattened = 720 [2025-01-10 07:53:27,853 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-01-10 07:53:27,854 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-01-10 07:53:27,855 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-01-10 07:53:27,855 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-01-10 07:53:27,862 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,862 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,865 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,889 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-01-10 07:53:27,889 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,890 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,899 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,900 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,917 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,918 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,919 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,925 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-01-10 07:53:27,925 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2025-01-10 07:53:27,925 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2025-01-10 07:53:27,925 INFO L274 PluginConnector]: RCFGBuilder initialized [2025-01-10 07:53:27,930 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (1/1) ... [2025-01-10 07:53:27,936 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:27,947 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:27,967 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:27,977 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-01-10 07:53:27,991 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-01-10 07:53:27,991 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-01-10 07:53:27,991 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-01-10 07:53:27,991 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-01-10 07:53:28,047 INFO L234 CfgBuilder]: Building ICFG [2025-01-10 07:53:28,048 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2025-01-10 07:53:28,592 INFO L? ?]: Removed 128 outVars from TransFormulas that were not future-live. [2025-01-10 07:53:28,592 INFO L283 CfgBuilder]: Performing block encoding [2025-01-10 07:53:28,602 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-01-10 07:53:28,603 INFO L312 CfgBuilder]: Removed 7 assume(true) statements. [2025-01-10 07:53:28,603 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:53:28 BoogieIcfgContainer [2025-01-10 07:53:28,603 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2025-01-10 07:53:28,604 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-01-10 07:53:28,604 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-01-10 07:53:28,608 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-01-10 07:53:28,608 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:53:28,609 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.01 07:53:27" (1/3) ... [2025-01-10 07:53:28,609 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1e977947 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:53:28, skipping insertion in model container [2025-01-10 07:53:28,609 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:53:28,610 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:53:27" (2/3) ... [2025-01-10 07:53:28,610 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1e977947 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:53:28, skipping insertion in model container [2025-01-10 07:53:28,610 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:53:28,610 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:53:28" (3/3) ... [2025-01-10 07:53:28,611 INFO L363 chiAutomizerObserver]: Analyzing ICFG transmitter.03.cil.c [2025-01-10 07:53:28,653 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-01-10 07:53:28,653 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-01-10 07:53:28,653 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-01-10 07:53:28,653 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-01-10 07:53:28,653 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-01-10 07:53:28,654 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-01-10 07:53:28,654 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-01-10 07:53:28,654 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-01-10 07:53:28,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 289 states, 288 states have (on average 1.5208333333333333) internal successors, (438), 288 states have internal predecessors, (438), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:28,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 232 [2025-01-10 07:53:28,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:28,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:28,693 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,693 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,693 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-01-10 07:53:28,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 289 states, 288 states have (on average 1.5208333333333333) internal successors, (438), 288 states have internal predecessors, (438), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:28,702 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 232 [2025-01-10 07:53:28,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:28,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:28,704 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:28,709 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:28,710 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:28,713 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:28,714 INFO L85 PathProgramCache]: Analyzing trace with hash -1773697160, now seen corresponding path program 1 times [2025-01-10 07:53:28,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:28,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1980160593] [2025-01-10 07:53:28,719 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:28,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:28,772 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:28,782 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:28,782 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:28,783 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:28,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:28,874 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:28,874 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1980160593] [2025-01-10 07:53:28,875 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1980160593] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:28,875 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:28,875 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:28,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919457811] [2025-01-10 07:53:28,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:28,879 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:28,879 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:28,880 INFO L85 PathProgramCache]: Analyzing trace with hash 866609152, now seen corresponding path program 1 times [2025-01-10 07:53:28,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:28,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901715014] [2025-01-10 07:53:28,881 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:28,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:28,893 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-01-10 07:53:28,894 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-01-10 07:53:28,894 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:28,894 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:28,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:28,916 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:28,916 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1901715014] [2025-01-10 07:53:28,916 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1901715014] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:28,916 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:28,917 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:53:28,917 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [788055473] [2025-01-10 07:53:28,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:28,918 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:28,918 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:28,938 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:28,939 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:28,940 INFO L87 Difference]: Start difference. First operand has 289 states, 288 states have (on average 1.5208333333333333) internal successors, (438), 288 states have internal predecessors, (438), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:28,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:28,967 INFO L93 Difference]: Finished difference Result 287 states and 427 transitions. [2025-01-10 07:53:28,968 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 287 states and 427 transitions. [2025-01-10 07:53:28,971 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 228 [2025-01-10 07:53:28,977 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 287 states to 281 states and 421 transitions. [2025-01-10 07:53:28,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281 [2025-01-10 07:53:28,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281 [2025-01-10 07:53:28,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 281 states and 421 transitions. [2025-01-10 07:53:28,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:28,982 INFO L218 hiAutomatonCegarLoop]: Abstraction has 281 states and 421 transitions. [2025-01-10 07:53:28,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states and 421 transitions. [2025-01-10 07:53:29,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 281. [2025-01-10 07:53:29,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281 states, 281 states have (on average 1.498220640569395) internal successors, (421), 280 states have internal predecessors, (421), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281 states to 281 states and 421 transitions. [2025-01-10 07:53:29,023 INFO L240 hiAutomatonCegarLoop]: Abstraction has 281 states and 421 transitions. [2025-01-10 07:53:29,024 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:29,026 INFO L432 stractBuchiCegarLoop]: Abstraction has 281 states and 421 transitions. [2025-01-10 07:53:29,026 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-01-10 07:53:29,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 281 states and 421 transitions. [2025-01-10 07:53:29,028 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 228 [2025-01-10 07:53:29,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:29,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:29,031 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,031 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,032 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:29,032 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:29,033 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,033 INFO L85 PathProgramCache]: Analyzing trace with hash 1627783798, now seen corresponding path program 1 times [2025-01-10 07:53:29,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1660776390] [2025-01-10 07:53:29,034 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,041 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:29,052 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:29,052 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,052 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1660776390] [2025-01-10 07:53:29,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1660776390] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,101 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:29,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1862964142] [2025-01-10 07:53:29,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,101 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:29,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,102 INFO L85 PathProgramCache]: Analyzing trace with hash 2063372865, now seen corresponding path program 1 times [2025-01-10 07:53:29,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [559068497] [2025-01-10 07:53:29,102 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,110 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 60 statements into 1 equivalence classes. [2025-01-10 07:53:29,124 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 60 of 60 statements. [2025-01-10 07:53:29,124 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,124 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,177 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [559068497] [2025-01-10 07:53:29,177 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [559068497] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,177 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,178 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:29,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8826070] [2025-01-10 07:53:29,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,178 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:29,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:29,178 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:29,178 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:29,179 INFO L87 Difference]: Start difference. First operand 281 states and 421 transitions. cyclomatic complexity: 141 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:29,198 INFO L93 Difference]: Finished difference Result 281 states and 420 transitions. [2025-01-10 07:53:29,198 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 281 states and 420 transitions. [2025-01-10 07:53:29,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 228 [2025-01-10 07:53:29,201 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 281 states to 281 states and 420 transitions. [2025-01-10 07:53:29,201 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281 [2025-01-10 07:53:29,202 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281 [2025-01-10 07:53:29,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 281 states and 420 transitions. [2025-01-10 07:53:29,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:29,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 281 states and 420 transitions. [2025-01-10 07:53:29,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states and 420 transitions. [2025-01-10 07:53:29,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 281. [2025-01-10 07:53:29,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281 states, 281 states have (on average 1.4946619217081851) internal successors, (420), 280 states have internal predecessors, (420), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281 states to 281 states and 420 transitions. [2025-01-10 07:53:29,217 INFO L240 hiAutomatonCegarLoop]: Abstraction has 281 states and 420 transitions. [2025-01-10 07:53:29,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:29,219 INFO L432 stractBuchiCegarLoop]: Abstraction has 281 states and 420 transitions. [2025-01-10 07:53:29,219 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-01-10 07:53:29,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 281 states and 420 transitions. [2025-01-10 07:53:29,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 228 [2025-01-10 07:53:29,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:29,220 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:29,221 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,221 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,221 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:29,221 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:29,222 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,222 INFO L85 PathProgramCache]: Analyzing trace with hash -1769790220, now seen corresponding path program 1 times [2025-01-10 07:53:29,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,222 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1645525518] [2025-01-10 07:53:29,222 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,230 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:29,236 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:29,239 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,239 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,274 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,274 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1645525518] [2025-01-10 07:53:29,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1645525518] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,274 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,275 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:29,275 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424449470] [2025-01-10 07:53:29,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,275 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:29,275 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,275 INFO L85 PathProgramCache]: Analyzing trace with hash -1312619808, now seen corresponding path program 1 times [2025-01-10 07:53:29,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1148006725] [2025-01-10 07:53:29,276 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,281 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 60 statements into 1 equivalence classes. [2025-01-10 07:53:29,286 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 60 of 60 statements. [2025-01-10 07:53:29,286 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,286 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1148006725] [2025-01-10 07:53:29,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1148006725] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,335 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,335 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:29,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1309340183] [2025-01-10 07:53:29,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,335 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:29,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:29,336 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:29,336 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:29,336 INFO L87 Difference]: Start difference. First operand 281 states and 420 transitions. cyclomatic complexity: 140 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:29,349 INFO L93 Difference]: Finished difference Result 281 states and 419 transitions. [2025-01-10 07:53:29,349 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 281 states and 419 transitions. [2025-01-10 07:53:29,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 228 [2025-01-10 07:53:29,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 281 states to 281 states and 419 transitions. [2025-01-10 07:53:29,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281 [2025-01-10 07:53:29,357 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281 [2025-01-10 07:53:29,357 INFO L73 IsDeterministic]: Start isDeterministic. Operand 281 states and 419 transitions. [2025-01-10 07:53:29,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:29,358 INFO L218 hiAutomatonCegarLoop]: Abstraction has 281 states and 419 transitions. [2025-01-10 07:53:29,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states and 419 transitions. [2025-01-10 07:53:29,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 281. [2025-01-10 07:53:29,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281 states, 281 states have (on average 1.491103202846975) internal successors, (419), 280 states have internal predecessors, (419), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281 states to 281 states and 419 transitions. [2025-01-10 07:53:29,363 INFO L240 hiAutomatonCegarLoop]: Abstraction has 281 states and 419 transitions. [2025-01-10 07:53:29,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:29,363 INFO L432 stractBuchiCegarLoop]: Abstraction has 281 states and 419 transitions. [2025-01-10 07:53:29,363 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-01-10 07:53:29,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 281 states and 419 transitions. [2025-01-10 07:53:29,365 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 228 [2025-01-10 07:53:29,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:29,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:29,365 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,365 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,366 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:29,366 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:29,366 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,366 INFO L85 PathProgramCache]: Analyzing trace with hash -2017936714, now seen corresponding path program 1 times [2025-01-10 07:53:29,366 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,367 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1878010309] [2025-01-10 07:53:29,367 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,373 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:29,378 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:29,379 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,379 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1878010309] [2025-01-10 07:53:29,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1878010309] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:53:29,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [15139490] [2025-01-10 07:53:29,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,424 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:29,425 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,425 INFO L85 PathProgramCache]: Analyzing trace with hash 2063372865, now seen corresponding path program 2 times [2025-01-10 07:53:29,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265025602] [2025-01-10 07:53:29,425 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:53:29,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,432 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 60 statements into 1 equivalence classes. [2025-01-10 07:53:29,440 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 60 of 60 statements. [2025-01-10 07:53:29,440 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:53:29,440 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,463 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265025602] [2025-01-10 07:53:29,463 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1265025602] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,464 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,464 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:29,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1100842365] [2025-01-10 07:53:29,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,464 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:29,464 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:29,464 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:29,464 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:29,465 INFO L87 Difference]: Start difference. First operand 281 states and 419 transitions. cyclomatic complexity: 139 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:29,495 INFO L93 Difference]: Finished difference Result 281 states and 414 transitions. [2025-01-10 07:53:29,495 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 281 states and 414 transitions. [2025-01-10 07:53:29,497 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 228 [2025-01-10 07:53:29,498 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 281 states to 281 states and 414 transitions. [2025-01-10 07:53:29,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281 [2025-01-10 07:53:29,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281 [2025-01-10 07:53:29,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 281 states and 414 transitions. [2025-01-10 07:53:29,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:29,500 INFO L218 hiAutomatonCegarLoop]: Abstraction has 281 states and 414 transitions. [2025-01-10 07:53:29,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states and 414 transitions. [2025-01-10 07:53:29,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 281. [2025-01-10 07:53:29,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281 states, 281 states have (on average 1.4733096085409252) internal successors, (414), 280 states have internal predecessors, (414), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281 states to 281 states and 414 transitions. [2025-01-10 07:53:29,507 INFO L240 hiAutomatonCegarLoop]: Abstraction has 281 states and 414 transitions. [2025-01-10 07:53:29,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:29,509 INFO L432 stractBuchiCegarLoop]: Abstraction has 281 states and 414 transitions. [2025-01-10 07:53:29,509 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-01-10 07:53:29,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 281 states and 414 transitions. [2025-01-10 07:53:29,510 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 228 [2025-01-10 07:53:29,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:29,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:29,514 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,516 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,516 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:29,516 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:29,517 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,517 INFO L85 PathProgramCache]: Analyzing trace with hash 1247671284, now seen corresponding path program 1 times [2025-01-10 07:53:29,517 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,517 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467633477] [2025-01-10 07:53:29,517 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,523 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:29,527 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:29,529 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,529 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,566 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1467633477] [2025-01-10 07:53:29,566 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1467633477] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,566 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,566 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:53:29,566 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [526469120] [2025-01-10 07:53:29,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,566 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:29,566 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,567 INFO L85 PathProgramCache]: Analyzing trace with hash 507122524, now seen corresponding path program 1 times [2025-01-10 07:53:29,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,567 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562401806] [2025-01-10 07:53:29,567 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,572 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 60 statements into 1 equivalence classes. [2025-01-10 07:53:29,601 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 60 of 60 statements. [2025-01-10 07:53:29,601 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,601 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,633 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1562401806] [2025-01-10 07:53:29,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1562401806] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:29,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111113882] [2025-01-10 07:53:29,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,633 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:29,633 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:29,634 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-10 07:53:29,634 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-10 07:53:29,634 INFO L87 Difference]: Start difference. First operand 281 states and 414 transitions. cyclomatic complexity: 134 Second operand has 5 states, 5 states have (on average 9.8) internal successors, (49), 5 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:29,738 INFO L93 Difference]: Finished difference Result 299 states and 432 transitions. [2025-01-10 07:53:29,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 299 states and 432 transitions. [2025-01-10 07:53:29,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 243 [2025-01-10 07:53:29,742 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 299 states to 299 states and 432 transitions. [2025-01-10 07:53:29,742 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 299 [2025-01-10 07:53:29,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 299 [2025-01-10 07:53:29,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 299 states and 432 transitions. [2025-01-10 07:53:29,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:29,742 INFO L218 hiAutomatonCegarLoop]: Abstraction has 299 states and 432 transitions. [2025-01-10 07:53:29,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 299 states and 432 transitions. [2025-01-10 07:53:29,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 299 to 299. [2025-01-10 07:53:29,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 299 states, 299 states have (on average 1.4448160535117056) internal successors, (432), 298 states have internal predecessors, (432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 299 states to 299 states and 432 transitions. [2025-01-10 07:53:29,748 INFO L240 hiAutomatonCegarLoop]: Abstraction has 299 states and 432 transitions. [2025-01-10 07:53:29,748 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:53:29,750 INFO L432 stractBuchiCegarLoop]: Abstraction has 299 states and 432 transitions. [2025-01-10 07:53:29,750 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-01-10 07:53:29,750 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 299 states and 432 transitions. [2025-01-10 07:53:29,751 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 243 [2025-01-10 07:53:29,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:29,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:29,754 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,754 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,754 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:29,754 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:29,755 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,755 INFO L85 PathProgramCache]: Analyzing trace with hash 738198194, now seen corresponding path program 1 times [2025-01-10 07:53:29,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1792760267] [2025-01-10 07:53:29,755 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,760 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:29,764 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:29,765 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,765 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,791 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1792760267] [2025-01-10 07:53:29,792 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1792760267] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,792 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,792 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:53:29,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [197662874] [2025-01-10 07:53:29,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,792 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:29,792 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,792 INFO L85 PathProgramCache]: Analyzing trace with hash 297420376, now seen corresponding path program 1 times [2025-01-10 07:53:29,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,794 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [541414792] [2025-01-10 07:53:29,794 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,798 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 60 statements into 1 equivalence classes. [2025-01-10 07:53:29,800 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 60 of 60 statements. [2025-01-10 07:53:29,800 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,800 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,814 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [541414792] [2025-01-10 07:53:29,814 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [541414792] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,814 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,814 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:29,814 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125220015] [2025-01-10 07:53:29,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,815 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:29,815 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:29,815 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:29,815 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:29,815 INFO L87 Difference]: Start difference. First operand 299 states and 432 transitions. cyclomatic complexity: 134 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:29,845 INFO L93 Difference]: Finished difference Result 503 states and 721 transitions. [2025-01-10 07:53:29,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 503 states and 721 transitions. [2025-01-10 07:53:29,848 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 446 [2025-01-10 07:53:29,850 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 503 states to 503 states and 721 transitions. [2025-01-10 07:53:29,850 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 503 [2025-01-10 07:53:29,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 503 [2025-01-10 07:53:29,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 503 states and 721 transitions. [2025-01-10 07:53:29,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:29,851 INFO L218 hiAutomatonCegarLoop]: Abstraction has 503 states and 721 transitions. [2025-01-10 07:53:29,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 503 states and 721 transitions. [2025-01-10 07:53:29,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 503 to 502. [2025-01-10 07:53:29,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 502 states, 502 states have (on average 1.4342629482071714) internal successors, (720), 501 states have internal predecessors, (720), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 502 states to 502 states and 720 transitions. [2025-01-10 07:53:29,858 INFO L240 hiAutomatonCegarLoop]: Abstraction has 502 states and 720 transitions. [2025-01-10 07:53:29,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:29,859 INFO L432 stractBuchiCegarLoop]: Abstraction has 502 states and 720 transitions. [2025-01-10 07:53:29,859 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-01-10 07:53:29,859 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 502 states and 720 transitions. [2025-01-10 07:53:29,861 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 445 [2025-01-10 07:53:29,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:29,861 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:29,862 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,862 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,862 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:29,862 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:29,862 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,862 INFO L85 PathProgramCache]: Analyzing trace with hash 1376982673, now seen corresponding path program 1 times [2025-01-10 07:53:29,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,863 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091259048] [2025-01-10 07:53:29,863 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,867 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:29,869 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:29,869 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,869 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,889 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1091259048] [2025-01-10 07:53:29,889 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1091259048] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,889 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,889 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:53:29,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2041694815] [2025-01-10 07:53:29,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,890 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:29,890 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,890 INFO L85 PathProgramCache]: Analyzing trace with hash -1260338726, now seen corresponding path program 1 times [2025-01-10 07:53:29,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672091734] [2025-01-10 07:53:29,890 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,894 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 60 statements into 1 equivalence classes. [2025-01-10 07:53:29,896 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 60 of 60 statements. [2025-01-10 07:53:29,896 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,896 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:29,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:29,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:29,910 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [672091734] [2025-01-10 07:53:29,910 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [672091734] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:29,911 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:29,911 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:29,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [751706403] [2025-01-10 07:53:29,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:29,911 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:29,911 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:29,911 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:29,911 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:29,912 INFO L87 Difference]: Start difference. First operand 502 states and 720 transitions. cyclomatic complexity: 220 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:29,943 INFO L93 Difference]: Finished difference Result 935 states and 1326 transitions. [2025-01-10 07:53:29,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 935 states and 1326 transitions. [2025-01-10 07:53:29,947 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 875 [2025-01-10 07:53:29,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 935 states to 935 states and 1326 transitions. [2025-01-10 07:53:29,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 935 [2025-01-10 07:53:29,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 935 [2025-01-10 07:53:29,953 INFO L73 IsDeterministic]: Start isDeterministic. Operand 935 states and 1326 transitions. [2025-01-10 07:53:29,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:29,956 INFO L218 hiAutomatonCegarLoop]: Abstraction has 935 states and 1326 transitions. [2025-01-10 07:53:29,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 935 states and 1326 transitions. [2025-01-10 07:53:29,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 935 to 933. [2025-01-10 07:53:29,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4190782422293677) internal successors, (1324), 932 states have internal predecessors, (1324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:29,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1324 transitions. [2025-01-10 07:53:29,974 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1324 transitions. [2025-01-10 07:53:29,974 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:29,975 INFO L432 stractBuchiCegarLoop]: Abstraction has 933 states and 1324 transitions. [2025-01-10 07:53:29,976 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-01-10 07:53:29,976 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1324 transitions. [2025-01-10 07:53:29,979 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 873 [2025-01-10 07:53:29,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:29,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:29,980 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,980 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:29,980 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:29,983 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:29,983 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:29,984 INFO L85 PathProgramCache]: Analyzing trace with hash 372621552, now seen corresponding path program 1 times [2025-01-10 07:53:29,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:29,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490095563] [2025-01-10 07:53:29,984 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:29,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:29,988 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:29,990 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:29,990 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:29,990 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:30,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:30,041 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:30,041 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1490095563] [2025-01-10 07:53:30,041 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1490095563] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:30,041 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:30,041 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:30,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255792636] [2025-01-10 07:53:30,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:30,042 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:30,042 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,042 INFO L85 PathProgramCache]: Analyzing trace with hash 297420376, now seen corresponding path program 2 times [2025-01-10 07:53:30,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:30,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672025782] [2025-01-10 07:53:30,042 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:53:30,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:30,046 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 60 statements into 1 equivalence classes. [2025-01-10 07:53:30,048 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 60 of 60 statements. [2025-01-10 07:53:30,048 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:53:30,048 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:30,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:30,071 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:30,071 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [672025782] [2025-01-10 07:53:30,071 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [672025782] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:30,071 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:30,071 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:30,071 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246532333] [2025-01-10 07:53:30,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:30,072 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:30,072 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:30,072 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:53:30,072 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:53:30,072 INFO L87 Difference]: Start difference. First operand 933 states and 1324 transitions. cyclomatic complexity: 395 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:30,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:30,137 INFO L93 Difference]: Finished difference Result 2005 states and 2830 transitions. [2025-01-10 07:53:30,137 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2005 states and 2830 transitions. [2025-01-10 07:53:30,147 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1898 [2025-01-10 07:53:30,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2005 states to 2005 states and 2830 transitions. [2025-01-10 07:53:30,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2005 [2025-01-10 07:53:30,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2005 [2025-01-10 07:53:30,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2005 states and 2830 transitions. [2025-01-10 07:53:30,159 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:30,160 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2005 states and 2830 transitions. [2025-01-10 07:53:30,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2005 states and 2830 transitions. [2025-01-10 07:53:30,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2005 to 1122. [2025-01-10 07:53:30,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1122 states, 1122 states have (on average 1.409982174688057) internal successors, (1582), 1121 states have internal predecessors, (1582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:30,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1122 states to 1122 states and 1582 transitions. [2025-01-10 07:53:30,181 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1122 states and 1582 transitions. [2025-01-10 07:53:30,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:53:30,182 INFO L432 stractBuchiCegarLoop]: Abstraction has 1122 states and 1582 transitions. [2025-01-10 07:53:30,183 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-01-10 07:53:30,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1122 states and 1582 transitions. [2025-01-10 07:53:30,187 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1025 [2025-01-10 07:53:30,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:30,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:30,188 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:30,188 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:30,188 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:30,189 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:30,190 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,190 INFO L85 PathProgramCache]: Analyzing trace with hash -286909970, now seen corresponding path program 1 times [2025-01-10 07:53:30,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:30,190 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815084253] [2025-01-10 07:53:30,190 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:30,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:30,194 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:30,197 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:30,197 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,197 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:30,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:30,222 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:30,223 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815084253] [2025-01-10 07:53:30,223 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815084253] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:30,223 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:30,223 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:30,223 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [37139900] [2025-01-10 07:53:30,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:30,223 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:30,223 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,224 INFO L85 PathProgramCache]: Analyzing trace with hash -1335118215, now seen corresponding path program 1 times [2025-01-10 07:53:30,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:30,224 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394223177] [2025-01-10 07:53:30,224 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:30,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:30,229 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 60 statements into 1 equivalence classes. [2025-01-10 07:53:30,233 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 60 of 60 statements. [2025-01-10 07:53:30,234 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,234 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:30,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:30,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:30,249 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [394223177] [2025-01-10 07:53:30,249 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [394223177] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:30,249 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:30,249 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:30,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2033885436] [2025-01-10 07:53:30,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:30,250 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:30,250 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:30,250 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:53:30,250 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:53:30,250 INFO L87 Difference]: Start difference. First operand 1122 states and 1582 transitions. cyclomatic complexity: 464 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:30,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:30,277 INFO L93 Difference]: Finished difference Result 933 states and 1310 transitions. [2025-01-10 07:53:30,277 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1310 transitions. [2025-01-10 07:53:30,282 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 873 [2025-01-10 07:53:30,286 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1310 transitions. [2025-01-10 07:53:30,286 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2025-01-10 07:53:30,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2025-01-10 07:53:30,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1310 transitions. [2025-01-10 07:53:30,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:30,288 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1310 transitions. [2025-01-10 07:53:30,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1310 transitions. [2025-01-10 07:53:30,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2025-01-10 07:53:30,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4040728831725617) internal successors, (1310), 932 states have internal predecessors, (1310), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:30,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1310 transitions. [2025-01-10 07:53:30,301 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1310 transitions. [2025-01-10 07:53:30,301 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:30,303 INFO L432 stractBuchiCegarLoop]: Abstraction has 933 states and 1310 transitions. [2025-01-10 07:53:30,303 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-01-10 07:53:30,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1310 transitions. [2025-01-10 07:53:30,306 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 873 [2025-01-10 07:53:30,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:30,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:30,307 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:30,307 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:30,307 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:30,307 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:30,308 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,308 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 1 times [2025-01-10 07:53:30,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:30,308 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1164491024] [2025-01-10 07:53:30,308 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:30,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:30,313 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:30,316 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:30,316 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,316 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:30,316 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:30,318 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:30,320 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:30,321 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,321 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:30,336 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:30,338 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,338 INFO L85 PathProgramCache]: Analyzing trace with hash -1290927526, now seen corresponding path program 1 times [2025-01-10 07:53:30,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:30,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763566007] [2025-01-10 07:53:30,338 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:30,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:30,342 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 60 statements into 1 equivalence classes. [2025-01-10 07:53:30,345 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 60 of 60 statements. [2025-01-10 07:53:30,345 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,345 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:30,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:30,359 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:30,359 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763566007] [2025-01-10 07:53:30,359 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763566007] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:30,359 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:30,359 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:30,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [967945951] [2025-01-10 07:53:30,359 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:30,359 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:30,359 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:30,360 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:30,360 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:30,360 INFO L87 Difference]: Start difference. First operand 933 states and 1310 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:30,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:30,398 INFO L93 Difference]: Finished difference Result 1382 states and 1922 transitions. [2025-01-10 07:53:30,398 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1382 states and 1922 transitions. [2025-01-10 07:53:30,405 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1284 [2025-01-10 07:53:30,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1382 states to 1382 states and 1922 transitions. [2025-01-10 07:53:30,425 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1382 [2025-01-10 07:53:30,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1382 [2025-01-10 07:53:30,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1382 states and 1922 transitions. [2025-01-10 07:53:30,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:30,428 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1382 states and 1922 transitions. [2025-01-10 07:53:30,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1382 states and 1922 transitions. [2025-01-10 07:53:30,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1382 to 1380. [2025-01-10 07:53:30,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1380 states, 1380 states have (on average 1.391304347826087) internal successors, (1920), 1379 states have internal predecessors, (1920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:30,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1380 states to 1380 states and 1920 transitions. [2025-01-10 07:53:30,448 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1380 states and 1920 transitions. [2025-01-10 07:53:30,449 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:30,450 INFO L432 stractBuchiCegarLoop]: Abstraction has 1380 states and 1920 transitions. [2025-01-10 07:53:30,450 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-01-10 07:53:30,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1380 states and 1920 transitions. [2025-01-10 07:53:30,455 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1282 [2025-01-10 07:53:30,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:30,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:30,455 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:30,456 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:30,456 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:30,456 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:30,456 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,456 INFO L85 PathProgramCache]: Analyzing trace with hash 768775798, now seen corresponding path program 1 times [2025-01-10 07:53:30,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:30,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917476783] [2025-01-10 07:53:30,457 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:30,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:30,461 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:30,462 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:30,462 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,462 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:30,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:30,486 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:30,486 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917476783] [2025-01-10 07:53:30,487 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917476783] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:30,487 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:30,487 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:30,487 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1122790998] [2025-01-10 07:53:30,487 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:30,487 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:30,487 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,487 INFO L85 PathProgramCache]: Analyzing trace with hash -999822789, now seen corresponding path program 1 times [2025-01-10 07:53:30,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:30,487 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950743274] [2025-01-10 07:53:30,487 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:30,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:30,493 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 60 statements into 1 equivalence classes. [2025-01-10 07:53:30,496 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 60 of 60 statements. [2025-01-10 07:53:30,496 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,496 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:30,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:30,534 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:30,534 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950743274] [2025-01-10 07:53:30,534 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950743274] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:30,534 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:30,534 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:53:30,534 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2144252823] [2025-01-10 07:53:30,534 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:30,535 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:30,535 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:30,535 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:53:30,535 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:53:30,535 INFO L87 Difference]: Start difference. First operand 1380 states and 1920 transitions. cyclomatic complexity: 544 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:30,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:30,592 INFO L93 Difference]: Finished difference Result 2361 states and 3301 transitions. [2025-01-10 07:53:30,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2361 states and 3301 transitions. [2025-01-10 07:53:30,602 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 2150 [2025-01-10 07:53:30,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2361 states to 2361 states and 3301 transitions. [2025-01-10 07:53:30,611 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2361 [2025-01-10 07:53:30,612 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2361 [2025-01-10 07:53:30,612 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2361 states and 3301 transitions. [2025-01-10 07:53:30,614 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:30,614 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2361 states and 3301 transitions. [2025-01-10 07:53:30,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2361 states and 3301 transitions. [2025-01-10 07:53:30,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2361 to 1268. [2025-01-10 07:53:30,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1268 states, 1268 states have (on average 1.3919558359621451) internal successors, (1765), 1267 states have internal predecessors, (1765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:30,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1268 states to 1268 states and 1765 transitions. [2025-01-10 07:53:30,632 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1268 states and 1765 transitions. [2025-01-10 07:53:30,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:53:30,632 INFO L432 stractBuchiCegarLoop]: Abstraction has 1268 states and 1765 transitions. [2025-01-10 07:53:30,633 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-01-10 07:53:30,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1268 states and 1765 transitions. [2025-01-10 07:53:30,636 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1207 [2025-01-10 07:53:30,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:30,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:30,637 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:30,637 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:30,637 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:30,637 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:30,637 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,638 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 2 times [2025-01-10 07:53:30,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:30,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960364951] [2025-01-10 07:53:30,638 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:53:30,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:30,641 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:30,643 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:30,643 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:53:30,643 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:30,644 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:30,645 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:30,646 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:30,646 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,646 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:30,650 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:30,650 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,651 INFO L85 PathProgramCache]: Analyzing trace with hash -999822789, now seen corresponding path program 2 times [2025-01-10 07:53:30,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:30,651 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092143610] [2025-01-10 07:53:30,651 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:53:30,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:30,656 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 60 statements into 1 equivalence classes. [2025-01-10 07:53:30,658 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 60 of 60 statements. [2025-01-10 07:53:30,658 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:53:30,658 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:30,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:30,692 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:30,692 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092143610] [2025-01-10 07:53:30,692 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2092143610] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:30,692 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:30,692 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:53:30,693 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456724902] [2025-01-10 07:53:30,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:30,693 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:30,693 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:30,694 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-10 07:53:30,694 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-10 07:53:30,694 INFO L87 Difference]: Start difference. First operand 1268 states and 1765 transitions. cyclomatic complexity: 501 Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:30,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:30,742 INFO L93 Difference]: Finished difference Result 1302 states and 1799 transitions. [2025-01-10 07:53:30,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1302 states and 1799 transitions. [2025-01-10 07:53:30,747 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1241 [2025-01-10 07:53:30,751 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1302 states to 1302 states and 1799 transitions. [2025-01-10 07:53:30,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1302 [2025-01-10 07:53:30,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1302 [2025-01-10 07:53:30,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1302 states and 1799 transitions. [2025-01-10 07:53:30,754 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:30,754 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1302 states and 1799 transitions. [2025-01-10 07:53:30,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1302 states and 1799 transitions. [2025-01-10 07:53:30,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1302 to 1286. [2025-01-10 07:53:30,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1286 states, 1286 states have (on average 1.3864696734059099) internal successors, (1783), 1285 states have internal predecessors, (1783), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:30,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1286 states to 1286 states and 1783 transitions. [2025-01-10 07:53:30,768 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1286 states and 1783 transitions. [2025-01-10 07:53:30,768 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:53:30,768 INFO L432 stractBuchiCegarLoop]: Abstraction has 1286 states and 1783 transitions. [2025-01-10 07:53:30,768 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-01-10 07:53:30,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1286 states and 1783 transitions. [2025-01-10 07:53:30,771 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1225 [2025-01-10 07:53:30,772 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:30,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:30,772 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:30,772 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:30,772 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:30,772 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:30,773 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,773 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 3 times [2025-01-10 07:53:30,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:30,773 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703617546] [2025-01-10 07:53:30,773 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:53:30,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:30,777 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:30,789 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:30,789 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:53:30,790 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:30,790 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:30,791 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:30,793 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:30,793 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,793 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:30,796 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:30,797 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,797 INFO L85 PathProgramCache]: Analyzing trace with hash -1652023896, now seen corresponding path program 1 times [2025-01-10 07:53:30,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:30,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149345467] [2025-01-10 07:53:30,797 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:30,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:30,801 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 63 statements into 1 equivalence classes. [2025-01-10 07:53:30,804 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 63 of 63 statements. [2025-01-10 07:53:30,804 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,804 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:30,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:30,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:30,835 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [149345467] [2025-01-10 07:53:30,835 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [149345467] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:30,836 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:30,836 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:53:30,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2007021220] [2025-01-10 07:53:30,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:30,836 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:30,836 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:30,836 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-10 07:53:30,836 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-10 07:53:30,837 INFO L87 Difference]: Start difference. First operand 1286 states and 1783 transitions. cyclomatic complexity: 501 Second operand has 5 states, 5 states have (on average 12.6) internal successors, (63), 5 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:30,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:30,918 INFO L93 Difference]: Finished difference Result 1310 states and 1790 transitions. [2025-01-10 07:53:30,918 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1310 states and 1790 transitions. [2025-01-10 07:53:30,922 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1249 [2025-01-10 07:53:30,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1310 states to 1310 states and 1790 transitions. [2025-01-10 07:53:30,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1310 [2025-01-10 07:53:30,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1310 [2025-01-10 07:53:30,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1310 states and 1790 transitions. [2025-01-10 07:53:30,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:30,930 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1310 states and 1790 transitions. [2025-01-10 07:53:30,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1310 states and 1790 transitions. [2025-01-10 07:53:30,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1310 to 1310. [2025-01-10 07:53:30,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1310 states, 1310 states have (on average 1.366412213740458) internal successors, (1790), 1309 states have internal predecessors, (1790), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:30,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1310 states to 1310 states and 1790 transitions. [2025-01-10 07:53:30,944 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1310 states and 1790 transitions. [2025-01-10 07:53:30,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:53:30,945 INFO L432 stractBuchiCegarLoop]: Abstraction has 1310 states and 1790 transitions. [2025-01-10 07:53:30,946 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-01-10 07:53:30,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1310 states and 1790 transitions. [2025-01-10 07:53:30,948 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1249 [2025-01-10 07:53:30,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:30,949 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:30,949 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:30,949 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:30,949 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:30,949 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:30,950 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,950 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 4 times [2025-01-10 07:53:30,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:30,950 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280206811] [2025-01-10 07:53:30,950 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:53:30,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:30,955 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 49 statements into 2 equivalence classes. [2025-01-10 07:53:30,957 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:30,958 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:53:30,958 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:30,958 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:30,959 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:30,961 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:30,961 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,961 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:30,966 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:30,966 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:30,966 INFO L85 PathProgramCache]: Analyzing trace with hash -1328975262, now seen corresponding path program 1 times [2025-01-10 07:53:30,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:30,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683274483] [2025-01-10 07:53:30,966 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:30,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:30,972 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 63 statements into 1 equivalence classes. [2025-01-10 07:53:30,974 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 63 of 63 statements. [2025-01-10 07:53:30,974 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:30,974 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:30,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:30,993 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:30,993 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683274483] [2025-01-10 07:53:30,993 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1683274483] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:30,993 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:30,993 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:30,993 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1262113840] [2025-01-10 07:53:30,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:30,993 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:30,993 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:30,994 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:30,994 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:30,994 INFO L87 Difference]: Start difference. First operand 1310 states and 1790 transitions. cyclomatic complexity: 484 Second operand has 3 states, 3 states have (on average 21.0) internal successors, (63), 3 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:31,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:31,027 INFO L93 Difference]: Finished difference Result 2326 states and 3129 transitions. [2025-01-10 07:53:31,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2326 states and 3129 transitions. [2025-01-10 07:53:31,033 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2258 [2025-01-10 07:53:31,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2326 states to 2326 states and 3129 transitions. [2025-01-10 07:53:31,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2326 [2025-01-10 07:53:31,042 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2326 [2025-01-10 07:53:31,042 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2326 states and 3129 transitions. [2025-01-10 07:53:31,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:31,045 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2326 states and 3129 transitions. [2025-01-10 07:53:31,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2326 states and 3129 transitions. [2025-01-10 07:53:31,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2326 to 2228. [2025-01-10 07:53:31,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2228 states, 2228 states have (on average 1.3496409335727109) internal successors, (3007), 2227 states have internal predecessors, (3007), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:31,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2228 states to 2228 states and 3007 transitions. [2025-01-10 07:53:31,067 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2228 states and 3007 transitions. [2025-01-10 07:53:31,068 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:31,069 INFO L432 stractBuchiCegarLoop]: Abstraction has 2228 states and 3007 transitions. [2025-01-10 07:53:31,069 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-01-10 07:53:31,069 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2228 states and 3007 transitions. [2025-01-10 07:53:31,073 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2160 [2025-01-10 07:53:31,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:31,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:31,073 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:31,074 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:31,074 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:31,074 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:31,074 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:31,074 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 5 times [2025-01-10 07:53:31,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:31,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322980035] [2025-01-10 07:53:31,074 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:53:31,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:31,079 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:31,081 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:31,081 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:53:31,081 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,082 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:31,083 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:31,085 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:31,086 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,086 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,089 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:31,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:31,094 INFO L85 PathProgramCache]: Analyzing trace with hash 1317934725, now seen corresponding path program 1 times [2025-01-10 07:53:31,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:31,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051039692] [2025-01-10 07:53:31,094 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:31,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:31,098 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 63 statements into 1 equivalence classes. [2025-01-10 07:53:31,101 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 63 of 63 statements. [2025-01-10 07:53:31,101 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,101 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:31,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:31,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:31,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051039692] [2025-01-10 07:53:31,155 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051039692] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:31,155 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:31,155 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:53:31,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1620174759] [2025-01-10 07:53:31,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:31,156 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:53:31,156 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:31,156 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-10 07:53:31,156 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-10 07:53:31,156 INFO L87 Difference]: Start difference. First operand 2228 states and 3007 transitions. cyclomatic complexity: 783 Second operand has 5 states, 5 states have (on average 12.6) internal successors, (63), 5 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:31,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:31,242 INFO L93 Difference]: Finished difference Result 2375 states and 3154 transitions. [2025-01-10 07:53:31,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2375 states and 3154 transitions. [2025-01-10 07:53:31,250 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2304 [2025-01-10 07:53:31,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2375 states to 2375 states and 3154 transitions. [2025-01-10 07:53:31,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2375 [2025-01-10 07:53:31,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2375 [2025-01-10 07:53:31,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2375 states and 3154 transitions. [2025-01-10 07:53:31,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:53:31,260 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2375 states and 3154 transitions. [2025-01-10 07:53:31,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2375 states and 3154 transitions. [2025-01-10 07:53:31,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2375 to 2375. [2025-01-10 07:53:31,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2375 states, 2375 states have (on average 1.328) internal successors, (3154), 2374 states have internal predecessors, (3154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:31,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2375 states to 2375 states and 3154 transitions. [2025-01-10 07:53:31,285 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2375 states and 3154 transitions. [2025-01-10 07:53:31,285 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:53:31,286 INFO L432 stractBuchiCegarLoop]: Abstraction has 2375 states and 3154 transitions. [2025-01-10 07:53:31,286 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-01-10 07:53:31,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2375 states and 3154 transitions. [2025-01-10 07:53:31,291 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2304 [2025-01-10 07:53:31,291 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:31,291 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:31,292 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:31,292 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:31,292 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:53:31,292 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret15#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-01-10 07:53:31,293 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:31,293 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 6 times [2025-01-10 07:53:31,293 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:31,293 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [810179112] [2025-01-10 07:53:31,293 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:53:31,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:31,298 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:31,300 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:31,300 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-01-10 07:53:31,300 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,300 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:31,302 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:31,304 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:31,304 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,304 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,307 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:31,308 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:31,308 INFO L85 PathProgramCache]: Analyzing trace with hash 398960102, now seen corresponding path program 1 times [2025-01-10 07:53:31,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:31,308 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531162461] [2025-01-10 07:53:31,308 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:31,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:31,313 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 63 statements into 1 equivalence classes. [2025-01-10 07:53:31,316 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 63 of 63 statements. [2025-01-10 07:53:31,316 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,316 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,316 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:31,317 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 63 statements into 1 equivalence classes. [2025-01-10 07:53:31,320 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 63 of 63 statements. [2025-01-10 07:53:31,320 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,320 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:31,325 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:31,325 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:31,325 INFO L85 PathProgramCache]: Analyzing trace with hash 122190805, now seen corresponding path program 1 times [2025-01-10 07:53:31,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:31,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [826684702] [2025-01-10 07:53:31,325 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:31,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:31,336 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 112 statements into 1 equivalence classes. [2025-01-10 07:53:31,339 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 112 of 112 statements. [2025-01-10 07:53:31,340 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:31,340 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:31,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:31,366 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:31,366 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [826684702] [2025-01-10 07:53:31,366 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [826684702] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:31,366 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:31,366 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:31,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410048836] [2025-01-10 07:53:31,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:31,844 INFO L204 LassoAnalysis]: Preferences: [2025-01-10 07:53:31,844 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-01-10 07:53:31,844 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-01-10 07:53:31,844 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-01-10 07:53:31,845 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2025-01-10 07:53:31,845 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:31,845 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-01-10 07:53:31,845 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-01-10 07:53:31,846 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration16_Loop [2025-01-10 07:53:31,846 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-01-10 07:53:31,846 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-01-10 07:53:31,858 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,862 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,864 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,865 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,868 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,870 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,871 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,873 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,874 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,876 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,877 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,879 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,883 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,884 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,887 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,890 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,892 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,893 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,895 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,896 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,897 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,904 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,906 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,907 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,909 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,910 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,913 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,915 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,916 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,919 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,921 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,922 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,924 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,925 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,928 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,930 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,931 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,932 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,934 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,935 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,936 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,938 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,939 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,942 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,944 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,945 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,947 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,948 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,950 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,953 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:31,954 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,190 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-01-10 07:53:32,191 INFO L365 LassoAnalysis]: Checking for nontermination... [2025-01-10 07:53:32,193 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,193 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,195 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,197 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-01-10 07:53:32,198 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:32,198 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:32,211 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:32,211 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:32,217 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2025-01-10 07:53:32,218 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,218 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,219 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,220 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-01-10 07:53:32,221 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:32,221 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:32,233 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:32,233 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:32,239 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2025-01-10 07:53:32,239 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,239 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,241 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,242 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-01-10 07:53:32,243 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:32,243 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:32,255 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:32,255 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret10#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:32,260 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2025-01-10 07:53:32,260 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,260 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,262 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,262 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-01-10 07:53:32,264 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:32,264 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:32,277 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:32,277 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:32,283 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:32,283 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,283 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,285 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,286 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-01-10 07:53:32,288 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:32,288 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:32,299 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:32,299 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:32,306 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:32,307 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,307 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,309 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,310 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-01-10 07:53:32,313 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:32,313 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:32,325 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:32,325 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret9#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret9#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:32,331 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2025-01-10 07:53:32,331 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,332 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,334 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,337 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-01-10 07:53:32,337 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:32,337 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:32,349 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:32,349 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:32,355 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2025-01-10 07:53:32,355 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,355 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,357 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,358 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-01-10 07:53:32,359 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:32,359 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:32,369 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:32,369 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret12#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret12#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:32,375 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2025-01-10 07:53:32,375 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,375 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,377 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,378 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2025-01-10 07:53:32,379 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:32,379 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:32,397 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:32,397 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:32,402 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:32,403 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,403 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,404 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,405 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2025-01-10 07:53:32,406 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:32,406 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:32,416 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:32,416 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:32,422 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:32,422 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,422 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,423 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,425 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2025-01-10 07:53:32,425 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:32,426 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:32,443 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:53:32,443 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:53:32,449 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2025-01-10 07:53:32,450 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,450 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,451 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,452 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2025-01-10 07:53:32,453 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:53:32,453 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:32,471 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2025-01-10 07:53:32,471 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,471 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,476 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,478 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2025-01-10 07:53:32,478 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2025-01-10 07:53:32,478 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:53:32,491 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2025-01-10 07:53:32,496 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2025-01-10 07:53:32,497 INFO L204 LassoAnalysis]: Preferences: [2025-01-10 07:53:32,497 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-01-10 07:53:32,497 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-01-10 07:53:32,497 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-01-10 07:53:32,497 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-01-10 07:53:32,497 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,497 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-01-10 07:53:32,497 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-01-10 07:53:32,497 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.03.cil.c_Iteration16_Loop [2025-01-10 07:53:32,497 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-01-10 07:53:32,497 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-01-10 07:53:32,499 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,504 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,508 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,510 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,513 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,516 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,519 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,520 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,521 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,524 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,528 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,530 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,533 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,541 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,545 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,549 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,551 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,552 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,554 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,556 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,562 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,563 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,564 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,566 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,567 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,572 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,579 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,580 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,582 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,583 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,586 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,588 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,589 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,590 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,592 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,594 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,599 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,602 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,603 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,605 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,606 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,607 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,608 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,610 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,611 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,613 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,614 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,618 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,621 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,622 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,624 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:53:32,860 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-01-10 07:53:32,867 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-01-10 07:53:32,869 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,869 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,870 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,872 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2025-01-10 07:53:32,874 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:32,884 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:32,885 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:32,885 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:32,885 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:32,885 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:32,888 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:32,888 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:32,889 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:32,894 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2025-01-10 07:53:32,895 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,895 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,896 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,898 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2025-01-10 07:53:32,899 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:32,909 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:32,909 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:32,909 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:32,909 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:32,909 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:32,909 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:32,909 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:32,910 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:32,915 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:32,916 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,916 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,917 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,918 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2025-01-10 07:53:32,919 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:32,928 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:32,928 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:32,928 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:32,928 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:32,928 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:32,929 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:32,929 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:32,930 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:32,935 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:32,936 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,936 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,937 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,939 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2025-01-10 07:53:32,939 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:32,949 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:32,949 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:32,949 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:32,949 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:32,949 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:32,950 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:32,950 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:32,951 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:32,956 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2025-01-10 07:53:32,957 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,957 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,958 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,960 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2025-01-10 07:53:32,961 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:32,970 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:32,970 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:32,970 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:32,970 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:32,970 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:32,971 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:32,971 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:32,972 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:32,977 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:32,977 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,977 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:32,979 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:32,979 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2025-01-10 07:53:32,980 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:32,990 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:32,990 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:32,990 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:32,990 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:32,990 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:32,993 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:32,993 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:32,994 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:32,999 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2025-01-10 07:53:32,999 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:32,999 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:33,001 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:33,002 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2025-01-10 07:53:33,002 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:33,012 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:33,012 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:33,012 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:33,012 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:33,012 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:33,013 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:33,013 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:33,014 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:33,023 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2025-01-10 07:53:33,023 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:33,023 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:33,025 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:33,026 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2025-01-10 07:53:33,028 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:33,038 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:33,038 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:33,038 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:33,038 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:33,038 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:33,038 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:33,038 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:33,040 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:33,045 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2025-01-10 07:53:33,045 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:33,045 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:33,047 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:33,049 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2025-01-10 07:53:33,050 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:33,060 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:33,060 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:33,060 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:33,060 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:33,060 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:33,061 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:33,061 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:33,062 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:33,067 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:33,068 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:33,068 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:33,069 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:33,071 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2025-01-10 07:53:33,072 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:33,082 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:33,082 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:33,082 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:33,082 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2025-01-10 07:53:33,082 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:33,082 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2025-01-10 07:53:33,082 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:33,084 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:33,090 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:33,090 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:33,090 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:33,092 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:33,093 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2025-01-10 07:53:33,094 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:33,104 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:33,104 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:33,104 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:33,104 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2025-01-10 07:53:33,104 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:33,105 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2025-01-10 07:53:33,105 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:33,106 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:53:33,112 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:33,112 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:33,112 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:33,114 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:33,115 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2025-01-10 07:53:33,118 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:53:33,128 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:53:33,128 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:53:33,128 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:53:33,128 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:53:33,128 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:53:33,129 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:53:33,129 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:53:33,131 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-01-10 07:53:33,137 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2025-01-10 07:53:33,139 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2025-01-10 07:53:33,140 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:53:33,141 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:53:33,146 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:53:33,147 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2025-01-10 07:53:33,147 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-01-10 07:53:33,147 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2025-01-10 07:53:33,147 INFO L474 LassoAnalysis]: Proved termination. [2025-01-10 07:53:33,148 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2025-01-10 07:53:33,154 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:33,157 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-01-10 07:53:33,179 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:33,194 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-01-10 07:53:33,206 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-01-10 07:53:33,206 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:33,206 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:33,208 INFO L256 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-01-10 07:53:33,209 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:53:33,268 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 63 statements into 1 equivalence classes. [2025-01-10 07:53:33,279 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 63 of 63 statements. [2025-01-10 07:53:33,280 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:33,280 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:33,280 INFO L256 TraceCheckSpWp]: Trace formula consists of 136 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-01-10 07:53:33,281 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:53:33,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:33,403 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2025-01-10 07:53:33,404 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 2375 states and 3154 transitions. cyclomatic complexity: 783 Second operand has 5 states, 5 states have (on average 22.4) internal successors, (112), 5 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:33,537 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 2375 states and 3154 transitions. cyclomatic complexity: 783. Second operand has 5 states, 5 states have (on average 22.4) internal successors, (112), 5 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 6213 states and 8291 transitions. Complement of second has 5 states. [2025-01-10 07:53:33,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-01-10 07:53:33,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 22.4) internal successors, (112), 5 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:33,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 361 transitions. [2025-01-10 07:53:33,541 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 361 transitions. Stem has 49 letters. Loop has 63 letters. [2025-01-10 07:53:33,542 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-01-10 07:53:33,543 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 361 transitions. Stem has 112 letters. Loop has 63 letters. [2025-01-10 07:53:33,544 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-01-10 07:53:33,546 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 361 transitions. Stem has 49 letters. Loop has 126 letters. [2025-01-10 07:53:33,546 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-01-10 07:53:33,546 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6213 states and 8291 transitions. [2025-01-10 07:53:33,566 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4174 [2025-01-10 07:53:33,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6213 states to 6201 states and 8279 transitions. [2025-01-10 07:53:33,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4272 [2025-01-10 07:53:33,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4295 [2025-01-10 07:53:33,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6201 states and 8279 transitions. [2025-01-10 07:53:33,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:53:33,600 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6201 states and 8279 transitions. [2025-01-10 07:53:33,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6201 states and 8279 transitions. [2025-01-10 07:53:33,674 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2025-01-10 07:53:33,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6201 to 6166. [2025-01-10 07:53:33,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6166 states, 6166 states have (on average 1.3353876094712942) internal successors, (8234), 6165 states have internal predecessors, (8234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:33,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6166 states to 6166 states and 8234 transitions. [2025-01-10 07:53:33,718 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6166 states and 8234 transitions. [2025-01-10 07:53:33,718 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:33,718 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:33,718 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:33,719 INFO L87 Difference]: Start difference. First operand 6166 states and 8234 transitions. Second operand has 3 states, 3 states have (on average 37.333333333333336) internal successors, (112), 3 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:33,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:33,763 INFO L93 Difference]: Finished difference Result 6496 states and 8576 transitions. [2025-01-10 07:53:33,763 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6496 states and 8576 transitions. [2025-01-10 07:53:33,785 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4394 [2025-01-10 07:53:33,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6496 states to 6496 states and 8576 transitions. [2025-01-10 07:53:33,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4480 [2025-01-10 07:53:33,807 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4480 [2025-01-10 07:53:33,807 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6496 states and 8576 transitions. [2025-01-10 07:53:33,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:53:33,808 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6496 states and 8576 transitions. [2025-01-10 07:53:33,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6496 states and 8576 transitions. [2025-01-10 07:53:33,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6496 to 6166. [2025-01-10 07:53:33,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6166 states, 6166 states have (on average 1.3256568277651637) internal successors, (8174), 6165 states have internal predecessors, (8174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:33,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6166 states to 6166 states and 8174 transitions. [2025-01-10 07:53:33,893 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6166 states and 8174 transitions. [2025-01-10 07:53:33,893 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:33,893 INFO L432 stractBuchiCegarLoop]: Abstraction has 6166 states and 8174 transitions. [2025-01-10 07:53:33,893 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-01-10 07:53:33,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6166 states and 8174 transitions. [2025-01-10 07:53:33,907 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4174 [2025-01-10 07:53:33,907 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:33,907 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:33,907 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:33,907 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:33,908 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-01-10 07:53:33,908 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2025-01-10 07:53:33,908 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:33,908 INFO L85 PathProgramCache]: Analyzing trace with hash -1276375256, now seen corresponding path program 1 times [2025-01-10 07:53:33,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:33,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175838004] [2025-01-10 07:53:33,908 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:33,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:33,913 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-01-10 07:53:33,915 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-01-10 07:53:33,915 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:33,915 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:33,917 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:33,919 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-01-10 07:53:33,922 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-01-10 07:53:33,922 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:33,922 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:33,925 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:33,925 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:33,925 INFO L85 PathProgramCache]: Analyzing trace with hash -149459294, now seen corresponding path program 1 times [2025-01-10 07:53:33,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:33,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029014885] [2025-01-10 07:53:33,925 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:33,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:33,927 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-01-10 07:53:33,928 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-01-10 07:53:33,928 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:33,928 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:33,928 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:33,929 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-01-10 07:53:33,929 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-01-10 07:53:33,929 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:33,929 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:33,930 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:33,930 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:33,930 INFO L85 PathProgramCache]: Analyzing trace with hash 1819029787, now seen corresponding path program 1 times [2025-01-10 07:53:33,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:33,930 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979283137] [2025-01-10 07:53:33,930 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:33,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:33,934 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 61 statements into 1 equivalence classes. [2025-01-10 07:53:33,936 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 61 of 61 statements. [2025-01-10 07:53:33,936 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:33,936 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:33,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:33,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:33,969 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979283137] [2025-01-10 07:53:33,969 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [979283137] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:33,969 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:33,969 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:33,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2135042885] [2025-01-10 07:53:33,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:34,003 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:34,004 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:34,004 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:34,004 INFO L87 Difference]: Start difference. First operand 6166 states and 8174 transitions. cyclomatic complexity: 2020 Second operand has 3 states, 3 states have (on average 20.333333333333332) internal successors, (61), 3 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:34,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:34,093 INFO L93 Difference]: Finished difference Result 10066 states and 13211 transitions. [2025-01-10 07:53:34,093 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10066 states and 13211 transitions. [2025-01-10 07:53:34,129 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 6405 [2025-01-10 07:53:34,156 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10066 states to 10066 states and 13211 transitions. [2025-01-10 07:53:34,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7014 [2025-01-10 07:53:34,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7014 [2025-01-10 07:53:34,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10066 states and 13211 transitions. [2025-01-10 07:53:34,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:53:34,162 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10066 states and 13211 transitions. [2025-01-10 07:53:34,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10066 states and 13211 transitions. [2025-01-10 07:53:34,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10066 to 9832. [2025-01-10 07:53:34,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9832 states, 9832 states have (on average 1.3137713588283157) internal successors, (12917), 9831 states have internal predecessors, (12917), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:34,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9832 states to 9832 states and 12917 transitions. [2025-01-10 07:53:34,282 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9832 states and 12917 transitions. [2025-01-10 07:53:34,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:34,282 INFO L432 stractBuchiCegarLoop]: Abstraction has 9832 states and 12917 transitions. [2025-01-10 07:53:34,282 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-01-10 07:53:34,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9832 states and 12917 transitions. [2025-01-10 07:53:34,304 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 6249 [2025-01-10 07:53:34,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:34,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:34,304 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:34,304 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:34,305 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-01-10 07:53:34,305 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2025-01-10 07:53:34,305 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:34,305 INFO L85 PathProgramCache]: Analyzing trace with hash -382888918, now seen corresponding path program 1 times [2025-01-10 07:53:34,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:34,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92905914] [2025-01-10 07:53:34,305 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:34,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:34,332 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-01-10 07:53:34,333 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-01-10 07:53:34,333 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:34,333 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:34,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:34,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:34,343 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [92905914] [2025-01-10 07:53:34,343 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [92905914] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:34,343 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:34,344 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:34,344 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [799095939] [2025-01-10 07:53:34,344 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:34,344 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:53:34,344 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:34,344 INFO L85 PathProgramCache]: Analyzing trace with hash -149459294, now seen corresponding path program 2 times [2025-01-10 07:53:34,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:34,344 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345094606] [2025-01-10 07:53:34,344 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:53:34,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:34,346 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 11 statements into 1 equivalence classes. [2025-01-10 07:53:34,346 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-01-10 07:53:34,346 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:53:34,346 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:34,347 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:34,347 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-01-10 07:53:34,347 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-01-10 07:53:34,347 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:34,347 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:34,348 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:34,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:34,384 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:34,384 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:34,384 INFO L87 Difference]: Start difference. First operand 9832 states and 12917 transitions. cyclomatic complexity: 3107 Second operand has 3 states, 3 states have (on average 16.666666666666668) internal successors, (50), 3 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:34,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:34,410 INFO L93 Difference]: Finished difference Result 7357 states and 9682 transitions. [2025-01-10 07:53:34,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7357 states and 9682 transitions. [2025-01-10 07:53:34,435 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 4981 [2025-01-10 07:53:34,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7357 states to 7357 states and 9682 transitions. [2025-01-10 07:53:34,456 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5154 [2025-01-10 07:53:34,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5154 [2025-01-10 07:53:34,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7357 states and 9682 transitions. [2025-01-10 07:53:34,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:53:34,460 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7357 states and 9682 transitions. [2025-01-10 07:53:34,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7357 states and 9682 transitions. [2025-01-10 07:53:34,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7357 to 7357. [2025-01-10 07:53:34,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7357 states, 7357 states have (on average 1.3160255538942505) internal successors, (9682), 7356 states have internal predecessors, (9682), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:34,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7357 states to 7357 states and 9682 transitions. [2025-01-10 07:53:34,551 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7357 states and 9682 transitions. [2025-01-10 07:53:34,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:34,552 INFO L432 stractBuchiCegarLoop]: Abstraction has 7357 states and 9682 transitions. [2025-01-10 07:53:34,552 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-01-10 07:53:34,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7357 states and 9682 transitions. [2025-01-10 07:53:34,568 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 4981 [2025-01-10 07:53:34,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:34,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:34,569 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:34,569 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:34,569 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-01-10 07:53:34,569 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" [2025-01-10 07:53:34,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:34,569 INFO L85 PathProgramCache]: Analyzing trace with hash -1276375256, now seen corresponding path program 2 times [2025-01-10 07:53:34,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:34,569 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992821713] [2025-01-10 07:53:34,569 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:53:34,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:34,575 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 50 statements into 1 equivalence classes. [2025-01-10 07:53:34,578 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-01-10 07:53:34,578 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:53:34,578 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:34,578 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:34,579 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-01-10 07:53:34,581 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-01-10 07:53:34,581 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:34,581 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:34,585 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:34,586 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:34,586 INFO L85 PathProgramCache]: Analyzing trace with hash -2016961850, now seen corresponding path program 1 times [2025-01-10 07:53:34,586 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:34,586 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [67674797] [2025-01-10 07:53:34,586 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:34,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:34,588 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-01-10 07:53:34,588 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-01-10 07:53:34,588 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:34,588 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:34,588 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:34,589 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-01-10 07:53:34,589 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-01-10 07:53:34,589 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:34,590 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:34,590 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:34,591 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:34,591 INFO L85 PathProgramCache]: Analyzing trace with hash -84565249, now seen corresponding path program 1 times [2025-01-10 07:53:34,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:34,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876947976] [2025-01-10 07:53:34,591 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:34,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:34,595 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 63 statements into 1 equivalence classes. [2025-01-10 07:53:34,597 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 63 of 63 statements. [2025-01-10 07:53:34,597 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:34,597 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:34,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:34,612 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:34,612 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876947976] [2025-01-10 07:53:34,612 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1876947976] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:34,612 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:34,612 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:53:34,612 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [707455809] [2025-01-10 07:53:34,613 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:34,645 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:34,645 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:34,645 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:34,645 INFO L87 Difference]: Start difference. First operand 7357 states and 9682 transitions. cyclomatic complexity: 2341 Second operand has 3 states, 3 states have (on average 21.0) internal successors, (63), 3 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:34,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:34,694 INFO L93 Difference]: Finished difference Result 12960 states and 16921 transitions. [2025-01-10 07:53:34,694 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12960 states and 16921 transitions. [2025-01-10 07:53:34,728 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 8654 [2025-01-10 07:53:34,758 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12960 states to 12960 states and 16921 transitions. [2025-01-10 07:53:34,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8942 [2025-01-10 07:53:34,763 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8942 [2025-01-10 07:53:34,763 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12960 states and 16921 transitions. [2025-01-10 07:53:34,764 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:53:34,764 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12960 states and 16921 transitions. [2025-01-10 07:53:34,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12960 states and 16921 transitions. [2025-01-10 07:53:34,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12960 to 12770. [2025-01-10 07:53:34,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12770 states, 12770 states have (on average 1.3070477682067345) internal successors, (16691), 12769 states have internal predecessors, (16691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:34,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12770 states to 12770 states and 16691 transitions. [2025-01-10 07:53:34,946 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12770 states and 16691 transitions. [2025-01-10 07:53:34,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:34,947 INFO L432 stractBuchiCegarLoop]: Abstraction has 12770 states and 16691 transitions. [2025-01-10 07:53:34,947 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-01-10 07:53:34,947 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12770 states and 16691 transitions. [2025-01-10 07:53:34,973 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 8464 [2025-01-10 07:53:34,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:34,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:34,974 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:34,974 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:34,974 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-01-10 07:53:34,974 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume !(0 == ~t3_st~0);" [2025-01-10 07:53:34,975 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:34,975 INFO L85 PathProgramCache]: Analyzing trace with hash -1276375256, now seen corresponding path program 3 times [2025-01-10 07:53:34,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:34,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [595634739] [2025-01-10 07:53:34,975 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:53:34,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:34,978 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 50 statements into 1 equivalence classes. [2025-01-10 07:53:34,980 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-01-10 07:53:34,980 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:53:34,980 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:34,980 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:34,981 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-01-10 07:53:34,982 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-01-10 07:53:34,983 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:34,983 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:34,985 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:34,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:34,985 INFO L85 PathProgramCache]: Analyzing trace with hash -1273863518, now seen corresponding path program 1 times [2025-01-10 07:53:34,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:34,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296597949] [2025-01-10 07:53:34,986 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:34,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:34,987 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes. [2025-01-10 07:53:34,988 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements. [2025-01-10 07:53:34,988 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:34,988 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:34,988 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:34,988 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 15 statements into 1 equivalence classes. [2025-01-10 07:53:34,989 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 15 of 15 statements. [2025-01-10 07:53:34,989 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:34,989 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:34,990 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:34,990 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:34,990 INFO L85 PathProgramCache]: Analyzing trace with hash 333398171, now seen corresponding path program 1 times [2025-01-10 07:53:34,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:34,990 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372436143] [2025-01-10 07:53:34,990 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:34,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:34,993 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 65 statements into 1 equivalence classes. [2025-01-10 07:53:34,995 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 65 of 65 statements. [2025-01-10 07:53:34,995 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:34,995 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:53:35,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:53:35,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:53:35,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [372436143] [2025-01-10 07:53:35,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [372436143] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:53:35,012 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:53:35,012 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:53:35,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386126042] [2025-01-10 07:53:35,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:53:35,047 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:53:35,047 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:53:35,048 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:53:35,048 INFO L87 Difference]: Start difference. First operand 12770 states and 16691 transitions. cyclomatic complexity: 3937 Second operand has 3 states, 2 states have (on average 32.5) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:35,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:53:35,101 INFO L93 Difference]: Finished difference Result 15400 states and 20077 transitions. [2025-01-10 07:53:35,101 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15400 states and 20077 transitions. [2025-01-10 07:53:35,194 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 10246 [2025-01-10 07:53:35,226 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15400 states to 15400 states and 20077 transitions. [2025-01-10 07:53:35,226 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10630 [2025-01-10 07:53:35,235 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10630 [2025-01-10 07:53:35,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15400 states and 20077 transitions. [2025-01-10 07:53:35,237 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:53:35,237 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15400 states and 20077 transitions. [2025-01-10 07:53:35,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15400 states and 20077 transitions. [2025-01-10 07:53:35,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15400 to 15400. [2025-01-10 07:53:35,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15400 states, 15400 states have (on average 1.3037012987012988) internal successors, (20077), 15399 states have internal predecessors, (20077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:53:35,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15400 states to 15400 states and 20077 transitions. [2025-01-10 07:53:35,435 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15400 states and 20077 transitions. [2025-01-10 07:53:35,435 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:53:35,435 INFO L432 stractBuchiCegarLoop]: Abstraction has 15400 states and 20077 transitions. [2025-01-10 07:53:35,436 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-01-10 07:53:35,436 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15400 states and 20077 transitions. [2025-01-10 07:53:35,466 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 10246 [2025-01-10 07:53:35,466 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:53:35,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:53:35,467 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:35,467 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:53:35,467 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-01-10 07:53:35,467 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" [2025-01-10 07:53:35,467 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:35,467 INFO L85 PathProgramCache]: Analyzing trace with hash -1276375256, now seen corresponding path program 4 times [2025-01-10 07:53:35,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:35,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722160521] [2025-01-10 07:53:35,468 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:53:35,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:35,472 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 50 statements into 2 equivalence classes. [2025-01-10 07:53:35,474 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 50 of 50 statements. [2025-01-10 07:53:35,474 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:53:35,474 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:35,474 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:35,476 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-01-10 07:53:35,479 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-01-10 07:53:35,479 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:35,479 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:35,482 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:35,483 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:35,483 INFO L85 PathProgramCache]: Analyzing trace with hash -117175041, now seen corresponding path program 1 times [2025-01-10 07:53:35,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:35,483 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481401114] [2025-01-10 07:53:35,483 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:35,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:35,485 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes. [2025-01-10 07:53:35,485 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements. [2025-01-10 07:53:35,485 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:35,486 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:35,486 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:35,486 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes. [2025-01-10 07:53:35,487 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements. [2025-01-10 07:53:35,487 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:35,487 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:35,488 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:35,488 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:53:35,488 INFO L85 PathProgramCache]: Analyzing trace with hash -1726918472, now seen corresponding path program 1 times [2025-01-10 07:53:35,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:53:35,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679513963] [2025-01-10 07:53:35,489 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:53:35,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:53:35,492 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-10 07:53:35,495 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-10 07:53:35,495 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:35,495 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:35,495 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:35,496 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-01-10 07:53:35,498 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-01-10 07:53:35,498 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:35,498 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:35,505 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:53:36,150 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-01-10 07:53:36,155 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-01-10 07:53:36,155 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:36,155 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:36,155 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:53:36,163 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-01-10 07:53:36,167 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-01-10 07:53:36,167 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:53:36,167 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:53:36,267 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 10.01 07:53:36 BoogieIcfgContainer [2025-01-10 07:53:36,270 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-01-10 07:53:36,271 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-01-10 07:53:36,271 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-01-10 07:53:36,271 INFO L274 PluginConnector]: Witness Printer initialized [2025-01-10 07:53:36,272 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:53:28" (3/4) ... [2025-01-10 07:53:36,273 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-01-10 07:53:36,323 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-01-10 07:53:36,323 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-01-10 07:53:36,325 INFO L158 Benchmark]: Toolchain (without parser) took 8777.32ms. Allocated memory was 167.8MB in the beginning and 562.0MB in the end (delta: 394.3MB). Free memory was 123.8MB in the beginning and 293.9MB in the end (delta: -170.1MB). Peak memory consumption was 224.2MB. Max. memory is 16.1GB. [2025-01-10 07:53:36,325 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 201.3MB. Free memory is still 120.5MB. There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:53:36,325 INFO L158 Benchmark]: CACSL2BoogieTranslator took 260.66ms. Allocated memory is still 167.8MB. Free memory was 123.3MB in the beginning and 109.3MB in the end (delta: 14.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-01-10 07:53:36,325 INFO L158 Benchmark]: Boogie Procedure Inliner took 44.93ms. Allocated memory is still 167.8MB. Free memory was 109.3MB in the beginning and 106.5MB in the end (delta: 2.8MB). There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:53:36,325 INFO L158 Benchmark]: Boogie Preprocessor took 71.02ms. Allocated memory is still 167.8MB. Free memory was 106.5MB in the beginning and 102.7MB in the end (delta: 3.7MB). There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:53:36,325 INFO L158 Benchmark]: RCFGBuilder took 678.03ms. Allocated memory is still 167.8MB. Free memory was 102.7MB in the beginning and 63.7MB in the end (delta: 39.0MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2025-01-10 07:53:36,325 INFO L158 Benchmark]: BuchiAutomizer took 7666.09ms. Allocated memory was 167.8MB in the beginning and 562.0MB in the end (delta: 394.3MB). Free memory was 63.7MB in the beginning and 302.4MB in the end (delta: -238.7MB). Peak memory consumption was 157.1MB. Max. memory is 16.1GB. [2025-01-10 07:53:36,326 INFO L158 Benchmark]: Witness Printer took 52.61ms. Allocated memory is still 562.0MB. Free memory was 302.4MB in the beginning and 293.9MB in the end (delta: 8.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-01-10 07:53:36,329 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 201.3MB. Free memory is still 120.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 260.66ms. Allocated memory is still 167.8MB. Free memory was 123.3MB in the beginning and 109.3MB in the end (delta: 14.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 44.93ms. Allocated memory is still 167.8MB. Free memory was 109.3MB in the beginning and 106.5MB in the end (delta: 2.8MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 71.02ms. Allocated memory is still 167.8MB. Free memory was 106.5MB in the beginning and 102.7MB in the end (delta: 3.7MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 678.03ms. Allocated memory is still 167.8MB. Free memory was 102.7MB in the beginning and 63.7MB in the end (delta: 39.0MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 7666.09ms. Allocated memory was 167.8MB in the beginning and 562.0MB in the end (delta: 394.3MB). Free memory was 63.7MB in the beginning and 302.4MB in the end (delta: -238.7MB). Peak memory consumption was 157.1MB. Max. memory is 16.1GB. * Witness Printer took 52.61ms. Allocated memory is still 562.0MB. Free memory was 302.4MB in the beginning and 293.9MB in the end (delta: 8.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (20 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * E_3) + 1) and consists of 3 locations. 20 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 15400 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.5s and 21 iterations. TraceHistogramMax:1. Analysis of lassos took 4.2s. Construction of modules took 0.5s. Büchi inclusion checks took 2.3s. Highest rank in rank-based complementation 3. Minimization of det autom 15. Minimization of nondet autom 6. Automata minimization 1.0s AutomataMinimizationTime, 21 MinimizatonAttempts, 2884 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 0.5s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 6982 SdHoareTripleChecker+Valid, 0.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 6981 mSDsluCounter, 18233 SdHoareTripleChecker+Invalid, 0.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 8503 mSDsCounter, 192 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 665 IncrementalHoareTripleChecker+Invalid, 857 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 192 mSolverCounterUnsat, 9730 mSDtfsCounter, 665 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc3 concLT1 SILN1 SILU0 SILI10 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital86 mio100 ax100 hnf100 lsp11 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 16ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 11 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.2s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 1]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE !(\read(tmp_ndt_1)) [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp_ndt_2)) [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE !(\read(tmp_ndt_3)) [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 1]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int M_E = 2; [L38] int T1_E = 2; [L39] int T2_E = 2; [L40] int T3_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0] [L697] int __retres1 ; [L701] CALL init_model() [L610] m_i = 1 [L611] t1_i = 1 [L612] t2_i = 1 [L613] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L701] RET init_model() [L702] CALL start_simulation() [L638] int kernel_st ; [L639] int tmp ; [L640] int tmp___0 ; [L644] kernel_st = 0 [L645] FCALL update_channels() [L646] CALL init_threads() [L281] COND TRUE m_i == 1 [L282] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L286] COND TRUE t1_i == 1 [L287] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L291] COND TRUE t2_i == 1 [L292] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L296] COND TRUE t3_i == 1 [L297] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L646] RET init_threads() [L647] CALL fire_delta_events() [L418] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L423] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L428] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L433] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L438] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L443] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L448] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L647] RET fire_delta_events() [L648] CALL activate_threads() [L501] int tmp ; [L502] int tmp___0 ; [L503] int tmp___1 ; [L504] int tmp___2 ; [L508] CALL, EXPR is_master_triggered() [L194] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L197] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L207] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L209] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L508] RET, EXPR is_master_triggered() [L508] tmp = is_master_triggered() [L510] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] CALL, EXPR is_transmit1_triggered() [L213] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L216] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L226] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L228] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L516] RET, EXPR is_transmit1_triggered() [L516] tmp___0 = is_transmit1_triggered() [L518] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] CALL, EXPR is_transmit2_triggered() [L232] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L235] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L245] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L247] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L524] RET, EXPR is_transmit2_triggered() [L524] tmp___1 = is_transmit2_triggered() [L526] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] CALL, EXPR is_transmit3_triggered() [L251] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L254] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L264] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L266] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L532] RET, EXPR is_transmit3_triggered() [L532] tmp___2 = is_transmit3_triggered() [L534] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L648] RET activate_threads() [L649] CALL reset_delta_events() [L461] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L466] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L471] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L476] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L481] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L486] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L491] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] [L649] RET reset_delta_events() [L655] kernel_st = 1 [L656] CALL eval() [L337] int tmp ; VAL [E_1=2, E_2=2, E_3=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0] Loop: [L344] CALL, EXPR exists_runnable_thread() [L306] int __retres1 ; [L309] COND TRUE m_st == 0 [L310] __retres1 = 1 [L332] return (__retres1); [L344] RET, EXPR exists_runnable_thread() [L344] tmp = exists_runnable_thread() [L346] COND TRUE \read(tmp) [L351] COND TRUE m_st == 0 [L352] int tmp_ndt_1; [L353] tmp_ndt_1 = __VERIFIER_nondet_int() [L354] COND FALSE !(\read(tmp_ndt_1)) [L365] COND TRUE t1_st == 0 [L366] int tmp_ndt_2; [L367] tmp_ndt_2 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp_ndt_2)) [L379] COND TRUE t2_st == 0 [L380] int tmp_ndt_3; [L381] tmp_ndt_3 = __VERIFIER_nondet_int() [L382] COND FALSE !(\read(tmp_ndt_3)) [L393] COND TRUE t3_st == 0 [L394] int tmp_ndt_4; [L395] tmp_ndt_4 = __VERIFIER_nondet_int() [L396] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-01-10 07:53:36,345 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)