./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 15:39:18,922 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 15:39:18,964 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf [2025-03-04 15:39:18,969 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 15:39:18,969 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 15:39:18,969 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 15:39:18,992 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 15:39:18,992 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 15:39:18,992 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 15:39:18,992 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 15:39:18,992 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 15:39:18,993 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 15:39:18,993 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 15:39:18,993 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 15:39:18,994 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 15:39:18,994 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 15:39:18,994 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 15:39:18,994 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 15:39:18,994 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 15:39:18,994 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 15:39:18,994 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 15:39:18,994 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 15:39:18,994 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 15:39:18,994 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 15:39:18,994 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 15:39:18,995 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 15:39:18,995 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 15:39:18,995 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 15:39:18,995 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 15:39:18,995 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 15:39:18,995 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 15:39:18,995 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 15:39:18,995 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 15:39:18,995 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 15:39:18,995 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 15:39:18,995 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 15:39:18,996 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 15:39:18,996 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe [2025-03-04 15:39:19,177 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 15:39:19,184 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 15:39:19,186 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 15:39:19,186 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 15:39:19,187 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 15:39:19,187 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2025-03-04 15:39:20,341 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/954d8cc26/39937625fa914b8bb6f898ad5b5aa41c/FLAG1fc6b7a89 [2025-03-04 15:39:20,599 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 15:39:20,599 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2025-03-04 15:39:20,609 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/954d8cc26/39937625fa914b8bb6f898ad5b5aa41c/FLAG1fc6b7a89 [2025-03-04 15:39:20,916 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/954d8cc26/39937625fa914b8bb6f898ad5b5aa41c [2025-03-04 15:39:20,920 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 15:39:20,922 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 15:39:20,925 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 15:39:20,925 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 15:39:20,931 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 15:39:20,934 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 03:39:20" (1/1) ... [2025-03-04 15:39:20,935 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4ba96874 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:20, skipping insertion in model container [2025-03-04 15:39:20,936 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 03:39:20" (1/1) ... [2025-03-04 15:39:20,958 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 15:39:21,156 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 15:39:21,165 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 15:39:21,201 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 15:39:21,220 INFO L204 MainTranslator]: Completed translation [2025-03-04 15:39:21,221 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21 WrapperNode [2025-03-04 15:39:21,221 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 15:39:21,222 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 15:39:21,223 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 15:39:21,223 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 15:39:21,229 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21" (1/1) ... [2025-03-04 15:39:21,238 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21" (1/1) ... [2025-03-04 15:39:21,252 INFO L138 Inliner]: procedures = 109, calls = 13, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 31 [2025-03-04 15:39:21,253 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 15:39:21,253 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 15:39:21,253 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 15:39:21,254 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 15:39:21,258 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21" (1/1) ... [2025-03-04 15:39:21,259 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21" (1/1) ... [2025-03-04 15:39:21,260 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21" (1/1) ... [2025-03-04 15:39:21,271 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [4, 3]. 57 percent of accesses are in the largest equivalence class. The 0 initializations are split as follows [0, 0]. The 3 writes are split as follows [2, 1]. [2025-03-04 15:39:21,271 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21" (1/1) ... [2025-03-04 15:39:21,271 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21" (1/1) ... [2025-03-04 15:39:21,275 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21" (1/1) ... [2025-03-04 15:39:21,276 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21" (1/1) ... [2025-03-04 15:39:21,279 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21" (1/1) ... [2025-03-04 15:39:21,279 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21" (1/1) ... [2025-03-04 15:39:21,280 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 15:39:21,281 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 15:39:21,281 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 15:39:21,281 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 15:39:21,282 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21" (1/1) ... [2025-03-04 15:39:21,285 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:39:21,295 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:39:21,309 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:39:21,312 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 15:39:21,330 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-03-04 15:39:21,330 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-03-04 15:39:21,330 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-03-04 15:39:21,330 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-03-04 15:39:21,330 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-03-04 15:39:21,330 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-04 15:39:21,330 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 15:39:21,330 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 15:39:21,395 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 15:39:21,397 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 15:39:21,462 INFO L? ?]: Removed 4 outVars from TransFormulas that were not future-live. [2025-03-04 15:39:21,462 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 15:39:21,468 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 15:39:21,468 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-04 15:39:21,468 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 03:39:21 BoogieIcfgContainer [2025-03-04 15:39:21,468 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 15:39:21,469 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 15:39:21,469 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 15:39:21,472 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 15:39:21,472 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 15:39:21,473 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 03:39:20" (1/3) ... [2025-03-04 15:39:21,473 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4f1e34d0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 03:39:21, skipping insertion in model container [2025-03-04 15:39:21,473 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 15:39:21,473 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:39:21" (2/3) ... [2025-03-04 15:39:21,473 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4f1e34d0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 03:39:21, skipping insertion in model container [2025-03-04 15:39:21,473 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 15:39:21,474 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 03:39:21" (3/3) ... [2025-03-04 15:39:21,474 INFO L363 chiAutomizerObserver]: Analyzing ICFG Urban-2013WST-Fig2-modified1000-alloca.i [2025-03-04 15:39:21,512 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 15:39:21,512 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 15:39:21,512 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 15:39:21,513 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 15:39:21,513 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 15:39:21,513 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 15:39:21,513 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 15:39:21,513 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 15:39:21,516 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:21,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2025-03-04 15:39:21,529 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:39:21,529 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:39:21,532 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:39:21,532 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2025-03-04 15:39:21,532 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 15:39:21,532 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:21,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2025-03-04 15:39:21,534 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:39:21,534 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:39:21,534 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:39:21,534 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2025-03-04 15:39:21,539 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-04 15:39:21,540 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !true;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-04 15:39:21,543 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:21,543 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 1 times [2025-03-04 15:39:21,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:21,548 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829029278] [2025-03-04 15:39:21,548 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:39:21,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:21,596 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:21,606 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:21,607 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:21,607 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:21,607 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:39:21,609 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:21,616 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:21,617 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:21,617 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:21,627 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:39:21,629 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:21,630 INFO L85 PathProgramCache]: Analyzing trace with hash 1322586, now seen corresponding path program 1 times [2025-03-04 15:39:21,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:21,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1948785783] [2025-03-04 15:39:21,630 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:39:21,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:21,635 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-03-04 15:39:21,638 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-03-04 15:39:21,638 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:21,638 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:39:21,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:21,663 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:39:21,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1948785783] [2025-03-04 15:39:21,664 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1948785783] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:39:21,664 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:39:21,664 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 15:39:21,664 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1075996348] [2025-03-04 15:39:21,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:39:21,667 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:39:21,667 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:39:21,687 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-04 15:39:21,688 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-04 15:39:21,691 INFO L87 Difference]: Start difference. First operand has 11 states, 10 states have (on average 1.4) internal successors, (14), 10 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:21,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:39:21,695 INFO L93 Difference]: Finished difference Result 11 states and 12 transitions. [2025-03-04 15:39:21,695 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 12 transitions. [2025-03-04 15:39:21,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2025-03-04 15:39:21,699 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 7 states and 8 transitions. [2025-03-04 15:39:21,700 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2025-03-04 15:39:21,700 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2025-03-04 15:39:21,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7 states and 8 transitions. [2025-03-04 15:39:21,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:39:21,700 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions. [2025-03-04 15:39:21,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7 states and 8 transitions. [2025-03-04 15:39:21,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7 to 7. [2025-03-04 15:39:21,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:21,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 8 transitions. [2025-03-04 15:39:21,719 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions. [2025-03-04 15:39:21,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-04 15:39:21,723 INFO L432 stractBuchiCegarLoop]: Abstraction has 7 states and 8 transitions. [2025-03-04 15:39:21,724 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 15:39:21,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 8 transitions. [2025-03-04 15:39:21,725 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2025-03-04 15:39:21,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:39:21,726 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:39:21,726 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:39:21,726 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-03-04 15:39:21,726 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-04 15:39:21,726 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-04 15:39:21,728 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:21,728 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 2 times [2025-03-04 15:39:21,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:21,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [701858522] [2025-03-04 15:39:21,728 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:39:21,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:21,738 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:21,746 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:21,746 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:39:21,746 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:21,746 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:39:21,750 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:21,758 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:21,758 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:21,758 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:21,759 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:39:21,760 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:21,760 INFO L85 PathProgramCache]: Analyzing trace with hash 40999300, now seen corresponding path program 1 times [2025-03-04 15:39:21,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:21,760 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579255191] [2025-03-04 15:39:21,760 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:39:21,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:21,773 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-03-04 15:39:21,778 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-03-04 15:39:21,778 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:21,779 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:39:21,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:21,892 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:39:21,892 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579255191] [2025-03-04 15:39:21,892 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [579255191] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:39:21,892 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:39:21,892 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 15:39:21,892 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728828268] [2025-03-04 15:39:21,893 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:39:21,893 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:39:21,893 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:39:21,893 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 15:39:21,893 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 15:39:21,893 INFO L87 Difference]: Start difference. First operand 7 states and 8 transitions. cyclomatic complexity: 2 Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:21,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:39:21,935 INFO L93 Difference]: Finished difference Result 9 states and 10 transitions. [2025-03-04 15:39:21,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9 states and 10 transitions. [2025-03-04 15:39:21,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2025-03-04 15:39:21,936 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9 states to 9 states and 10 transitions. [2025-03-04 15:39:21,936 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2025-03-04 15:39:21,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2025-03-04 15:39:21,936 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 10 transitions. [2025-03-04 15:39:21,936 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:39:21,936 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2025-03-04 15:39:21,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 10 transitions. [2025-03-04 15:39:21,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2025-03-04 15:39:21,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 8 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:21,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 10 transitions. [2025-03-04 15:39:21,937 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2025-03-04 15:39:21,940 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 15:39:21,941 INFO L432 stractBuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2025-03-04 15:39:21,941 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 15:39:21,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 10 transitions. [2025-03-04 15:39:21,941 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2025-03-04 15:39:21,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:39:21,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:39:21,942 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:39:21,942 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1] [2025-03-04 15:39:21,942 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-04 15:39:21,942 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-04 15:39:21,942 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:21,942 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 3 times [2025-03-04 15:39:21,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:21,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [569761416] [2025-03-04 15:39:21,942 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:39:21,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:21,951 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:21,957 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:21,960 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 15:39:21,961 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:21,961 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:39:21,962 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:21,966 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:21,969 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:21,969 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:21,970 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:39:21,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:21,971 INFO L85 PathProgramCache]: Analyzing trace with hash 745656389, now seen corresponding path program 1 times [2025-03-04 15:39:21,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:21,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076585305] [2025-03-04 15:39:21,971 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:39:21,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:21,979 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-03-04 15:39:21,986 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-03-04 15:39:21,989 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:21,989 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:39:22,149 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:22,149 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:39:22,149 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1076585305] [2025-03-04 15:39:22,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1076585305] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:39:22,149 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1951685394] [2025-03-04 15:39:22,149 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:39:22,150 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:39:22,150 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:39:22,152 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:39:22,153 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2025-03-04 15:39:22,189 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-03-04 15:39:22,196 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-03-04 15:39:22,196 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:22,196 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:39:22,198 INFO L256 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 6 conjuncts are in the unsatisfiable core [2025-03-04 15:39:22,199 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:39:22,232 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-03-04 15:39:22,260 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:22,286 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:22,287 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:39:22,333 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:22,334 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1951685394] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:39:22,334 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:39:22,334 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5] total 10 [2025-03-04 15:39:22,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [270560066] [2025-03-04 15:39:22,334 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:39:22,334 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:39:22,334 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:39:22,335 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-04 15:39:22,335 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2025-03-04 15:39:22,335 INFO L87 Difference]: Start difference. First operand 9 states and 10 transitions. cyclomatic complexity: 2 Second operand has 10 states, 10 states have (on average 1.5) internal successors, (15), 10 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:22,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:39:22,413 INFO L93 Difference]: Finished difference Result 15 states and 16 transitions. [2025-03-04 15:39:22,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 16 transitions. [2025-03-04 15:39:22,414 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2025-03-04 15:39:22,414 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 16 transitions. [2025-03-04 15:39:22,414 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2025-03-04 15:39:22,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2025-03-04 15:39:22,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 16 transitions. [2025-03-04 15:39:22,414 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:39:22,414 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2025-03-04 15:39:22,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 16 transitions. [2025-03-04 15:39:22,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2025-03-04 15:39:22,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 14 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:22,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2025-03-04 15:39:22,415 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2025-03-04 15:39:22,417 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 15:39:22,419 INFO L432 stractBuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2025-03-04 15:39:22,419 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 15:39:22,419 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 16 transitions. [2025-03-04 15:39:22,420 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2025-03-04 15:39:22,421 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:39:22,421 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:39:22,421 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:39:22,421 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [5, 4, 1, 1, 1, 1] [2025-03-04 15:39:22,421 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-04 15:39:22,421 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-04 15:39:22,422 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:22,422 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 4 times [2025-03-04 15:39:22,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:22,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [422963773] [2025-03-04 15:39:22,422 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:39:22,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:22,429 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 15:39:22,446 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:22,447 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:39:22,447 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:22,447 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:39:22,448 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:22,449 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:22,449 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:22,449 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:22,451 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:39:22,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:22,451 INFO L85 PathProgramCache]: Analyzing trace with hash 551987976, now seen corresponding path program 2 times [2025-03-04 15:39:22,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:22,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689811065] [2025-03-04 15:39:22,451 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:39:22,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:22,457 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 13 statements into 2 equivalence classes. [2025-03-04 15:39:22,468 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 13 of 13 statements. [2025-03-04 15:39:22,469 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:39:22,469 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:39:22,904 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:22,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:39:22,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1689811065] [2025-03-04 15:39:22,904 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1689811065] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:39:22,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1949343071] [2025-03-04 15:39:22,904 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:39:22,905 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:39:22,905 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:39:22,908 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:39:22,910 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2025-03-04 15:39:22,954 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 13 statements into 2 equivalence classes. [2025-03-04 15:39:22,970 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 13 of 13 statements. [2025-03-04 15:39:22,970 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:39:22,970 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:39:22,971 INFO L256 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 12 conjuncts are in the unsatisfiable core [2025-03-04 15:39:22,973 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:39:22,977 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-03-04 15:39:22,988 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:23,008 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:23,032 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:23,079 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:23,098 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:23,098 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:39:23,189 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:23,189 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1949343071] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:39:23,189 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:39:23,190 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8] total 22 [2025-03-04 15:39:23,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1617757344] [2025-03-04 15:39:23,190 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:39:23,190 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:39:23,190 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:39:23,190 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-03-04 15:39:23,191 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=297, Unknown=0, NotChecked=0, Total=462 [2025-03-04 15:39:23,191 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. cyclomatic complexity: 2 Second operand has 22 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:23,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:39:23,346 INFO L93 Difference]: Finished difference Result 27 states and 28 transitions. [2025-03-04 15:39:23,347 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 28 transitions. [2025-03-04 15:39:23,347 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2025-03-04 15:39:23,347 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 28 transitions. [2025-03-04 15:39:23,348 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2025-03-04 15:39:23,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2025-03-04 15:39:23,348 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 28 transitions. [2025-03-04 15:39:23,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:39:23,348 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2025-03-04 15:39:23,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 28 transitions. [2025-03-04 15:39:23,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2025-03-04 15:39:23,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.037037037037037) internal successors, (28), 26 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:23,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2025-03-04 15:39:23,349 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2025-03-04 15:39:23,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2025-03-04 15:39:23,350 INFO L432 stractBuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2025-03-04 15:39:23,350 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 15:39:23,350 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 28 transitions. [2025-03-04 15:39:23,351 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2025-03-04 15:39:23,351 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:39:23,351 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:39:23,351 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:39:23,351 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [11, 10, 1, 1, 1, 1] [2025-03-04 15:39:23,351 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-04 15:39:23,351 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-04 15:39:23,352 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:23,352 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 5 times [2025-03-04 15:39:23,352 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:23,352 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281524119] [2025-03-04 15:39:23,352 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:39:23,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:23,356 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:23,359 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:23,359 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:39:23,359 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:23,359 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:39:23,360 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:23,360 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:23,360 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:23,360 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:23,361 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:39:23,362 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:23,362 INFO L85 PathProgramCache]: Analyzing trace with hash 1878717902, now seen corresponding path program 3 times [2025-03-04 15:39:23,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:23,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1104726097] [2025-03-04 15:39:23,362 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:39:23,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:23,369 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 25 statements into 11 equivalence classes. [2025-03-04 15:39:23,388 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) and asserted 25 of 25 statements. [2025-03-04 15:39:23,389 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2025-03-04 15:39:23,389 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:39:24,051 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:24,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:39:24,052 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1104726097] [2025-03-04 15:39:24,052 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1104726097] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:39:24,052 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1675682842] [2025-03-04 15:39:24,052 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:39:24,052 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:39:24,052 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:39:24,054 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:39:24,056 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2025-03-04 15:39:24,094 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 25 statements into 11 equivalence classes. [2025-03-04 15:39:24,151 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) and asserted 25 of 25 statements. [2025-03-04 15:39:24,151 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2025-03-04 15:39:24,151 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:39:24,157 INFO L256 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 24 conjuncts are in the unsatisfiable core [2025-03-04 15:39:24,161 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:39:24,167 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-03-04 15:39:24,177 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:24,199 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:24,217 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:24,232 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:24,248 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:24,263 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:24,278 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:24,297 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:24,314 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:24,332 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:24,353 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:24,353 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:39:24,586 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:24,586 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1675682842] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:39:24,586 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:39:24,589 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 14, 14] total 40 [2025-03-04 15:39:24,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1534736219] [2025-03-04 15:39:24,590 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:39:24,590 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:39:24,590 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:39:24,590 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2025-03-04 15:39:24,591 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=570, Invalid=990, Unknown=0, NotChecked=0, Total=1560 [2025-03-04 15:39:24,591 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. cyclomatic complexity: 2 Second operand has 40 states, 40 states have (on average 1.725) internal successors, (69), 40 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:25,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:39:25,060 INFO L93 Difference]: Finished difference Result 51 states and 52 transitions. [2025-03-04 15:39:25,060 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 52 transitions. [2025-03-04 15:39:25,061 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2025-03-04 15:39:25,064 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 51 states and 52 transitions. [2025-03-04 15:39:25,064 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2025-03-04 15:39:25,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2025-03-04 15:39:25,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 52 transitions. [2025-03-04 15:39:25,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:39:25,065 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2025-03-04 15:39:25,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 52 transitions. [2025-03-04 15:39:25,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2025-03-04 15:39:25,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0196078431372548) internal successors, (52), 50 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:25,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 52 transitions. [2025-03-04 15:39:25,069 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2025-03-04 15:39:25,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2025-03-04 15:39:25,070 INFO L432 stractBuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2025-03-04 15:39:25,070 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 15:39:25,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 52 transitions. [2025-03-04 15:39:25,071 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2025-03-04 15:39:25,071 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:39:25,071 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:39:25,071 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:39:25,071 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [23, 22, 1, 1, 1, 1] [2025-03-04 15:39:25,072 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-04 15:39:25,072 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-04 15:39:25,072 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:25,072 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 6 times [2025-03-04 15:39:25,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:25,072 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1011350651] [2025-03-04 15:39:25,072 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:39:25,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:25,076 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:25,077 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:25,077 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 15:39:25,077 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:25,077 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:39:25,078 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:25,079 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:25,079 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:25,079 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:25,080 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:39:25,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:25,080 INFO L85 PathProgramCache]: Analyzing trace with hash -1594285990, now seen corresponding path program 4 times [2025-03-04 15:39:25,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:25,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162225781] [2025-03-04 15:39:25,081 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:39:25,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:25,092 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 49 statements into 2 equivalence classes. [2025-03-04 15:39:25,118 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 49 of 49 statements. [2025-03-04 15:39:25,119 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:39:25,119 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:39:27,248 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:27,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:39:27,248 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [162225781] [2025-03-04 15:39:27,249 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [162225781] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:39:27,249 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1685446831] [2025-03-04 15:39:27,249 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:39:27,249 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:39:27,249 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:39:27,251 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:39:27,252 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2025-03-04 15:39:27,304 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 49 statements into 2 equivalence classes. [2025-03-04 15:39:27,508 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 49 of 49 statements. [2025-03-04 15:39:27,508 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:39:27,508 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:39:27,510 INFO L256 TraceCheckSpWp]: Trace formula consists of 362 conjuncts, 48 conjuncts are in the unsatisfiable core [2025-03-04 15:39:27,514 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:39:27,516 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-03-04 15:39:27,521 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,539 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,558 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,576 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,596 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,618 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,639 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,658 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,677 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,696 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,717 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,741 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,764 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,790 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,812 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,832 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,859 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,882 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,911 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,935 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,961 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:27,986 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:28,008 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:28,008 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:39:28,756 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:28,756 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1685446831] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:39:28,756 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:39:28,756 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 26, 26] total 94 [2025-03-04 15:39:28,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1347691737] [2025-03-04 15:39:28,756 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:39:28,757 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:39:28,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:39:28,758 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2025-03-04 15:39:28,762 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3036, Invalid=5706, Unknown=0, NotChecked=0, Total=8742 [2025-03-04 15:39:28,763 INFO L87 Difference]: Start difference. First operand 51 states and 52 transitions. cyclomatic complexity: 2 Second operand has 94 states, 94 states have (on average 1.5) internal successors, (141), 94 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:30,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:39:30,092 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions. [2025-03-04 15:39:30,092 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 100 transitions. [2025-03-04 15:39:30,093 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-04 15:39:30,093 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 99 states and 100 transitions. [2025-03-04 15:39:30,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99 [2025-03-04 15:39:30,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99 [2025-03-04 15:39:30,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 100 transitions. [2025-03-04 15:39:30,094 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:39:30,094 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2025-03-04 15:39:30,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 100 transitions. [2025-03-04 15:39:30,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2025-03-04 15:39:30,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.0101010101010102) internal successors, (100), 98 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:30,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions. [2025-03-04 15:39:30,097 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2025-03-04 15:39:30,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2025-03-04 15:39:30,098 INFO L432 stractBuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2025-03-04 15:39:30,098 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-04 15:39:30,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 100 transitions. [2025-03-04 15:39:30,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-04 15:39:30,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:39:30,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:39:30,101 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:39:30,103 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [47, 46, 1, 1, 1, 1] [2025-03-04 15:39:30,103 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-04 15:39:30,103 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-04 15:39:30,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:30,104 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 7 times [2025-03-04 15:39:30,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:30,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [460314340] [2025-03-04 15:39:30,104 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:39:30,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:30,107 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:30,108 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:30,109 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:30,109 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:30,109 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:39:30,109 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:30,111 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:30,111 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:30,111 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:30,112 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:39:30,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:30,113 INFO L85 PathProgramCache]: Analyzing trace with hash -1098528398, now seen corresponding path program 5 times [2025-03-04 15:39:30,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:30,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212433031] [2025-03-04 15:39:30,115 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:39:30,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:30,137 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 97 statements into 47 equivalence classes. [2025-03-04 15:39:30,278 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) and asserted 97 of 97 statements. [2025-03-04 15:39:30,278 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2025-03-04 15:39:30,278 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:39:35,031 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:35,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:39:35,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212433031] [2025-03-04 15:39:35,031 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1212433031] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:39:35,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [17192015] [2025-03-04 15:39:35,031 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:39:35,031 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:39:35,031 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:39:35,033 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:39:35,036 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2025-03-04 15:39:35,102 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 97 statements into 47 equivalence classes. [2025-03-04 15:39:52,454 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) and asserted 97 of 97 statements. [2025-03-04 15:39:52,454 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2025-03-04 15:39:52,454 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:39:52,468 INFO L256 TraceCheckSpWp]: Trace formula consists of 722 conjuncts, 96 conjuncts are in the unsatisfiable core [2025-03-04 15:39:52,479 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:39:52,482 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-03-04 15:39:52,486 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,503 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,521 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,536 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,550 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,571 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,591 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,615 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,633 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,652 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,675 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,703 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,732 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,760 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,781 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,805 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,826 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,848 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,871 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,896 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,919 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,943 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,967 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:52,992 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,017 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,044 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,075 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,105 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,134 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,165 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,196 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,228 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,263 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,291 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,320 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,352 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,382 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,417 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,450 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,480 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,517 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,556 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,599 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,641 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,684 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,729 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-04 15:39:53,762 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:53,762 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:39:55,845 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:39:55,845 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [17192015] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:39:55,845 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:39:55,845 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 50, 50] total 160 [2025-03-04 15:39:55,845 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [875312389] [2025-03-04 15:39:55,845 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:39:55,846 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:39:55,846 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:39:55,848 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 160 interpolants. [2025-03-04 15:39:55,855 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9054, Invalid=16386, Unknown=0, NotChecked=0, Total=25440 [2025-03-04 15:39:55,855 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. cyclomatic complexity: 2 Second operand has 160 states, 160 states have (on average 1.775) internal successors, (284), 160 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:59,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:39:59,256 INFO L93 Difference]: Finished difference Result 195 states and 196 transitions. [2025-03-04 15:39:59,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195 states and 196 transitions. [2025-03-04 15:39:59,257 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193 [2025-03-04 15:39:59,258 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195 states to 195 states and 196 transitions. [2025-03-04 15:39:59,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-03-04 15:39:59,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2025-03-04 15:39:59,259 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 196 transitions. [2025-03-04 15:39:59,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:39:59,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2025-03-04 15:39:59,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 196 transitions. [2025-03-04 15:39:59,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2025-03-04 15:39:59,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.005128205128205) internal successors, (196), 194 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:39:59,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 196 transitions. [2025-03-04 15:39:59,266 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2025-03-04 15:39:59,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 190 states. [2025-03-04 15:39:59,267 INFO L432 stractBuchiCegarLoop]: Abstraction has 195 states and 196 transitions. [2025-03-04 15:39:59,267 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-04 15:39:59,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 196 transitions. [2025-03-04 15:39:59,269 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193 [2025-03-04 15:39:59,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:39:59,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:39:59,270 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:39:59,270 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [95, 94, 1, 1, 1, 1] [2025-03-04 15:39:59,270 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-04 15:39:59,270 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-04 15:39:59,271 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:59,271 INFO L85 PathProgramCache]: Analyzing trace with hash 1472, now seen corresponding path program 8 times [2025-03-04 15:39:59,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:59,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453786685] [2025-03-04 15:39:59,271 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:39:59,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:59,274 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:59,274 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:59,274 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:39:59,275 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:59,275 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:39:59,275 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:39:59,275 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:39:59,275 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:39:59,275 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:39:59,277 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:39:59,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:39:59,277 INFO L85 PathProgramCache]: Analyzing trace with hash -676303966, now seen corresponding path program 6 times [2025-03-04 15:39:59,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:39:59,277 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928206086] [2025-03-04 15:39:59,277 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:39:59,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:39:59,304 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 193 statements into 95 equivalence classes. [2025-03-04 15:39:59,606 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) and asserted 193 of 193 statements. [2025-03-04 15:39:59,607 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2025-03-04 15:39:59,607 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:40:14,548 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:40:14,548 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:40:14,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [928206086] [2025-03-04 15:40:14,548 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [928206086] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:40:14,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [774138103] [2025-03-04 15:40:14,548 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:40:14,548 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:40:14,548 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:40:14,551 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:40:14,552 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2025-03-04 15:40:14,640 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 193 statements into 95 equivalence classes.