./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/bist_cell.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/bist_cell.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 16:19:38,641 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 16:19:38,695 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-04 16:19:38,698 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 16:19:38,698 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 16:19:38,698 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 16:19:38,713 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 16:19:38,714 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 16:19:38,715 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 16:19:38,715 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 16:19:38,715 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 16:19:38,715 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 16:19:38,716 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 16:19:38,716 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 16:19:38,716 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 16:19:38,716 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 16:19:38,717 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 16:19:38,717 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 16:19:38,717 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 16:19:38,717 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 16:19:38,717 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 16:19:38,717 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 16:19:38,717 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-04 16:19:38,717 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 16:19:38,718 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-04 16:19:38,718 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 16:19:38,718 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 16:19:38,718 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 16:19:38,718 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 16:19:38,718 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 16:19:38,718 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-04 16:19:38,718 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 16:19:38,718 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 16:19:38,718 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 16:19:38,718 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 16:19:38,718 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 16:19:38,718 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 16:19:38,718 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 16:19:38,718 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 16:19:38,719 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 16:19:38,719 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 [2025-03-04 16:19:38,936 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 16:19:38,943 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 16:19:38,945 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 16:19:38,946 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 16:19:38,946 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 16:19:38,947 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/bist_cell.cil.c [2025-03-04 16:19:40,108 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6cfcb30ed/c50e11a0ebbd4d078f4548b8b2e89e1f/FLAG28fe3edc8 [2025-03-04 16:19:40,341 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 16:19:40,341 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c [2025-03-04 16:19:40,348 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6cfcb30ed/c50e11a0ebbd4d078f4548b8b2e89e1f/FLAG28fe3edc8 [2025-03-04 16:19:40,367 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6cfcb30ed/c50e11a0ebbd4d078f4548b8b2e89e1f [2025-03-04 16:19:40,369 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 16:19:40,371 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 16:19:40,373 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 16:19:40,374 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 16:19:40,377 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 16:19:40,379 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,381 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1b659a25 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40, skipping insertion in model container [2025-03-04 16:19:40,381 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,402 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 16:19:40,563 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:19:40,572 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 16:19:40,598 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:19:40,614 INFO L204 MainTranslator]: Completed translation [2025-03-04 16:19:40,614 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40 WrapperNode [2025-03-04 16:19:40,614 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 16:19:40,615 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 16:19:40,615 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 16:19:40,615 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 16:19:40,620 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,624 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,643 INFO L138 Inliner]: procedures = 30, calls = 31, calls flagged for inlining = 26, calls inlined = 32, statements flattened = 339 [2025-03-04 16:19:40,643 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 16:19:40,643 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 16:19:40,644 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 16:19:40,644 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 16:19:40,648 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,649 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,650 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,657 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-04 16:19:40,658 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,658 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,665 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,666 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,667 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,667 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,673 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 16:19:40,674 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 16:19:40,674 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 16:19:40,674 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 16:19:40,674 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40" (1/1) ... [2025-03-04 16:19:40,682 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:40,697 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:40,712 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:40,717 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 16:19:40,736 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-04 16:19:40,736 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-04 16:19:40,737 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 16:19:40,737 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 16:19:40,793 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 16:19:40,794 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 16:19:41,101 INFO L? ?]: Removed 36 outVars from TransFormulas that were not future-live. [2025-03-04 16:19:41,102 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 16:19:41,111 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 16:19:41,112 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-04 16:19:41,112 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:19:41 BoogieIcfgContainer [2025-03-04 16:19:41,113 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 16:19:41,113 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 16:19:41,113 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 16:19:41,117 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 16:19:41,117 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:19:41,117 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 04:19:40" (1/3) ... [2025-03-04 16:19:41,118 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@410183e1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:19:41, skipping insertion in model container [2025-03-04 16:19:41,118 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:19:41,118 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:40" (2/3) ... [2025-03-04 16:19:41,118 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@410183e1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:19:41, skipping insertion in model container [2025-03-04 16:19:41,118 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:19:41,118 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:19:41" (3/3) ... [2025-03-04 16:19:41,119 INFO L363 chiAutomizerObserver]: Analyzing ICFG bist_cell.cil.c [2025-03-04 16:19:41,153 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 16:19:41,154 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 16:19:41,154 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 16:19:41,154 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 16:19:41,154 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 16:19:41,155 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 16:19:41,155 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 16:19:41,155 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 16:19:41,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 126 states, 125 states have (on average 1.568) internal successors, (196), 125 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:41,174 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:41,175 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:41,175 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:41,182 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:41,182 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:41,182 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 16:19:41,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 126 states, 125 states have (on average 1.568) internal successors, (196), 125 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:41,188 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:41,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:41,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:41,192 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:41,192 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:41,197 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:41,197 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-04 16:19:41,201 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:41,201 INFO L85 PathProgramCache]: Analyzing trace with hash -2014143597, now seen corresponding path program 1 times [2025-03-04 16:19:41,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:41,209 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [688857071] [2025-03-04 16:19:41,209 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:41,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:41,259 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:19:41,277 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:19:41,278 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:41,278 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:41,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:41,371 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:41,371 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [688857071] [2025-03-04 16:19:41,371 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [688857071] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:41,371 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:41,372 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:41,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121526129] [2025-03-04 16:19:41,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:41,376 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:41,377 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:41,378 INFO L85 PathProgramCache]: Analyzing trace with hash -1308095898, now seen corresponding path program 1 times [2025-03-04 16:19:41,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:41,378 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327425587] [2025-03-04 16:19:41,378 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:41,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:41,388 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-04 16:19:41,389 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-04 16:19:41,389 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:41,389 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:41,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:41,400 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:41,400 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1327425587] [2025-03-04 16:19:41,400 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1327425587] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:41,400 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:41,400 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:19:41,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1391279830] [2025-03-04 16:19:41,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:41,401 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:41,402 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:41,420 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:41,420 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:41,422 INFO L87 Difference]: Start difference. First operand has 126 states, 125 states have (on average 1.568) internal successors, (196), 125 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:41,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:41,461 INFO L93 Difference]: Finished difference Result 124 states and 190 transitions. [2025-03-04 16:19:41,463 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 190 transitions. [2025-03-04 16:19:41,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:41,474 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 117 states and 183 transitions. [2025-03-04 16:19:41,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-03-04 16:19:41,477 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-03-04 16:19:41,478 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 183 transitions. [2025-03-04 16:19:41,479 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:41,479 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2025-03-04 16:19:41,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 183 transitions. [2025-03-04 16:19:41,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-03-04 16:19:41,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.564102564102564) internal successors, (183), 116 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:41,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 183 transitions. [2025-03-04 16:19:41,509 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2025-03-04 16:19:41,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:41,513 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 183 transitions. [2025-03-04 16:19:41,513 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 16:19:41,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 183 transitions. [2025-03-04 16:19:41,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:41,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:41,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:41,519 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:41,519 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:41,520 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume !(~b0_val~0 != ~b0_val_t~0);" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:41,522 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-04 16:19:41,522 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:41,523 INFO L85 PathProgramCache]: Analyzing trace with hash 611581221, now seen corresponding path program 1 times [2025-03-04 16:19:41,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:41,523 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351549073] [2025-03-04 16:19:41,523 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:41,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:41,530 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-04 16:19:41,539 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 16:19:41,541 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:41,541 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:41,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:41,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:41,641 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1351549073] [2025-03-04 16:19:41,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1351549073] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:41,641 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:41,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:41,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515042391] [2025-03-04 16:19:41,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:41,641 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:41,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:41,642 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 1 times [2025-03-04 16:19:41,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:41,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313655901] [2025-03-04 16:19:41,642 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:41,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:41,648 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:19:41,658 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:19:41,658 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:41,658 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:41,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:41,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:41,731 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [313655901] [2025-03-04 16:19:41,731 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [313655901] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:41,731 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:41,731 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:41,731 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1145194046] [2025-03-04 16:19:41,732 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:41,732 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:41,732 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:41,732 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:41,732 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:41,732 INFO L87 Difference]: Start difference. First operand 117 states and 183 transitions. cyclomatic complexity: 67 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:41,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:41,751 INFO L93 Difference]: Finished difference Result 117 states and 182 transitions. [2025-03-04 16:19:41,751 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 182 transitions. [2025-03-04 16:19:41,753 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:41,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 182 transitions. [2025-03-04 16:19:41,754 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-03-04 16:19:41,755 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-03-04 16:19:41,755 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 182 transitions. [2025-03-04 16:19:41,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:41,755 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2025-03-04 16:19:41,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 182 transitions. [2025-03-04 16:19:41,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-03-04 16:19:41,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5555555555555556) internal successors, (182), 116 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:41,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 182 transitions. [2025-03-04 16:19:41,759 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2025-03-04 16:19:41,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:41,761 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 182 transitions. [2025-03-04 16:19:41,761 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 16:19:41,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 182 transitions. [2025-03-04 16:19:41,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:41,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:41,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:41,764 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:41,764 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:41,765 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:41,765 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-04 16:19:41,765 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:41,766 INFO L85 PathProgramCache]: Analyzing trace with hash -350032796, now seen corresponding path program 1 times [2025-03-04 16:19:41,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:41,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [460105900] [2025-03-04 16:19:41,766 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:41,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:41,777 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-04 16:19:41,780 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 16:19:41,783 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:41,783 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:41,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:41,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:41,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [460105900] [2025-03-04 16:19:41,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [460105900] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:41,819 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:41,819 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:41,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841865668] [2025-03-04 16:19:41,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:41,820 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:41,820 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:41,820 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 2 times [2025-03-04 16:19:41,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:41,820 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1025593590] [2025-03-04 16:19:41,820 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:19:41,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:41,825 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:19:41,828 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:19:41,828 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:41,828 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:41,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:41,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:41,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1025593590] [2025-03-04 16:19:41,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1025593590] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:41,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:41,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:41,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564967473] [2025-03-04 16:19:41,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:41,885 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:41,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:41,886 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:41,886 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:41,887 INFO L87 Difference]: Start difference. First operand 117 states and 182 transitions. cyclomatic complexity: 66 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:41,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:41,902 INFO L93 Difference]: Finished difference Result 117 states and 181 transitions. [2025-03-04 16:19:41,902 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 181 transitions. [2025-03-04 16:19:41,903 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:41,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 181 transitions. [2025-03-04 16:19:41,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-03-04 16:19:41,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-03-04 16:19:41,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 181 transitions. [2025-03-04 16:19:41,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:41,904 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2025-03-04 16:19:41,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 181 transitions. [2025-03-04 16:19:41,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-03-04 16:19:41,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.547008547008547) internal successors, (181), 116 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:41,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 181 transitions. [2025-03-04 16:19:41,911 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2025-03-04 16:19:41,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:41,913 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 181 transitions. [2025-03-04 16:19:41,914 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 16:19:41,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 181 transitions. [2025-03-04 16:19:41,914 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:41,915 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:41,915 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:41,916 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:41,916 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:41,916 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume !(~b1_val~0 != ~b1_val_t~0);" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:41,917 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-04 16:19:41,917 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:41,917 INFO L85 PathProgramCache]: Analyzing trace with hash -357443661, now seen corresponding path program 1 times [2025-03-04 16:19:41,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:41,917 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579695454] [2025-03-04 16:19:41,918 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:41,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:41,924 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-04 16:19:41,929 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-04 16:19:41,929 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:41,929 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:41,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:41,989 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:41,989 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1579695454] [2025-03-04 16:19:41,989 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1579695454] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:41,989 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:41,989 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:19:41,989 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901717692] [2025-03-04 16:19:41,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:41,989 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:41,990 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:41,990 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 3 times [2025-03-04 16:19:41,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:41,990 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738132607] [2025-03-04 16:19:41,990 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:19:41,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:41,994 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:19:41,997 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:19:41,997 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:19:41,997 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:42,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:42,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:42,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738132607] [2025-03-04 16:19:42,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [738132607] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:42,029 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:42,029 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:42,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1686575980] [2025-03-04 16:19:42,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:42,029 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:42,032 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:42,032 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:19:42,032 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:19:42,032 INFO L87 Difference]: Start difference. First operand 117 states and 181 transitions. cyclomatic complexity: 65 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 4 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:42,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:42,070 INFO L93 Difference]: Finished difference Result 117 states and 180 transitions. [2025-03-04 16:19:42,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 180 transitions. [2025-03-04 16:19:42,071 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:42,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 180 transitions. [2025-03-04 16:19:42,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-03-04 16:19:42,072 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-03-04 16:19:42,072 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 180 transitions. [2025-03-04 16:19:42,073 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:42,073 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2025-03-04 16:19:42,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 180 transitions. [2025-03-04 16:19:42,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-03-04 16:19:42,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5384615384615385) internal successors, (180), 116 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:42,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 180 transitions. [2025-03-04 16:19:42,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2025-03-04 16:19:42,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:19:42,077 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 180 transitions. [2025-03-04 16:19:42,077 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 16:19:42,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 180 transitions. [2025-03-04 16:19:42,078 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:42,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:42,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:42,079 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:42,079 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:42,079 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:42,082 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-04 16:19:42,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:42,083 INFO L85 PathProgramCache]: Analyzing trace with hash -388463468, now seen corresponding path program 1 times [2025-03-04 16:19:42,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:42,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212325686] [2025-03-04 16:19:42,083 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:42,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:42,087 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-04 16:19:42,089 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-04 16:19:42,089 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:42,089 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:42,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:42,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:42,118 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212325686] [2025-03-04 16:19:42,118 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1212325686] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:42,118 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:42,118 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:42,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [803472512] [2025-03-04 16:19:42,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:42,119 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:42,119 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:42,119 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 4 times [2025-03-04 16:19:42,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:42,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1891958491] [2025-03-04 16:19:42,120 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:19:42,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:42,126 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 39 statements into 2 equivalence classes. [2025-03-04 16:19:42,129 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:19:42,130 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-03-04 16:19:42,130 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:42,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:42,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:42,167 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1891958491] [2025-03-04 16:19:42,167 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1891958491] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:42,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:42,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:42,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1838307181] [2025-03-04 16:19:42,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:42,168 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:42,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:42,168 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:42,168 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:42,169 INFO L87 Difference]: Start difference. First operand 117 states and 180 transitions. cyclomatic complexity: 64 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:42,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:42,181 INFO L93 Difference]: Finished difference Result 117 states and 179 transitions. [2025-03-04 16:19:42,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 179 transitions. [2025-03-04 16:19:42,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:42,184 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 179 transitions. [2025-03-04 16:19:42,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-03-04 16:19:42,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-03-04 16:19:42,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 179 transitions. [2025-03-04 16:19:42,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:42,185 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2025-03-04 16:19:42,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 179 transitions. [2025-03-04 16:19:42,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-03-04 16:19:42,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5299145299145298) internal successors, (179), 116 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:42,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 179 transitions. [2025-03-04 16:19:42,188 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2025-03-04 16:19:42,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:42,189 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 179 transitions. [2025-03-04 16:19:42,189 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 16:19:42,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 179 transitions. [2025-03-04 16:19:42,190 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:42,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:42,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:42,191 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:42,191 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:42,191 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume !(~d0_val~0 != ~d0_val_t~0);" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:42,191 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-04 16:19:42,191 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:42,191 INFO L85 PathProgramCache]: Analyzing trace with hash 1243696292, now seen corresponding path program 1 times [2025-03-04 16:19:42,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:42,192 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344318064] [2025-03-04 16:19:42,192 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:42,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:42,215 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-03-04 16:19:42,216 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-03-04 16:19:42,216 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:42,216 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:42,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:42,266 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:42,266 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1344318064] [2025-03-04 16:19:42,266 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1344318064] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:42,266 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:42,266 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:19:42,266 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [948399650] [2025-03-04 16:19:42,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:42,267 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:42,267 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:42,267 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 5 times [2025-03-04 16:19:42,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:42,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161846147] [2025-03-04 16:19:42,267 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 16:19:42,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:42,272 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:19:42,274 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:19:42,275 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:42,275 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:42,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:42,300 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:42,300 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [161846147] [2025-03-04 16:19:42,300 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [161846147] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:42,300 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:42,300 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:42,300 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [24875804] [2025-03-04 16:19:42,300 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:42,300 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:42,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:42,301 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:19:42,301 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:19:42,301 INFO L87 Difference]: Start difference. First operand 117 states and 179 transitions. cyclomatic complexity: 63 Second operand has 4 states, 4 states have (on average 9.25) internal successors, (37), 4 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:42,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:42,331 INFO L93 Difference]: Finished difference Result 117 states and 178 transitions. [2025-03-04 16:19:42,331 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 178 transitions. [2025-03-04 16:19:42,332 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:42,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 178 transitions. [2025-03-04 16:19:42,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-03-04 16:19:42,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-03-04 16:19:42,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 178 transitions. [2025-03-04 16:19:42,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:42,333 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2025-03-04 16:19:42,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 178 transitions. [2025-03-04 16:19:42,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-03-04 16:19:42,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5213675213675213) internal successors, (178), 116 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:42,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 178 transitions. [2025-03-04 16:19:42,338 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2025-03-04 16:19:42,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:19:42,343 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 178 transitions. [2025-03-04 16:19:42,344 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-04 16:19:42,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 178 transitions. [2025-03-04 16:19:42,345 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:42,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:42,345 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:42,346 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:42,347 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:42,347 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:42,347 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-04 16:19:42,347 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:42,347 INFO L85 PathProgramCache]: Analyzing trace with hash -974061661, now seen corresponding path program 1 times [2025-03-04 16:19:42,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:42,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024052441] [2025-03-04 16:19:42,349 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:42,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:42,353 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-03-04 16:19:42,356 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-03-04 16:19:42,358 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:42,358 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:42,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:42,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:42,374 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024052441] [2025-03-04 16:19:42,374 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2024052441] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:42,374 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:42,374 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:42,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1069727469] [2025-03-04 16:19:42,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:42,375 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:42,375 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:42,375 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 6 times [2025-03-04 16:19:42,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:42,375 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665512095] [2025-03-04 16:19:42,375 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 16:19:42,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:42,379 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:19:42,384 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:19:42,384 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 16:19:42,384 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:42,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:42,411 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:42,411 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665512095] [2025-03-04 16:19:42,411 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665512095] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:42,412 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:42,412 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:42,412 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657817111] [2025-03-04 16:19:42,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:42,412 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:42,412 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:42,412 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:42,412 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:42,413 INFO L87 Difference]: Start difference. First operand 117 states and 178 transitions. cyclomatic complexity: 62 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:42,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:42,421 INFO L93 Difference]: Finished difference Result 117 states and 177 transitions. [2025-03-04 16:19:42,421 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 177 transitions. [2025-03-04 16:19:42,422 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:42,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 177 transitions. [2025-03-04 16:19:42,422 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-03-04 16:19:42,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-03-04 16:19:42,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 177 transitions. [2025-03-04 16:19:42,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:42,423 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2025-03-04 16:19:42,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 177 transitions. [2025-03-04 16:19:42,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-03-04 16:19:42,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5128205128205128) internal successors, (177), 116 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:42,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 177 transitions. [2025-03-04 16:19:42,425 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2025-03-04 16:19:42,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:42,426 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 177 transitions. [2025-03-04 16:19:42,426 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-04 16:19:42,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 177 transitions. [2025-03-04 16:19:42,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-03-04 16:19:42,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:42,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:42,427 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:42,427 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:42,428 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume !(~d1_val~0 != ~d1_val_t~0);" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:42,428 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-04 16:19:42,428 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:42,428 INFO L85 PathProgramCache]: Analyzing trace with hash -795926540, now seen corresponding path program 1 times [2025-03-04 16:19:42,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:42,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280549416] [2025-03-04 16:19:42,428 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:42,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:42,432 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:19:42,434 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:19:42,435 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:42,435 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:42,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:42,477 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:42,477 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280549416] [2025-03-04 16:19:42,477 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280549416] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:42,477 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:42,477 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:19:42,477 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [489557207] [2025-03-04 16:19:42,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:42,478 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:42,478 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:42,478 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 7 times [2025-03-04 16:19:42,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:42,478 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2146948132] [2025-03-04 16:19:42,478 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 16:19:42,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:42,485 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:19:42,490 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:19:42,490 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:42,490 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:42,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:42,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:42,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2146948132] [2025-03-04 16:19:42,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2146948132] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:42,521 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:42,521 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:42,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [328069370] [2025-03-04 16:19:42,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:42,521 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:42,521 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:42,521 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-04 16:19:42,521 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-04 16:19:42,522 INFO L87 Difference]: Start difference. First operand 117 states and 177 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:42,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:42,546 INFO L93 Difference]: Finished difference Result 122 states and 182 transitions. [2025-03-04 16:19:42,546 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122 states and 182 transitions. [2025-03-04 16:19:42,548 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 76 [2025-03-04 16:19:42,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122 states to 122 states and 182 transitions. [2025-03-04 16:19:42,548 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122 [2025-03-04 16:19:42,548 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122 [2025-03-04 16:19:42,549 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122 states and 182 transitions. [2025-03-04 16:19:42,549 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:42,549 INFO L218 hiAutomatonCegarLoop]: Abstraction has 122 states and 182 transitions. [2025-03-04 16:19:42,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states and 182 transitions. [2025-03-04 16:19:42,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 120. [2025-03-04 16:19:42,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120 states, 120 states have (on average 1.5) internal successors, (180), 119 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:42,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 180 transitions. [2025-03-04 16:19:42,553 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120 states and 180 transitions. [2025-03-04 16:19:42,553 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:19:42,554 INFO L432 stractBuchiCegarLoop]: Abstraction has 120 states and 180 transitions. [2025-03-04 16:19:42,554 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-04 16:19:42,554 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120 states and 180 transitions. [2025-03-04 16:19:42,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 74 [2025-03-04 16:19:42,558 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:42,558 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:42,559 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:42,559 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:42,559 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume !(~d1_val~0 != ~d1_val_t~0);" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:42,559 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-03-04 16:19:42,559 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:42,559 INFO L85 PathProgramCache]: Analyzing trace with hash -795926540, now seen corresponding path program 2 times [2025-03-04 16:19:42,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:42,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564835831] [2025-03-04 16:19:42,560 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:19:42,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:42,563 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:19:42,565 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:19:42,565 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:42,565 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:42,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:42,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:42,614 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1564835831] [2025-03-04 16:19:42,614 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1564835831] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:42,614 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:42,614 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:19:42,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [683574168] [2025-03-04 16:19:42,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:42,615 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:42,615 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:42,615 INFO L85 PathProgramCache]: Analyzing trace with hash -721208601, now seen corresponding path program 1 times [2025-03-04 16:19:42,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:42,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1480268988] [2025-03-04 16:19:42,616 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:42,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:42,621 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:19:42,624 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:19:42,624 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:42,624 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:42,624 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:42,628 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:19:42,631 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:19:42,632 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:42,632 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:42,648 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:42,935 INFO L204 LassoAnalysis]: Preferences: [2025-03-04 16:19:42,936 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-04 16:19:42,936 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-04 16:19:42,936 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-04 16:19:42,936 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2025-03-04 16:19:42,936 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:42,936 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-04 16:19:42,936 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-04 16:19:42,936 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2025-03-04 16:19:42,936 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-04 16:19:42,937 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-04 16:19:42,948 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,953 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,958 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,962 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,966 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,968 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,970 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,971 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,973 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,977 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,981 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,985 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,987 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,989 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,990 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,993 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,996 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:42,998 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,000 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,002 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,004 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,005 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,007 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,009 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,010 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,012 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,163 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-04 16:19:43,164 INFO L365 LassoAnalysis]: Checking for nontermination... [2025-03-04 16:19:43,165 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:43,165 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:43,167 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:43,169 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-03-04 16:19:43,170 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-03-04 16:19:43,170 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-04 16:19:43,184 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-03-04 16:19:43,184 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-03-04 16:19:43,190 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2025-03-04 16:19:43,191 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:43,191 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:43,193 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:43,193 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-03-04 16:19:43,194 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-03-04 16:19:43,194 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-04 16:19:43,213 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2025-03-04 16:19:43,213 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:43,213 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:43,215 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:43,215 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-03-04 16:19:43,217 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2025-03-04 16:19:43,217 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-04 16:19:43,232 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2025-03-04 16:19:43,237 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2025-03-04 16:19:43,237 INFO L204 LassoAnalysis]: Preferences: [2025-03-04 16:19:43,237 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-04 16:19:43,237 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-04 16:19:43,237 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-04 16:19:43,237 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-03-04 16:19:43,237 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:43,237 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-04 16:19:43,237 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-04 16:19:43,237 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2025-03-04 16:19:43,237 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-04 16:19:43,238 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-04 16:19:43,239 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,242 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,244 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,246 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,250 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,254 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,258 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,260 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,264 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,268 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,272 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,273 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,276 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,277 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,280 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,283 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,284 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,286 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,288 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,290 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,292 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,294 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,296 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,297 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,301 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,303 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,305 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:43,459 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-04 16:19:43,462 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-03-04 16:19:43,463 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:43,464 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:43,465 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:43,467 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-03-04 16:19:43,468 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 16:19:43,480 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 16:19:43,480 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 16:19:43,481 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 16:19:43,481 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 16:19:43,481 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 16:19:43,486 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 16:19:43,486 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 16:19:43,488 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 16:19:43,496 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2025-03-04 16:19:43,496 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:43,496 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:43,497 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:43,498 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-03-04 16:19:43,501 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 16:19:43,511 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 16:19:43,511 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 16:19:43,511 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 16:19:43,511 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 16:19:43,511 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 16:19:43,512 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 16:19:43,513 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 16:19:43,516 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 16:19:43,522 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2025-03-04 16:19:43,522 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:43,523 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:43,524 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:43,525 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-03-04 16:19:43,527 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 16:19:43,537 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 16:19:43,537 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 16:19:43,537 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 16:19:43,537 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 16:19:43,537 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 16:19:43,537 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 16:19:43,537 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 16:19:43,539 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 16:19:43,544 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2025-03-04 16:19:43,544 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:43,544 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:43,546 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:43,547 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-03-04 16:19:43,548 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 16:19:43,559 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 16:19:43,559 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 16:19:43,559 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 16:19:43,559 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 16:19:43,559 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 16:19:43,560 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 16:19:43,560 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 16:19:43,562 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-03-04 16:19:43,566 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2025-03-04 16:19:43,568 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2025-03-04 16:19:43,569 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:43,569 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:43,572 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:43,573 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-03-04 16:19:43,574 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-03-04 16:19:43,574 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2025-03-04 16:19:43,575 INFO L474 LassoAnalysis]: Proved termination. [2025-03-04 16:19:43,575 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~d1_ev~0) = -1*~d1_ev~0 + 1 Supporting invariants [] [2025-03-04 16:19:43,581 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2025-03-04 16:19:43,583 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-03-04 16:19:43,609 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:43,622 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:19:43,639 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:19:43,639 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:43,639 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:43,641 INFO L256 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-03-04 16:19:43,642 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 16:19:43,695 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:19:43,703 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:19:43,703 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:43,703 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:43,704 INFO L256 TraceCheckSpWp]: Trace formula consists of 96 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-03-04 16:19:43,705 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 16:19:43,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:43,789 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2025-03-04 16:19:43,790 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:43,858 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61. Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 274 states and 420 transitions. Complement of second has 5 states. [2025-03-04 16:19:43,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-03-04 16:19:43,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:43,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2025-03-04 16:19:43,865 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 40 letters. Loop has 39 letters. [2025-03-04 16:19:43,867 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 16:19:43,867 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 79 letters. Loop has 39 letters. [2025-03-04 16:19:43,867 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 16:19:43,867 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 40 letters. Loop has 78 letters. [2025-03-04 16:19:43,868 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 16:19:43,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 274 states and 420 transitions. [2025-03-04 16:19:43,871 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2025-03-04 16:19:43,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 274 states to 274 states and 420 transitions. [2025-03-04 16:19:43,872 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-03-04 16:19:43,873 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2025-03-04 16:19:43,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 274 states and 420 transitions. [2025-03-04 16:19:43,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:43,873 INFO L218 hiAutomatonCegarLoop]: Abstraction has 274 states and 420 transitions. [2025-03-04 16:19:43,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states and 420 transitions. [2025-03-04 16:19:43,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 271. [2025-03-04 16:19:43,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5387453874538746) internal successors, (417), 270 states have internal predecessors, (417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:43,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 417 transitions. [2025-03-04 16:19:43,877 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 417 transitions. [2025-03-04 16:19:43,878 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:43,878 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:19:43,878 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:19:43,878 INFO L87 Difference]: Start difference. First operand 271 states and 417 transitions. Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:43,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:43,901 INFO L93 Difference]: Finished difference Result 271 states and 416 transitions. [2025-03-04 16:19:43,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 416 transitions. [2025-03-04 16:19:43,903 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2025-03-04 16:19:43,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 271 states and 416 transitions. [2025-03-04 16:19:43,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-03-04 16:19:43,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2025-03-04 16:19:43,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 271 states and 416 transitions. [2025-03-04 16:19:43,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:43,904 INFO L218 hiAutomatonCegarLoop]: Abstraction has 271 states and 416 transitions. [2025-03-04 16:19:43,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states and 416 transitions. [2025-03-04 16:19:43,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 271. [2025-03-04 16:19:43,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5350553505535056) internal successors, (416), 270 states have internal predecessors, (416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:43,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 416 transitions. [2025-03-04 16:19:43,908 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 416 transitions. [2025-03-04 16:19:43,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:19:43,909 INFO L432 stractBuchiCegarLoop]: Abstraction has 271 states and 416 transitions. [2025-03-04 16:19:43,909 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-04 16:19:43,909 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 271 states and 416 transitions. [2025-03-04 16:19:43,910 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2025-03-04 16:19:43,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:43,910 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:43,911 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:43,911 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:43,911 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" [2025-03-04 16:19:43,911 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume !(0 == ~d1_ev~0);" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume !(1 == ~d1_ev~0);" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" "assume true;" [2025-03-04 16:19:43,912 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:43,912 INFO L85 PathProgramCache]: Analyzing trace with hash -1121676761, now seen corresponding path program 1 times [2025-03-04 16:19:43,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:43,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241314404] [2025-03-04 16:19:43,912 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:43,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:43,916 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:19:43,918 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:19:43,918 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:43,918 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:43,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:43,939 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:43,939 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241314404] [2025-03-04 16:19:43,939 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241314404] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:43,939 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:43,939 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:43,939 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [658077831] [2025-03-04 16:19:43,939 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:43,939 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:43,940 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:43,940 INFO L85 PathProgramCache]: Analyzing trace with hash -1693610513, now seen corresponding path program 1 times [2025-03-04 16:19:43,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:43,940 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767821064] [2025-03-04 16:19:43,940 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:43,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:43,944 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:19:43,947 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:19:43,947 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:43,947 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:43,947 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:43,949 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:19:43,952 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:19:43,952 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:43,952 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:43,955 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:44,038 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2025-03-04 16:19:44,187 INFO L204 LassoAnalysis]: Preferences: [2025-03-04 16:19:44,188 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-04 16:19:44,188 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-04 16:19:44,188 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-04 16:19:44,188 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2025-03-04 16:19:44,188 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:44,188 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-04 16:19:44,188 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-04 16:19:44,188 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration10_Loop [2025-03-04 16:19:44,188 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-04 16:19:44,188 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-04 16:19:44,189 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,194 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,195 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,199 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,200 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,202 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,204 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,206 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,208 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,210 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,212 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,214 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,215 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,217 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,218 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,219 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,220 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,222 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,228 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,230 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,231 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,232 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,236 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,238 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,242 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,244 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,245 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,378 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-04 16:19:44,378 INFO L365 LassoAnalysis]: Checking for nontermination... [2025-03-04 16:19:44,378 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:44,379 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:44,382 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:44,384 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2025-03-04 16:19:44,384 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-03-04 16:19:44,384 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-04 16:19:44,400 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2025-03-04 16:19:44,400 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:44,400 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:44,416 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:44,417 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2025-03-04 16:19:44,418 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2025-03-04 16:19:44,418 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-04 16:19:44,429 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2025-03-04 16:19:44,435 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2025-03-04 16:19:44,435 INFO L204 LassoAnalysis]: Preferences: [2025-03-04 16:19:44,435 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-04 16:19:44,435 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-04 16:19:44,435 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-04 16:19:44,435 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-03-04 16:19:44,435 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:44,435 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-04 16:19:44,435 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-04 16:19:44,435 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration10_Loop [2025-03-04 16:19:44,435 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-04 16:19:44,435 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-04 16:19:44,436 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,441 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,444 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,446 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,449 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,452 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,454 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,460 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,462 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,464 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,465 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,466 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,468 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,469 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,471 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,472 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,474 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,475 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,479 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,480 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,482 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,483 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,486 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,488 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,490 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,491 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,493 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:19:44,631 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-04 16:19:44,631 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-03-04 16:19:44,631 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:44,631 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:44,636 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:44,638 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2025-03-04 16:19:44,639 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 16:19:44,649 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 16:19:44,649 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 16:19:44,649 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 16:19:44,649 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 16:19:44,649 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 16:19:44,650 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 16:19:44,650 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 16:19:44,651 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 16:19:44,658 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2025-03-04 16:19:44,658 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:44,658 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:44,659 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:44,661 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2025-03-04 16:19:44,663 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 16:19:44,673 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 16:19:44,673 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 16:19:44,673 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 16:19:44,673 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 16:19:44,673 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 16:19:44,675 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 16:19:44,675 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 16:19:44,676 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-03-04 16:19:44,678 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2025-03-04 16:19:44,678 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2025-03-04 16:19:44,678 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:44,678 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:44,680 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:44,682 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2025-03-04 16:19:44,682 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-03-04 16:19:44,683 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2025-03-04 16:19:44,683 INFO L474 LassoAnalysis]: Proved termination. [2025-03-04 16:19:44,683 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~d0_ev~0) = -1*~d0_ev~0 + 1 Supporting invariants [] [2025-03-04 16:19:44,688 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2025-03-04 16:19:44,688 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-03-04 16:19:44,700 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:44,710 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:19:44,722 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:19:44,722 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:44,722 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:44,724 INFO L256 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-03-04 16:19:44,724 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 16:19:44,766 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2025-03-04 16:19:44,776 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:19:44,785 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:19:44,786 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:44,786 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:44,786 INFO L256 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-03-04 16:19:44,787 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 16:19:44,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:44,863 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2025-03-04 16:19:44,863 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 271 states and 416 transitions. cyclomatic complexity: 148 Second operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:44,898 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 271 states and 416 transitions. cyclomatic complexity: 148. Second operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 734 states and 1142 transitions. Complement of second has 5 states. [2025-03-04 16:19:44,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-03-04 16:19:44,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:44,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2025-03-04 16:19:44,899 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 39 letters. [2025-03-04 16:19:44,900 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 16:19:44,900 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 80 letters. Loop has 39 letters. [2025-03-04 16:19:44,900 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 16:19:44,900 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 78 letters. [2025-03-04 16:19:44,901 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 16:19:44,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 734 states and 1142 transitions. [2025-03-04 16:19:44,905 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 296 [2025-03-04 16:19:44,908 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 734 states to 734 states and 1142 transitions. [2025-03-04 16:19:44,908 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 346 [2025-03-04 16:19:44,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 351 [2025-03-04 16:19:44,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 734 states and 1142 transitions. [2025-03-04 16:19:44,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:44,909 INFO L218 hiAutomatonCegarLoop]: Abstraction has 734 states and 1142 transitions. [2025-03-04 16:19:44,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 734 states and 1142 transitions. [2025-03-04 16:19:44,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 734 to 729. [2025-03-04 16:19:44,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 729 states, 729 states have (on average 1.5541838134430728) internal successors, (1133), 728 states have internal predecessors, (1133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:44,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 729 states to 729 states and 1133 transitions. [2025-03-04 16:19:44,931 INFO L240 hiAutomatonCegarLoop]: Abstraction has 729 states and 1133 transitions. [2025-03-04 16:19:44,932 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:44,932 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:44,932 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:44,932 INFO L87 Difference]: Start difference. First operand 729 states and 1133 transitions. Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:44,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:44,956 INFO L93 Difference]: Finished difference Result 909 states and 1378 transitions. [2025-03-04 16:19:44,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 909 states and 1378 transitions. [2025-03-04 16:19:44,961 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 376 [2025-03-04 16:19:44,965 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 909 states to 909 states and 1378 transitions. [2025-03-04 16:19:44,965 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 426 [2025-03-04 16:19:44,966 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 426 [2025-03-04 16:19:44,966 INFO L73 IsDeterministic]: Start isDeterministic. Operand 909 states and 1378 transitions. [2025-03-04 16:19:44,966 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:44,966 INFO L218 hiAutomatonCegarLoop]: Abstraction has 909 states and 1378 transitions. [2025-03-04 16:19:44,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 909 states and 1378 transitions. [2025-03-04 16:19:44,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 909 to 909. [2025-03-04 16:19:44,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 909 states, 909 states have (on average 1.515951595159516) internal successors, (1378), 908 states have internal predecessors, (1378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:44,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 909 states to 909 states and 1378 transitions. [2025-03-04 16:19:44,981 INFO L240 hiAutomatonCegarLoop]: Abstraction has 909 states and 1378 transitions. [2025-03-04 16:19:44,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:44,981 INFO L432 stractBuchiCegarLoop]: Abstraction has 909 states and 1378 transitions. [2025-03-04 16:19:44,982 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-04 16:19:44,982 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 909 states and 1378 transitions. [2025-03-04 16:19:44,985 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 376 [2025-03-04 16:19:44,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:44,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:44,986 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:44,986 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:44,986 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-04 16:19:44,986 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume !(0 == ~comp_m1_st~0);" [2025-03-04 16:19:44,986 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:44,987 INFO L85 PathProgramCache]: Analyzing trace with hash 432230803, now seen corresponding path program 1 times [2025-03-04 16:19:44,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:44,987 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1480983431] [2025-03-04 16:19:44,987 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:44,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:44,991 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:44,993 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:44,993 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:44,993 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:45,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:45,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:45,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1480983431] [2025-03-04 16:19:45,008 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1480983431] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:45,008 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:45,008 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:45,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [584529820] [2025-03-04 16:19:45,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:45,009 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:45,009 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,009 INFO L85 PathProgramCache]: Analyzing trace with hash 292527795, now seen corresponding path program 1 times [2025-03-04 16:19:45,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,009 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [87561044] [2025-03-04 16:19:45,009 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:45,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,011 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-03-04 16:19:45,013 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-03-04 16:19:45,013 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,013 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:45,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:45,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:45,043 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [87561044] [2025-03-04 16:19:45,043 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [87561044] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:45,043 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:45,043 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:45,043 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1109181040] [2025-03-04 16:19:45,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:45,043 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:45,043 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:45,044 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-04 16:19:45,044 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-04 16:19:45,044 INFO L87 Difference]: Start difference. First operand 909 states and 1378 transitions. cyclomatic complexity: 478 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:45,083 INFO L93 Difference]: Finished difference Result 927 states and 1387 transitions. [2025-03-04 16:19:45,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 927 states and 1387 transitions. [2025-03-04 16:19:45,087 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 384 [2025-03-04 16:19:45,092 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 927 states to 927 states and 1387 transitions. [2025-03-04 16:19:45,092 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 434 [2025-03-04 16:19:45,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 434 [2025-03-04 16:19:45,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 927 states and 1387 transitions. [2025-03-04 16:19:45,094 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:45,094 INFO L218 hiAutomatonCegarLoop]: Abstraction has 927 states and 1387 transitions. [2025-03-04 16:19:45,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 927 states and 1387 transitions. [2025-03-04 16:19:45,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 927 to 909. [2025-03-04 16:19:45,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 909 states, 909 states have (on average 1.506050605060506) internal successors, (1369), 908 states have internal predecessors, (1369), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 909 states to 909 states and 1369 transitions. [2025-03-04 16:19:45,107 INFO L240 hiAutomatonCegarLoop]: Abstraction has 909 states and 1369 transitions. [2025-03-04 16:19:45,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:19:45,108 INFO L432 stractBuchiCegarLoop]: Abstraction has 909 states and 1369 transitions. [2025-03-04 16:19:45,108 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-04 16:19:45,108 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 909 states and 1369 transitions. [2025-03-04 16:19:45,111 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 376 [2025-03-04 16:19:45,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:45,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:45,112 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,112 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,112 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-04 16:19:45,112 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume !(0 == ~comp_m1_st~0);" [2025-03-04 16:19:45,112 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,112 INFO L85 PathProgramCache]: Analyzing trace with hash 432230803, now seen corresponding path program 2 times [2025-03-04 16:19:45,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158727389] [2025-03-04 16:19:45,112 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:19:45,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,116 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:45,118 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:45,118 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:45,118 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:45,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:45,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:45,131 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158727389] [2025-03-04 16:19:45,131 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1158727389] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:45,131 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:45,131 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:45,131 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953074499] [2025-03-04 16:19:45,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:45,132 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:45,132 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,132 INFO L85 PathProgramCache]: Analyzing trace with hash 290680753, now seen corresponding path program 1 times [2025-03-04 16:19:45,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535651340] [2025-03-04 16:19:45,132 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:45,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,134 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-03-04 16:19:45,134 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-03-04 16:19:45,134 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,135 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:45,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:45,140 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:45,140 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535651340] [2025-03-04 16:19:45,140 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535651340] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:45,140 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:45,140 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:19:45,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902067048] [2025-03-04 16:19:45,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:45,140 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:45,140 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:45,140 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:45,141 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:45,141 INFO L87 Difference]: Start difference. First operand 909 states and 1369 transitions. cyclomatic complexity: 469 Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:45,161 INFO L93 Difference]: Finished difference Result 1111 states and 1643 transitions. [2025-03-04 16:19:45,161 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1111 states and 1643 transitions. [2025-03-04 16:19:45,166 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2025-03-04 16:19:45,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1111 states to 1111 states and 1643 transitions. [2025-03-04 16:19:45,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 526 [2025-03-04 16:19:45,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 526 [2025-03-04 16:19:45,170 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1111 states and 1643 transitions. [2025-03-04 16:19:45,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:45,171 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1111 states and 1643 transitions. [2025-03-04 16:19:45,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1111 states and 1643 transitions. [2025-03-04 16:19:45,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1111 to 1111. [2025-03-04 16:19:45,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1111 states, 1111 states have (on average 1.478847884788479) internal successors, (1643), 1110 states have internal predecessors, (1643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1111 states to 1111 states and 1643 transitions. [2025-03-04 16:19:45,186 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1111 states and 1643 transitions. [2025-03-04 16:19:45,186 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:45,186 INFO L432 stractBuchiCegarLoop]: Abstraction has 1111 states and 1643 transitions. [2025-03-04 16:19:45,186 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-04 16:19:45,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1111 states and 1643 transitions. [2025-03-04 16:19:45,190 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2025-03-04 16:19:45,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:45,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:45,191 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,191 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,191 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~comp_m1_i~0;~comp_m1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-04 16:19:45,191 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-04 16:19:45,191 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,191 INFO L85 PathProgramCache]: Analyzing trace with hash 220879890, now seen corresponding path program 1 times [2025-03-04 16:19:45,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,192 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [676046831] [2025-03-04 16:19:45,192 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:45,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,195 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:45,196 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:45,196 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,197 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:45,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:45,223 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:45,223 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [676046831] [2025-03-04 16:19:45,223 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [676046831] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:45,223 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:45,223 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:19:45,223 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [119044577] [2025-03-04 16:19:45,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:45,223 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:45,223 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,223 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 1 times [2025-03-04 16:19:45,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,224 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143631790] [2025-03-04 16:19:45,224 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:45,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,225 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,226 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,226 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,226 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,226 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:45,227 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,227 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,228 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,228 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,229 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:45,244 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:45,245 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:19:45,245 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:19:45,245 INFO L87 Difference]: Start difference. First operand 1111 states and 1643 transitions. cyclomatic complexity: 541 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:45,280 INFO L93 Difference]: Finished difference Result 1097 states and 1619 transitions. [2025-03-04 16:19:45,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1097 states and 1619 transitions. [2025-03-04 16:19:45,284 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2025-03-04 16:19:45,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1097 states to 1097 states and 1619 transitions. [2025-03-04 16:19:45,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 512 [2025-03-04 16:19:45,289 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 512 [2025-03-04 16:19:45,289 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1097 states and 1619 transitions. [2025-03-04 16:19:45,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:45,290 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1097 states and 1619 transitions. [2025-03-04 16:19:45,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1097 states and 1619 transitions. [2025-03-04 16:19:45,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1097 to 1097. [2025-03-04 16:19:45,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1097 states, 1097 states have (on average 1.4758432087511395) internal successors, (1619), 1096 states have internal predecessors, (1619), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1097 states to 1097 states and 1619 transitions. [2025-03-04 16:19:45,303 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1097 states and 1619 transitions. [2025-03-04 16:19:45,303 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:19:45,303 INFO L432 stractBuchiCegarLoop]: Abstraction has 1097 states and 1619 transitions. [2025-03-04 16:19:45,303 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-04 16:19:45,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1097 states and 1619 transitions. [2025-03-04 16:19:45,307 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2025-03-04 16:19:45,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:45,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:45,307 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,308 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,308 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-04 16:19:45,308 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-04 16:19:45,308 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,308 INFO L85 PathProgramCache]: Analyzing trace with hash 628744308, now seen corresponding path program 1 times [2025-03-04 16:19:45,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,308 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [921962939] [2025-03-04 16:19:45,309 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:45,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,312 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:45,313 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:45,313 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,313 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:45,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:45,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:45,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [921962939] [2025-03-04 16:19:45,326 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [921962939] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:45,326 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:45,326 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:45,326 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278390033] [2025-03-04 16:19:45,326 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:45,326 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:45,327 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,327 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 2 times [2025-03-04 16:19:45,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,327 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505583517] [2025-03-04 16:19:45,327 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:19:45,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,329 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,329 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,329 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:45,329 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,329 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:45,330 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,330 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,330 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,331 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,331 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:45,347 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:45,348 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:45,348 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:45,348 INFO L87 Difference]: Start difference. First operand 1097 states and 1619 transitions. cyclomatic complexity: 531 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:45,371 INFO L93 Difference]: Finished difference Result 1394 states and 2020 transitions. [2025-03-04 16:19:45,372 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1394 states and 2020 transitions. [2025-03-04 16:19:45,378 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 584 [2025-03-04 16:19:45,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1394 states to 1394 states and 2020 transitions. [2025-03-04 16:19:45,383 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 644 [2025-03-04 16:19:45,384 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 644 [2025-03-04 16:19:45,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1394 states and 2020 transitions. [2025-03-04 16:19:45,385 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:45,385 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1394 states and 2020 transitions. [2025-03-04 16:19:45,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1394 states and 2020 transitions. [2025-03-04 16:19:45,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1394 to 1394. [2025-03-04 16:19:45,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1394 states, 1394 states have (on average 1.449067431850789) internal successors, (2020), 1393 states have internal predecessors, (2020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1394 states to 1394 states and 2020 transitions. [2025-03-04 16:19:45,403 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1394 states and 2020 transitions. [2025-03-04 16:19:45,403 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:45,404 INFO L432 stractBuchiCegarLoop]: Abstraction has 1394 states and 2020 transitions. [2025-03-04 16:19:45,404 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-04 16:19:45,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1394 states and 2020 transitions. [2025-03-04 16:19:45,408 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 584 [2025-03-04 16:19:45,408 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:45,408 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:45,409 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,409 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,409 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-04 16:19:45,409 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-04 16:19:45,409 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,410 INFO L85 PathProgramCache]: Analyzing trace with hash 1625816661, now seen corresponding path program 1 times [2025-03-04 16:19:45,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,410 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882381614] [2025-03-04 16:19:45,410 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:45,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,414 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:45,417 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:45,417 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,417 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:45,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:45,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:45,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882381614] [2025-03-04 16:19:45,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882381614] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:45,426 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:45,427 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:45,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1187780555] [2025-03-04 16:19:45,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:45,427 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:45,427 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,427 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 3 times [2025-03-04 16:19:45,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,427 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529893633] [2025-03-04 16:19:45,427 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:19:45,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,429 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,430 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,430 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:19:45,430 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,430 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:45,431 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,431 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,431 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,432 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,433 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:45,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:45,461 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:45,461 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:45,461 INFO L87 Difference]: Start difference. First operand 1394 states and 2020 transitions. cyclomatic complexity: 635 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:45,479 INFO L93 Difference]: Finished difference Result 1547 states and 2225 transitions. [2025-03-04 16:19:45,479 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1547 states and 2225 transitions. [2025-03-04 16:19:45,485 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 686 [2025-03-04 16:19:45,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1547 states to 1547 states and 2225 transitions. [2025-03-04 16:19:45,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2025-03-04 16:19:45,491 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2025-03-04 16:19:45,491 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1547 states and 2225 transitions. [2025-03-04 16:19:45,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:45,492 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1547 states and 2225 transitions. [2025-03-04 16:19:45,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1547 states and 2225 transitions. [2025-03-04 16:19:45,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1547 to 1547. [2025-03-04 16:19:45,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1547 states, 1547 states have (on average 1.438267614738203) internal successors, (2225), 1546 states have internal predecessors, (2225), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1547 states to 1547 states and 2225 transitions. [2025-03-04 16:19:45,509 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1547 states and 2225 transitions. [2025-03-04 16:19:45,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:45,509 INFO L432 stractBuchiCegarLoop]: Abstraction has 1547 states and 2225 transitions. [2025-03-04 16:19:45,509 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-04 16:19:45,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1547 states and 2225 transitions. [2025-03-04 16:19:45,514 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 686 [2025-03-04 16:19:45,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:45,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:45,515 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,515 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,515 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-04 16:19:45,515 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-04 16:19:45,515 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,515 INFO L85 PathProgramCache]: Analyzing trace with hash 272506964, now seen corresponding path program 1 times [2025-03-04 16:19:45,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,516 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76347906] [2025-03-04 16:19:45,516 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:45,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,520 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:45,522 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:45,522 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,522 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:45,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:45,532 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:45,532 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [76347906] [2025-03-04 16:19:45,532 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [76347906] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:45,532 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:45,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:45,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [180297901] [2025-03-04 16:19:45,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:45,533 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:45,533 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,533 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 4 times [2025-03-04 16:19:45,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941889772] [2025-03-04 16:19:45,533 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:19:45,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,534 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 8 statements into 2 equivalence classes. [2025-03-04 16:19:45,535 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,535 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 16:19:45,535 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,535 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:45,536 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,537 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,537 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,537 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,538 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:45,553 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:45,553 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:45,553 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:45,553 INFO L87 Difference]: Start difference. First operand 1547 states and 2225 transitions. cyclomatic complexity: 687 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:45,574 INFO L93 Difference]: Finished difference Result 1691 states and 2415 transitions. [2025-03-04 16:19:45,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1691 states and 2415 transitions. [2025-03-04 16:19:45,580 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 793 [2025-03-04 16:19:45,585 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1691 states to 1691 states and 2415 transitions. [2025-03-04 16:19:45,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 853 [2025-03-04 16:19:45,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 853 [2025-03-04 16:19:45,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1691 states and 2415 transitions. [2025-03-04 16:19:45,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:45,586 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1691 states and 2415 transitions. [2025-03-04 16:19:45,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1691 states and 2415 transitions. [2025-03-04 16:19:45,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1691 to 1691. [2025-03-04 16:19:45,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1691 states, 1691 states have (on average 1.4281490242460082) internal successors, (2415), 1690 states have internal predecessors, (2415), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1691 states to 1691 states and 2415 transitions. [2025-03-04 16:19:45,605 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1691 states and 2415 transitions. [2025-03-04 16:19:45,605 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:45,605 INFO L432 stractBuchiCegarLoop]: Abstraction has 1691 states and 2415 transitions. [2025-03-04 16:19:45,605 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-04 16:19:45,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1691 states and 2415 transitions. [2025-03-04 16:19:45,616 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 793 [2025-03-04 16:19:45,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:45,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:45,617 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,617 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,617 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-04 16:19:45,617 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-04 16:19:45,617 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,617 INFO L85 PathProgramCache]: Analyzing trace with hash 783041141, now seen corresponding path program 1 times [2025-03-04 16:19:45,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641724403] [2025-03-04 16:19:45,617 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:45,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,621 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:45,622 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:45,622 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,622 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:45,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:45,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:45,632 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641724403] [2025-03-04 16:19:45,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641724403] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:45,632 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:45,632 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:45,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1608992902] [2025-03-04 16:19:45,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:45,632 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:45,633 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,633 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 5 times [2025-03-04 16:19:45,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123127121] [2025-03-04 16:19:45,633 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 16:19:45,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,634 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,635 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,635 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:45,635 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,635 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:45,635 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,635 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,635 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,635 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,636 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:45,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:45,652 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:45,652 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:45,652 INFO L87 Difference]: Start difference. First operand 1691 states and 2415 transitions. cyclomatic complexity: 733 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:45,672 INFO L93 Difference]: Finished difference Result 1846 states and 2629 transitions. [2025-03-04 16:19:45,672 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1846 states and 2629 transitions. [2025-03-04 16:19:45,676 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 866 [2025-03-04 16:19:45,682 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1846 states to 1846 states and 2629 transitions. [2025-03-04 16:19:45,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2025-03-04 16:19:45,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2025-03-04 16:19:45,683 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1846 states and 2629 transitions. [2025-03-04 16:19:45,683 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:45,683 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1846 states and 2629 transitions. [2025-03-04 16:19:45,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1846 states and 2629 transitions. [2025-03-04 16:19:45,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1846 to 1846. [2025-03-04 16:19:45,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1846 states, 1846 states have (on average 1.424160346695558) internal successors, (2629), 1845 states have internal predecessors, (2629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1846 states to 1846 states and 2629 transitions. [2025-03-04 16:19:45,703 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1846 states and 2629 transitions. [2025-03-04 16:19:45,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:45,704 INFO L432 stractBuchiCegarLoop]: Abstraction has 1846 states and 2629 transitions. [2025-03-04 16:19:45,704 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-04 16:19:45,704 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1846 states and 2629 transitions. [2025-03-04 16:19:45,707 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 866 [2025-03-04 16:19:45,707 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:45,708 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:45,708 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,708 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,708 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-04 16:19:45,708 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-04 16:19:45,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,708 INFO L85 PathProgramCache]: Analyzing trace with hash -959769194, now seen corresponding path program 1 times [2025-03-04 16:19:45,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859824428] [2025-03-04 16:19:45,709 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:45,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,712 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:45,713 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:45,713 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,713 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:45,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:45,724 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:45,724 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859824428] [2025-03-04 16:19:45,724 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1859824428] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:45,724 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:45,724 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:45,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [231733489] [2025-03-04 16:19:45,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:45,724 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:45,725 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,725 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 6 times [2025-03-04 16:19:45,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771148697] [2025-03-04 16:19:45,725 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 16:19:45,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,726 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,727 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,727 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 16:19:45,727 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,727 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:45,727 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,728 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,728 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,728 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,729 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:45,745 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:45,746 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:45,746 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:45,746 INFO L87 Difference]: Start difference. First operand 1846 states and 2629 transitions. cyclomatic complexity: 792 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:45,765 INFO L93 Difference]: Finished difference Result 2125 states and 3031 transitions. [2025-03-04 16:19:45,765 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2125 states and 3031 transitions. [2025-03-04 16:19:45,772 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 988 [2025-03-04 16:19:45,778 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2125 states to 2125 states and 3031 transitions. [2025-03-04 16:19:45,778 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1048 [2025-03-04 16:19:45,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1048 [2025-03-04 16:19:45,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2125 states and 3031 transitions. [2025-03-04 16:19:45,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:45,779 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2125 states and 3031 transitions. [2025-03-04 16:19:45,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2125 states and 3031 transitions. [2025-03-04 16:19:45,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2125 to 2125. [2025-03-04 16:19:45,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2125 states, 2125 states have (on average 1.4263529411764706) internal successors, (3031), 2124 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2125 states to 2125 states and 3031 transitions. [2025-03-04 16:19:45,802 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2125 states and 3031 transitions. [2025-03-04 16:19:45,802 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:45,802 INFO L432 stractBuchiCegarLoop]: Abstraction has 2125 states and 3031 transitions. [2025-03-04 16:19:45,802 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-04 16:19:45,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2125 states and 3031 transitions. [2025-03-04 16:19:45,806 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 988 [2025-03-04 16:19:45,808 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:45,808 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:45,808 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,808 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,808 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-04 16:19:45,808 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-04 16:19:45,809 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,809 INFO L85 PathProgramCache]: Analyzing trace with hash -1847272875, now seen corresponding path program 1 times [2025-03-04 16:19:45,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,809 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412364555] [2025-03-04 16:19:45,809 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:45,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,812 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:45,814 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:45,814 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,814 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:45,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:45,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:45,827 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412364555] [2025-03-04 16:19:45,827 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412364555] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:45,827 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:45,827 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:45,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1622361344] [2025-03-04 16:19:45,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:45,828 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:45,828 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,828 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 7 times [2025-03-04 16:19:45,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,828 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961934999] [2025-03-04 16:19:45,828 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 16:19:45,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,829 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,830 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,830 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,830 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,830 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:45,830 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,831 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,832 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,832 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,832 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:45,848 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:45,848 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:45,848 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:45,849 INFO L87 Difference]: Start difference. First operand 2125 states and 3031 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:45,873 INFO L93 Difference]: Finished difference Result 2598 states and 3693 transitions. [2025-03-04 16:19:45,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2598 states and 3693 transitions. [2025-03-04 16:19:45,881 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1098 [2025-03-04 16:19:45,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2598 states to 2447 states and 3458 transitions. [2025-03-04 16:19:45,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1162 [2025-03-04 16:19:45,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1162 [2025-03-04 16:19:45,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2447 states and 3458 transitions. [2025-03-04 16:19:45,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:45,890 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2447 states and 3458 transitions. [2025-03-04 16:19:45,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2447 states and 3458 transitions. [2025-03-04 16:19:45,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2447 to 2447. [2025-03-04 16:19:45,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2447 states, 2447 states have (on average 1.4131589701675522) internal successors, (3458), 2446 states have internal predecessors, (3458), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:45,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2447 states to 2447 states and 3458 transitions. [2025-03-04 16:19:45,940 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2447 states and 3458 transitions. [2025-03-04 16:19:45,940 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:45,941 INFO L432 stractBuchiCegarLoop]: Abstraction has 2447 states and 3458 transitions. [2025-03-04 16:19:45,941 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-04 16:19:45,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2447 states and 3458 transitions. [2025-03-04 16:19:45,946 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1098 [2025-03-04 16:19:45,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:45,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:45,946 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,946 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:45,946 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-04 16:19:45,946 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-04 16:19:45,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,947 INFO L85 PathProgramCache]: Analyzing trace with hash -1875902026, now seen corresponding path program 1 times [2025-03-04 16:19:45,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109738547] [2025-03-04 16:19:45,947 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:45,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,951 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:45,952 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:45,952 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,952 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:45,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:45,965 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:45,965 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109738547] [2025-03-04 16:19:45,965 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2109738547] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:45,965 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:45,965 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:45,965 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1822617908] [2025-03-04 16:19:45,965 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:45,965 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:45,965 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:45,965 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 8 times [2025-03-04 16:19:45,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:45,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601140894] [2025-03-04 16:19:45,966 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:19:45,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:45,968 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,968 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,968 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:45,968 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,968 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:45,969 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:45,969 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:45,969 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:45,969 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:45,972 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:45,988 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:45,988 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:45,989 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:45,989 INFO L87 Difference]: Start difference. First operand 2447 states and 3458 transitions. cyclomatic complexity: 1020 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:46,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:46,010 INFO L93 Difference]: Finished difference Result 3167 states and 4405 transitions. [2025-03-04 16:19:46,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3167 states and 4405 transitions. [2025-03-04 16:19:46,017 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1251 [2025-03-04 16:19:46,025 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3167 states to 2931 states and 4063 transitions. [2025-03-04 16:19:46,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1307 [2025-03-04 16:19:46,026 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1307 [2025-03-04 16:19:46,026 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2931 states and 4063 transitions. [2025-03-04 16:19:46,026 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:19:46,026 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2931 states and 4063 transitions. [2025-03-04 16:19:46,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2931 states and 4063 transitions. [2025-03-04 16:19:46,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2931 to 2931. [2025-03-04 16:19:46,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2931 states, 2931 states have (on average 1.386216308427158) internal successors, (4063), 2930 states have internal predecessors, (4063), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:46,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2931 states to 2931 states and 4063 transitions. [2025-03-04 16:19:46,055 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2931 states and 4063 transitions. [2025-03-04 16:19:46,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:46,055 INFO L432 stractBuchiCegarLoop]: Abstraction has 2931 states and 4063 transitions. [2025-03-04 16:19:46,056 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-03-04 16:19:46,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2931 states and 4063 transitions. [2025-03-04 16:19:46,062 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1251 [2025-03-04 16:19:46,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:46,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:46,062 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:46,062 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:46,062 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-03-04 16:19:46,062 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-03-04 16:19:46,062 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:46,063 INFO L85 PathProgramCache]: Analyzing trace with hash -1876825547, now seen corresponding path program 1 times [2025-03-04 16:19:46,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:46,063 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067542717] [2025-03-04 16:19:46,063 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:46,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:46,066 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:46,067 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:46,067 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:46,067 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:46,067 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:46,069 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:46,070 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:46,070 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:46,070 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:46,074 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:46,074 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:46,074 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 9 times [2025-03-04 16:19:46,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:46,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113056114] [2025-03-04 16:19:46,075 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:19:46,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:46,076 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:46,077 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:46,077 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:19:46,077 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:46,077 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:46,077 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:19:46,078 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:19:46,078 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:46,078 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:46,079 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:46,079 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:46,079 INFO L85 PathProgramCache]: Analyzing trace with hash -1550254834, now seen corresponding path program 1 times [2025-03-04 16:19:46,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:46,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1360100280] [2025-03-04 16:19:46,079 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:46,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:46,082 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-03-04 16:19:46,083 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-04 16:19:46,084 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:46,084 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:46,084 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:46,085 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-03-04 16:19:46,086 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-04 16:19:46,087 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:46,087 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:46,091 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:46,763 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:46,768 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:46,768 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:46,768 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:46,768 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:46,774 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:46,781 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:46,782 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:46,782 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:46,866 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 04.03 04:19:46 BoogieIcfgContainer [2025-03-04 16:19:46,866 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-04 16:19:46,867 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-04 16:19:46,867 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-04 16:19:46,867 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-04 16:19:46,868 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:19:41" (3/4) ... [2025-03-04 16:19:46,870 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-03-04 16:19:46,929 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-04 16:19:46,929 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-04 16:19:46,929 INFO L158 Benchmark]: Toolchain (without parser) took 6558.60ms. Allocated memory was 142.6MB in the beginning and 251.7MB in the end (delta: 109.1MB). Free memory was 111.8MB in the beginning and 128.5MB in the end (delta: -16.6MB). Peak memory consumption was 94.6MB. Max. memory is 16.1GB. [2025-03-04 16:19:46,930 INFO L158 Benchmark]: CDTParser took 0.21ms. Allocated memory is still 201.3MB. Free memory is still 122.3MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:19:46,930 INFO L158 Benchmark]: CACSL2BoogieTranslator took 241.70ms. Allocated memory is still 142.6MB. Free memory was 111.8MB in the beginning and 98.7MB in the end (delta: 13.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 16:19:46,930 INFO L158 Benchmark]: Boogie Procedure Inliner took 27.85ms. Allocated memory is still 142.6MB. Free memory was 98.7MB in the beginning and 96.4MB in the end (delta: 2.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 16:19:46,930 INFO L158 Benchmark]: Boogie Preprocessor took 29.65ms. Allocated memory is still 142.6MB. Free memory was 96.4MB in the beginning and 94.5MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:19:46,930 INFO L158 Benchmark]: IcfgBuilder took 438.93ms. Allocated memory is still 142.6MB. Free memory was 94.5MB in the beginning and 71.3MB in the end (delta: 23.3MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2025-03-04 16:19:46,930 INFO L158 Benchmark]: BuchiAutomizer took 5753.27ms. Allocated memory was 142.6MB in the beginning and 251.7MB in the end (delta: 109.1MB). Free memory was 71.3MB in the beginning and 136.8MB in the end (delta: -65.6MB). Peak memory consumption was 44.3MB. Max. memory is 16.1GB. [2025-03-04 16:19:46,930 INFO L158 Benchmark]: Witness Printer took 62.09ms. Allocated memory is still 251.7MB. Free memory was 136.8MB in the beginning and 128.5MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 16:19:46,931 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21ms. Allocated memory is still 201.3MB. Free memory is still 122.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 241.70ms. Allocated memory is still 142.6MB. Free memory was 111.8MB in the beginning and 98.7MB in the end (delta: 13.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 27.85ms. Allocated memory is still 142.6MB. Free memory was 98.7MB in the beginning and 96.4MB in the end (delta: 2.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 29.65ms. Allocated memory is still 142.6MB. Free memory was 96.4MB in the beginning and 94.5MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 438.93ms. Allocated memory is still 142.6MB. Free memory was 94.5MB in the beginning and 71.3MB in the end (delta: 23.3MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 5753.27ms. Allocated memory was 142.6MB in the beginning and 251.7MB in the end (delta: 109.1MB). Free memory was 71.3MB in the beginning and 136.8MB in the end (delta: -65.6MB). Peak memory consumption was 44.3MB. Max. memory is 16.1GB. * Witness Printer took 62.09ms. Allocated memory is still 251.7MB. Free memory was 136.8MB in the beginning and 128.5MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (20 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * d1_ev) + 1) and consists of 3 locations. One deterministic module has affine ranking function (((long long) -1 * d0_ev) + 1) and consists of 3 locations. 20 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 2931 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.6s and 21 iterations. TraceHistogramMax:1. Analysis of lassos took 3.9s. Construction of modules took 0.2s. Büchi inclusion checks took 1.2s. Highest rank in rank-based complementation 3. Minimization of det autom 8. Minimization of nondet autom 14. Automata minimization 0.3s AutomataMinimizationTime, 22 MinimizatonAttempts, 28 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 797 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 795 mSDsluCounter, 8503 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 4629 mSDsCounter, 57 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 303 IncrementalHoareTripleChecker+Invalid, 360 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 57 mSolverCounterUnsat, 3874 mSDtfsCounter, 303 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT0 conc0 concLT0 SILN8 SILU0 SILI10 SILT2 lasso0 LassoPreprocessingBenchmarks: Lassos: inital60 mio100 ax100 hnf100 lsp15 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq184 hnf97 smp100 dnf152 smp86 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 24ms VariablesStem: 0 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 1 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 285]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 285]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-03-04 16:19:46,949 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)