./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/kundu1.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/kundu1.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c114a15ea6b1c9b012290758a6a9559b9c02a944706c9768958a3bd9c86822a7 --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 16:19:45,400 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 16:19:45,459 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-04 16:19:45,464 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 16:19:45,465 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 16:19:45,465 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 16:19:45,486 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 16:19:45,487 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 16:19:45,487 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 16:19:45,488 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 16:19:45,488 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 16:19:45,489 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 16:19:45,489 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 16:19:45,489 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 16:19:45,489 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 16:19:45,490 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 16:19:45,490 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 16:19:45,490 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 16:19:45,490 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 16:19:45,490 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 16:19:45,490 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 16:19:45,490 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 16:19:45,490 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-04 16:19:45,490 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 16:19:45,490 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-04 16:19:45,490 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 16:19:45,490 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 16:19:45,491 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 16:19:45,491 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 16:19:45,491 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 16:19:45,491 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-04 16:19:45,491 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 16:19:45,491 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 16:19:45,491 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 16:19:45,491 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 16:19:45,491 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 16:19:45,491 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 16:19:45,491 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 16:19:45,491 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 16:19:45,492 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 16:19:45,492 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c114a15ea6b1c9b012290758a6a9559b9c02a944706c9768958a3bd9c86822a7 [2025-03-04 16:19:45,684 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 16:19:45,689 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 16:19:45,691 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 16:19:45,692 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 16:19:45,692 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 16:19:45,692 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/kundu1.cil.c [2025-03-04 16:19:46,832 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e7cf8e0fd/4f356bb62d8742bcaf7f3b0121600481/FLAG6de50e080 [2025-03-04 16:19:47,051 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 16:19:47,052 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu1.cil.c [2025-03-04 16:19:47,061 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e7cf8e0fd/4f356bb62d8742bcaf7f3b0121600481/FLAG6de50e080 [2025-03-04 16:19:47,405 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e7cf8e0fd/4f356bb62d8742bcaf7f3b0121600481 [2025-03-04 16:19:47,407 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 16:19:47,409 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 16:19:47,410 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 16:19:47,411 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 16:19:47,414 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 16:19:47,414 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,415 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@58d265d2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47, skipping insertion in model container [2025-03-04 16:19:47,415 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,437 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 16:19:47,577 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:19:47,588 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 16:19:47,618 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:19:47,640 INFO L204 MainTranslator]: Completed translation [2025-03-04 16:19:47,640 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47 WrapperNode [2025-03-04 16:19:47,641 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 16:19:47,641 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 16:19:47,641 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 16:19:47,641 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 16:19:47,646 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,656 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,678 INFO L138 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 37, statements flattened = 363 [2025-03-04 16:19:47,679 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 16:19:47,679 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 16:19:47,680 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 16:19:47,680 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 16:19:47,686 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,686 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,688 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,695 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-04 16:19:47,695 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,695 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,699 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,700 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,701 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,701 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,702 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 16:19:47,703 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 16:19:47,703 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 16:19:47,703 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 16:19:47,704 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47" (1/1) ... [2025-03-04 16:19:47,707 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:47,715 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:47,725 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:47,726 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 16:19:47,741 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-04 16:19:47,741 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-04 16:19:47,741 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 16:19:47,741 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 16:19:47,793 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 16:19:47,795 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 16:19:48,145 INFO L? ?]: Removed 68 outVars from TransFormulas that were not future-live. [2025-03-04 16:19:48,146 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 16:19:48,154 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 16:19:48,154 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-04 16:19:48,154 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:19:48 BoogieIcfgContainer [2025-03-04 16:19:48,155 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 16:19:48,155 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 16:19:48,155 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 16:19:48,158 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 16:19:48,159 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:19:48,159 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 04:19:47" (1/3) ... [2025-03-04 16:19:48,159 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2044a78a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:19:48, skipping insertion in model container [2025-03-04 16:19:48,159 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:19:48,159 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:47" (2/3) ... [2025-03-04 16:19:48,159 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2044a78a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:19:48, skipping insertion in model container [2025-03-04 16:19:48,160 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:19:48,160 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:19:48" (3/3) ... [2025-03-04 16:19:48,160 INFO L363 chiAutomizerObserver]: Analyzing ICFG kundu1.cil.c [2025-03-04 16:19:48,193 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 16:19:48,194 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 16:19:48,194 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 16:19:48,194 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 16:19:48,194 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 16:19:48,195 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 16:19:48,195 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 16:19:48,195 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 16:19:48,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 132 states, 131 states have (on average 1.4351145038167938) internal successors, (188), 131 states have internal predecessors, (188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:48,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 103 [2025-03-04 16:19:48,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:48,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:48,226 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:48,227 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:48,227 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 16:19:48,229 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 132 states, 131 states have (on average 1.4351145038167938) internal successors, (188), 131 states have internal predecessors, (188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:48,235 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 103 [2025-03-04 16:19:48,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:48,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:48,238 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:48,238 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:48,245 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~P_1_i~0);~P_1_st~0 := 2;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:48,245 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume !true;" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:48,250 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:48,253 INFO L85 PathProgramCache]: Analyzing trace with hash 47334983, now seen corresponding path program 1 times [2025-03-04 16:19:48,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:48,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [813564779] [2025-03-04 16:19:48,259 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:48,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:48,316 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-04 16:19:48,329 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-04 16:19:48,330 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:48,330 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:48,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:48,417 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:48,417 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [813564779] [2025-03-04 16:19:48,418 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [813564779] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:48,418 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:48,418 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:48,420 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1136358634] [2025-03-04 16:19:48,420 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:48,423 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:48,423 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:48,424 INFO L85 PathProgramCache]: Analyzing trace with hash -1089582804, now seen corresponding path program 1 times [2025-03-04 16:19:48,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:48,424 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791457975] [2025-03-04 16:19:48,424 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:48,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:48,430 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-04 16:19:48,433 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 16:19:48,434 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:48,434 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:48,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:48,446 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:48,446 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [791457975] [2025-03-04 16:19:48,446 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [791457975] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:48,446 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:48,446 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:19:48,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [691827615] [2025-03-04 16:19:48,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:48,447 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:48,447 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:48,466 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:48,466 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:48,468 INFO L87 Difference]: Start difference. First operand has 132 states, 131 states have (on average 1.4351145038167938) internal successors, (188), 131 states have internal predecessors, (188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 7.0) internal successors, (21), 3 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:48,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:48,495 INFO L93 Difference]: Finished difference Result 126 states and 176 transitions. [2025-03-04 16:19:48,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126 states and 176 transitions. [2025-03-04 16:19:48,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2025-03-04 16:19:48,506 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126 states to 119 states and 169 transitions. [2025-03-04 16:19:48,506 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 119 [2025-03-04 16:19:48,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 119 [2025-03-04 16:19:48,509 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119 states and 169 transitions. [2025-03-04 16:19:48,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:48,510 INFO L218 hiAutomatonCegarLoop]: Abstraction has 119 states and 169 transitions. [2025-03-04 16:19:48,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states and 169 transitions. [2025-03-04 16:19:48,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 119. [2025-03-04 16:19:48,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 119 states, 119 states have (on average 1.4201680672268908) internal successors, (169), 118 states have internal predecessors, (169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:48,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 169 transitions. [2025-03-04 16:19:48,536 INFO L240 hiAutomatonCegarLoop]: Abstraction has 119 states and 169 transitions. [2025-03-04 16:19:48,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:48,539 INFO L432 stractBuchiCegarLoop]: Abstraction has 119 states and 169 transitions. [2025-03-04 16:19:48,539 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 16:19:48,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 119 states and 169 transitions. [2025-03-04 16:19:48,541 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2025-03-04 16:19:48,541 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:48,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:48,543 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:48,543 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:48,543 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:48,543 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:48,544 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:48,544 INFO L85 PathProgramCache]: Analyzing trace with hash -1305974714, now seen corresponding path program 1 times [2025-03-04 16:19:48,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:48,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672060069] [2025-03-04 16:19:48,544 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:48,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:48,551 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-04 16:19:48,558 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-04 16:19:48,558 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:48,558 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:48,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:48,594 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:48,594 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [672060069] [2025-03-04 16:19:48,594 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [672060069] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:48,594 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:48,594 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:48,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1364363670] [2025-03-04 16:19:48,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:48,595 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:48,595 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:48,595 INFO L85 PathProgramCache]: Analyzing trace with hash -880660716, now seen corresponding path program 1 times [2025-03-04 16:19:48,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:48,595 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198727366] [2025-03-04 16:19:48,595 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:48,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:48,607 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-03-04 16:19:48,621 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-03-04 16:19:48,622 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:48,622 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:48,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:48,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:48,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [198727366] [2025-03-04 16:19:48,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [198727366] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:48,690 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:48,690 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:48,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [249701871] [2025-03-04 16:19:48,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:48,690 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:48,690 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:48,691 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:48,691 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:48,691 INFO L87 Difference]: Start difference. First operand 119 states and 169 transitions. cyclomatic complexity: 51 Second operand has 3 states, 3 states have (on average 7.0) internal successors, (21), 3 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:48,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:48,707 INFO L93 Difference]: Finished difference Result 119 states and 168 transitions. [2025-03-04 16:19:48,707 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 119 states and 168 transitions. [2025-03-04 16:19:48,708 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2025-03-04 16:19:48,709 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 119 states to 119 states and 168 transitions. [2025-03-04 16:19:48,709 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 119 [2025-03-04 16:19:48,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 119 [2025-03-04 16:19:48,709 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119 states and 168 transitions. [2025-03-04 16:19:48,710 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:48,710 INFO L218 hiAutomatonCegarLoop]: Abstraction has 119 states and 168 transitions. [2025-03-04 16:19:48,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states and 168 transitions. [2025-03-04 16:19:48,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 119. [2025-03-04 16:19:48,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 119 states, 119 states have (on average 1.411764705882353) internal successors, (168), 118 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:48,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 168 transitions. [2025-03-04 16:19:48,714 INFO L240 hiAutomatonCegarLoop]: Abstraction has 119 states and 168 transitions. [2025-03-04 16:19:48,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:48,714 INFO L432 stractBuchiCegarLoop]: Abstraction has 119 states and 168 transitions. [2025-03-04 16:19:48,714 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 16:19:48,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 119 states and 168 transitions. [2025-03-04 16:19:48,717 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2025-03-04 16:19:48,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:48,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:48,718 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:48,718 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:48,718 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:48,718 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:48,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:48,719 INFO L85 PathProgramCache]: Analyzing trace with hash -795440537, now seen corresponding path program 1 times [2025-03-04 16:19:48,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:48,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899744588] [2025-03-04 16:19:48,719 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:48,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:48,724 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-04 16:19:48,737 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-04 16:19:48,737 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:48,737 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:48,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:48,787 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:48,787 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1899744588] [2025-03-04 16:19:48,787 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1899744588] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:48,787 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:48,788 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:48,788 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821815138] [2025-03-04 16:19:48,788 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:48,788 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:48,788 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:48,788 INFO L85 PathProgramCache]: Analyzing trace with hash -880660716, now seen corresponding path program 2 times [2025-03-04 16:19:48,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:48,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2072790294] [2025-03-04 16:19:48,788 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:19:48,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:48,800 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 36 statements into 1 equivalence classes. [2025-03-04 16:19:48,806 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-03-04 16:19:48,806 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:48,806 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:48,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:48,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:48,842 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2072790294] [2025-03-04 16:19:48,842 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2072790294] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:48,842 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:48,842 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:48,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509392842] [2025-03-04 16:19:48,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:48,843 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:48,843 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:48,843 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:48,843 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:48,843 INFO L87 Difference]: Start difference. First operand 119 states and 168 transitions. cyclomatic complexity: 50 Second operand has 3 states, 3 states have (on average 7.0) internal successors, (21), 3 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:48,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:48,893 INFO L93 Difference]: Finished difference Result 208 states and 290 transitions. [2025-03-04 16:19:48,893 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 208 states and 290 transitions. [2025-03-04 16:19:48,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 184 [2025-03-04 16:19:48,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 208 states to 208 states and 290 transitions. [2025-03-04 16:19:48,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 208 [2025-03-04 16:19:48,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 208 [2025-03-04 16:19:48,896 INFO L73 IsDeterministic]: Start isDeterministic. Operand 208 states and 290 transitions. [2025-03-04 16:19:48,897 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:48,897 INFO L218 hiAutomatonCegarLoop]: Abstraction has 208 states and 290 transitions. [2025-03-04 16:19:48,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states and 290 transitions. [2025-03-04 16:19:48,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 204. [2025-03-04 16:19:48,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 204 states, 204 states have (on average 1.3970588235294117) internal successors, (285), 203 states have internal predecessors, (285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:48,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 285 transitions. [2025-03-04 16:19:48,903 INFO L240 hiAutomatonCegarLoop]: Abstraction has 204 states and 285 transitions. [2025-03-04 16:19:48,904 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:48,904 INFO L432 stractBuchiCegarLoop]: Abstraction has 204 states and 285 transitions. [2025-03-04 16:19:48,904 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 16:19:48,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 285 transitions. [2025-03-04 16:19:48,906 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 180 [2025-03-04 16:19:48,907 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:48,907 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:48,908 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:48,908 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:48,908 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:48,908 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:48,909 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:48,909 INFO L85 PathProgramCache]: Analyzing trace with hash -1347008982, now seen corresponding path program 1 times [2025-03-04 16:19:48,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:48,909 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786448575] [2025-03-04 16:19:48,909 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:48,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:48,915 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-04 16:19:48,917 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-04 16:19:48,917 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:48,917 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:48,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:48,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:48,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786448575] [2025-03-04 16:19:48,948 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786448575] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:48,948 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:48,948 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:19:48,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [71771328] [2025-03-04 16:19:48,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:48,948 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:48,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:48,949 INFO L85 PathProgramCache]: Analyzing trace with hash 1471110743, now seen corresponding path program 1 times [2025-03-04 16:19:48,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:48,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1787575593] [2025-03-04 16:19:48,949 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:48,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:48,953 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-03-04 16:19:48,956 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-03-04 16:19:48,956 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:48,956 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:48,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:48,999 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:48,999 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1787575593] [2025-03-04 16:19:48,999 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1787575593] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:48,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:49,000 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:49,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220026174] [2025-03-04 16:19:49,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:49,000 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:49,000 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:49,000 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:19:49,000 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:19:49,000 INFO L87 Difference]: Start difference. First operand 204 states and 285 transitions. cyclomatic complexity: 82 Second operand has 4 states, 4 states have (on average 5.25) internal successors, (21), 4 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:49,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:49,102 INFO L93 Difference]: Finished difference Result 451 states and 615 transitions. [2025-03-04 16:19:49,102 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 451 states and 615 transitions. [2025-03-04 16:19:49,105 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 416 [2025-03-04 16:19:49,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 451 states to 451 states and 615 transitions. [2025-03-04 16:19:49,107 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 451 [2025-03-04 16:19:49,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 451 [2025-03-04 16:19:49,108 INFO L73 IsDeterministic]: Start isDeterministic. Operand 451 states and 615 transitions. [2025-03-04 16:19:49,109 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:49,109 INFO L218 hiAutomatonCegarLoop]: Abstraction has 451 states and 615 transitions. [2025-03-04 16:19:49,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states and 615 transitions. [2025-03-04 16:19:49,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 349. [2025-03-04 16:19:49,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 349 states, 349 states have (on average 1.3782234957020056) internal successors, (481), 348 states have internal predecessors, (481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:49,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 349 states to 349 states and 481 transitions. [2025-03-04 16:19:49,120 INFO L240 hiAutomatonCegarLoop]: Abstraction has 349 states and 481 transitions. [2025-03-04 16:19:49,120 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:19:49,121 INFO L432 stractBuchiCegarLoop]: Abstraction has 349 states and 481 transitions. [2025-03-04 16:19:49,121 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 16:19:49,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 349 states and 481 transitions. [2025-03-04 16:19:49,122 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 326 [2025-03-04 16:19:49,122 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:49,122 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:49,123 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:49,123 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:49,123 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume 2 == ~C_1_pc~0;" "assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:49,123 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume 2 == ~C_1_pc~0;" "assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:49,124 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,124 INFO L85 PathProgramCache]: Analyzing trace with hash 360461253, now seen corresponding path program 1 times [2025-03-04 16:19:49,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,124 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1526727987] [2025-03-04 16:19:49,124 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:49,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,130 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes. [2025-03-04 16:19:49,136 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-04 16:19:49,136 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,136 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:49,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:49,163 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:49,163 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1526727987] [2025-03-04 16:19:49,164 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1526727987] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:49,164 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:49,164 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:49,164 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429018332] [2025-03-04 16:19:49,164 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:49,164 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:49,164 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,166 INFO L85 PathProgramCache]: Analyzing trace with hash 1324942576, now seen corresponding path program 1 times [2025-03-04 16:19:49,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,166 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950797441] [2025-03-04 16:19:49,166 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:49,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,172 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-03-04 16:19:49,177 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-03-04 16:19:49,179 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,180 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:49,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:49,217 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:49,217 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950797441] [2025-03-04 16:19:49,217 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950797441] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:49,217 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:49,217 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:49,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039564476] [2025-03-04 16:19:49,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:49,218 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:49,218 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:49,218 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:49,219 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:49,219 INFO L87 Difference]: Start difference. First operand 349 states and 481 transitions. cyclomatic complexity: 133 Second operand has 3 states, 3 states have (on average 7.333333333333333) internal successors, (22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:49,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:49,254 INFO L93 Difference]: Finished difference Result 514 states and 697 transitions. [2025-03-04 16:19:49,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 514 states and 697 transitions. [2025-03-04 16:19:49,258 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 492 [2025-03-04 16:19:49,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 514 states to 514 states and 697 transitions. [2025-03-04 16:19:49,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 514 [2025-03-04 16:19:49,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 514 [2025-03-04 16:19:49,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 514 states and 697 transitions. [2025-03-04 16:19:49,261 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:49,262 INFO L218 hiAutomatonCegarLoop]: Abstraction has 514 states and 697 transitions. [2025-03-04 16:19:49,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 514 states and 697 transitions. [2025-03-04 16:19:49,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 514 to 498. [2025-03-04 16:19:49,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.359437751004016) internal successors, (677), 497 states have internal predecessors, (677), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:49,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 677 transitions. [2025-03-04 16:19:49,283 INFO L240 hiAutomatonCegarLoop]: Abstraction has 498 states and 677 transitions. [2025-03-04 16:19:49,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:49,284 INFO L432 stractBuchiCegarLoop]: Abstraction has 498 states and 677 transitions. [2025-03-04 16:19:49,284 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 16:19:49,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 677 transitions. [2025-03-04 16:19:49,286 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2025-03-04 16:19:49,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:49,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:49,286 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:49,286 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:49,286 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:49,286 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:49,287 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,287 INFO L85 PathProgramCache]: Analyzing trace with hash 1190706632, now seen corresponding path program 1 times [2025-03-04 16:19:49,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,287 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827040024] [2025-03-04 16:19:49,287 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:49,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,290 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes. [2025-03-04 16:19:49,293 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-04 16:19:49,293 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,293 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,293 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:49,294 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes. [2025-03-04 16:19:49,296 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-04 16:19:49,296 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,296 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,314 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:49,314 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,314 INFO L85 PathProgramCache]: Analyzing trace with hash -1820351885, now seen corresponding path program 1 times [2025-03-04 16:19:49,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,314 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965559747] [2025-03-04 16:19:49,314 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:49,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,321 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-03-04 16:19:49,326 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-03-04 16:19:49,326 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,326 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:49,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:49,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:49,353 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1965559747] [2025-03-04 16:19:49,353 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1965559747] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:49,353 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:49,353 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:49,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1580456127] [2025-03-04 16:19:49,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:49,354 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:49,354 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:49,354 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-04 16:19:49,354 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-04 16:19:49,354 INFO L87 Difference]: Start difference. First operand 498 states and 677 transitions. cyclomatic complexity: 180 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:49,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:49,403 INFO L93 Difference]: Finished difference Result 540 states and 719 transitions. [2025-03-04 16:19:49,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 540 states and 719 transitions. [2025-03-04 16:19:49,406 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 518 [2025-03-04 16:19:49,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 540 states to 540 states and 719 transitions. [2025-03-04 16:19:49,408 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 540 [2025-03-04 16:19:49,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 540 [2025-03-04 16:19:49,409 INFO L73 IsDeterministic]: Start isDeterministic. Operand 540 states and 719 transitions. [2025-03-04 16:19:49,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:49,409 INFO L218 hiAutomatonCegarLoop]: Abstraction has 540 states and 719 transitions. [2025-03-04 16:19:49,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states and 719 transitions. [2025-03-04 16:19:49,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 516. [2025-03-04 16:19:49,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 516 states, 516 states have (on average 1.3468992248062015) internal successors, (695), 515 states have internal predecessors, (695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:49,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 516 states to 516 states and 695 transitions. [2025-03-04 16:19:49,423 INFO L240 hiAutomatonCegarLoop]: Abstraction has 516 states and 695 transitions. [2025-03-04 16:19:49,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:19:49,424 INFO L432 stractBuchiCegarLoop]: Abstraction has 516 states and 695 transitions. [2025-03-04 16:19:49,424 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-04 16:19:49,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 516 states and 695 transitions. [2025-03-04 16:19:49,426 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 494 [2025-03-04 16:19:49,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:49,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:49,426 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:49,426 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:49,426 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:49,426 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~P_1_st~0);" "assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:49,427 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,427 INFO L85 PathProgramCache]: Analyzing trace with hash 1190706632, now seen corresponding path program 2 times [2025-03-04 16:19:49,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,427 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585015301] [2025-03-04 16:19:49,427 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:19:49,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,433 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 22 statements into 1 equivalence classes. [2025-03-04 16:19:49,437 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-04 16:19:49,437 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:49,437 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,437 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:49,440 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes. [2025-03-04 16:19:49,441 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-04 16:19:49,441 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,443 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,447 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:49,447 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,447 INFO L85 PathProgramCache]: Analyzing trace with hash 1760204618, now seen corresponding path program 1 times [2025-03-04 16:19:49,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,449 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455911306] [2025-03-04 16:19:49,449 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:49,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,454 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-04 16:19:49,459 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-04 16:19:49,459 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,459 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:49,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:49,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:49,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455911306] [2025-03-04 16:19:49,531 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1455911306] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:49,531 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:49,531 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:49,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1632699036] [2025-03-04 16:19:49,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:49,531 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:49,531 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:49,531 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-04 16:19:49,531 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-04 16:19:49,531 INFO L87 Difference]: Start difference. First operand 516 states and 695 transitions. cyclomatic complexity: 180 Second operand has 5 states, 5 states have (on average 7.6) internal successors, (38), 5 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:49,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:49,570 INFO L93 Difference]: Finished difference Result 534 states and 706 transitions. [2025-03-04 16:19:49,570 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 534 states and 706 transitions. [2025-03-04 16:19:49,573 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 512 [2025-03-04 16:19:49,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 534 states to 534 states and 706 transitions. [2025-03-04 16:19:49,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 534 [2025-03-04 16:19:49,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 534 [2025-03-04 16:19:49,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 534 states and 706 transitions. [2025-03-04 16:19:49,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:49,576 INFO L218 hiAutomatonCegarLoop]: Abstraction has 534 states and 706 transitions. [2025-03-04 16:19:49,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 534 states and 706 transitions. [2025-03-04 16:19:49,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 534 to 534. [2025-03-04 16:19:49,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 534 states, 534 states have (on average 1.3220973782771535) internal successors, (706), 533 states have internal predecessors, (706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:49,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 534 states to 534 states and 706 transitions. [2025-03-04 16:19:49,583 INFO L240 hiAutomatonCegarLoop]: Abstraction has 534 states and 706 transitions. [2025-03-04 16:19:49,583 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:19:49,585 INFO L432 stractBuchiCegarLoop]: Abstraction has 534 states and 706 transitions. [2025-03-04 16:19:49,585 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-04 16:19:49,585 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 534 states and 706 transitions. [2025-03-04 16:19:49,586 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 512 [2025-03-04 16:19:49,586 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:49,586 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:49,588 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:49,588 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:49,589 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:49,589 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~P_1_st~0);" "assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:49,589 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,589 INFO L85 PathProgramCache]: Analyzing trace with hash 1190706632, now seen corresponding path program 3 times [2025-03-04 16:19:49,589 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,589 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375091596] [2025-03-04 16:19:49,589 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:19:49,589 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,594 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 22 statements into 1 equivalence classes. [2025-03-04 16:19:49,598 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-04 16:19:49,598 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:19:49,598 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,598 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:49,599 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes. [2025-03-04 16:19:49,605 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-04 16:19:49,605 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,605 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,608 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:49,608 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,608 INFO L85 PathProgramCache]: Analyzing trace with hash -277851671, now seen corresponding path program 1 times [2025-03-04 16:19:49,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355638950] [2025-03-04 16:19:49,608 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:49,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,615 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-03-04 16:19:49,619 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-03-04 16:19:49,619 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,619 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:49,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:49,637 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:49,637 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355638950] [2025-03-04 16:19:49,637 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355638950] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:49,637 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:49,637 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:49,637 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1566181764] [2025-03-04 16:19:49,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:49,637 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:49,638 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:49,638 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:49,638 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:49,640 INFO L87 Difference]: Start difference. First operand 534 states and 706 transitions. cyclomatic complexity: 173 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:49,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:49,663 INFO L93 Difference]: Finished difference Result 774 states and 1005 transitions. [2025-03-04 16:19:49,663 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 774 states and 1005 transitions. [2025-03-04 16:19:49,666 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 741 [2025-03-04 16:19:49,668 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 774 states to 774 states and 1005 transitions. [2025-03-04 16:19:49,669 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 774 [2025-03-04 16:19:49,669 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 774 [2025-03-04 16:19:49,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 774 states and 1005 transitions. [2025-03-04 16:19:49,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:49,670 INFO L218 hiAutomatonCegarLoop]: Abstraction has 774 states and 1005 transitions. [2025-03-04 16:19:49,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 774 states and 1005 transitions. [2025-03-04 16:19:49,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 774 to 774. [2025-03-04 16:19:49,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 774 states, 774 states have (on average 1.2984496124031009) internal successors, (1005), 773 states have internal predecessors, (1005), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:49,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 774 states to 774 states and 1005 transitions. [2025-03-04 16:19:49,680 INFO L240 hiAutomatonCegarLoop]: Abstraction has 774 states and 1005 transitions. [2025-03-04 16:19:49,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:49,683 INFO L432 stractBuchiCegarLoop]: Abstraction has 774 states and 1005 transitions. [2025-03-04 16:19:49,684 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-04 16:19:49,684 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 774 states and 1005 transitions. [2025-03-04 16:19:49,686 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 741 [2025-03-04 16:19:49,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:49,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:49,687 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:49,687 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:49,688 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" [2025-03-04 16:19:49,688 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume !(0 == ~C_1_st~0);" [2025-03-04 16:19:49,688 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,688 INFO L85 PathProgramCache]: Analyzing trace with hash 1807779335, now seen corresponding path program 1 times [2025-03-04 16:19:49,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611312026] [2025-03-04 16:19:49,689 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:49,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,693 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:19:49,694 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:19:49,695 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,695 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,695 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:49,697 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:19:49,699 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:19:49,700 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,700 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,704 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:49,707 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,707 INFO L85 PathProgramCache]: Analyzing trace with hash 502320936, now seen corresponding path program 1 times [2025-03-04 16:19:49,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168139221] [2025-03-04 16:19:49,707 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:49,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,709 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-04 16:19:49,711 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-04 16:19:49,711 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,711 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,711 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:49,712 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-04 16:19:49,713 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-04 16:19:49,713 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,713 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,715 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:49,716 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,716 INFO L85 PathProgramCache]: Analyzing trace with hash 354398178, now seen corresponding path program 1 times [2025-03-04 16:19:49,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102947898] [2025-03-04 16:19:49,716 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:49,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,723 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-04 16:19:49,725 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-04 16:19:49,725 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,725 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:49,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:49,755 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:49,755 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102947898] [2025-03-04 16:19:49,755 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102947898] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:49,755 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:49,755 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:19:49,755 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2088637207] [2025-03-04 16:19:49,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:49,791 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:49,791 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:49,791 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:49,791 INFO L87 Difference]: Start difference. First operand 774 states and 1005 transitions. cyclomatic complexity: 234 Second operand has 3 states, 2 states have (on average 16.5) internal successors, (33), 3 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:49,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:49,818 INFO L93 Difference]: Finished difference Result 1251 states and 1599 transitions. [2025-03-04 16:19:49,818 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1251 states and 1599 transitions. [2025-03-04 16:19:49,822 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1209 [2025-03-04 16:19:49,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1251 states to 1251 states and 1599 transitions. [2025-03-04 16:19:49,826 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1251 [2025-03-04 16:19:49,827 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1251 [2025-03-04 16:19:49,827 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1251 states and 1599 transitions. [2025-03-04 16:19:49,828 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:49,828 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1251 states and 1599 transitions. [2025-03-04 16:19:49,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1251 states and 1599 transitions. [2025-03-04 16:19:49,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1251 to 1251. [2025-03-04 16:19:49,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1251 states, 1251 states have (on average 1.2781774580335732) internal successors, (1599), 1250 states have internal predecessors, (1599), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:49,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1251 states to 1251 states and 1599 transitions. [2025-03-04 16:19:49,842 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1251 states and 1599 transitions. [2025-03-04 16:19:49,842 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:49,844 INFO L432 stractBuchiCegarLoop]: Abstraction has 1251 states and 1599 transitions. [2025-03-04 16:19:49,844 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-04 16:19:49,844 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1251 states and 1599 transitions. [2025-03-04 16:19:49,847 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1209 [2025-03-04 16:19:49,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:49,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:49,848 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:49,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:49,848 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" [2025-03-04 16:19:49,848 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~C_1_st~0;havoc eval_#t~nondet7#1;eval_~tmp___1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___1~0#1);" [2025-03-04 16:19:49,850 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,850 INFO L85 PathProgramCache]: Analyzing trace with hash 1807779335, now seen corresponding path program 2 times [2025-03-04 16:19:49,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591680828] [2025-03-04 16:19:49,850 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:19:49,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,855 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:19:49,857 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:19:49,858 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:49,858 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,858 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:49,859 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:19:49,861 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:19:49,861 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,861 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,864 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:49,864 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,864 INFO L85 PathProgramCache]: Analyzing trace with hash -1607920039, now seen corresponding path program 1 times [2025-03-04 16:19:49,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,864 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504807799] [2025-03-04 16:19:49,865 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:49,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,866 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-04 16:19:49,867 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-04 16:19:49,867 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,867 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,867 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:49,867 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-04 16:19:49,870 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-04 16:19:49,870 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,870 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,871 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:49,872 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:49,872 INFO L85 PathProgramCache]: Analyzing trace with hash -1898558241, now seen corresponding path program 1 times [2025-03-04 16:19:49,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:49,872 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587860689] [2025-03-04 16:19:49,872 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:49,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:49,877 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-04 16:19:49,878 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-04 16:19:49,878 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,878 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,878 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:49,881 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-04 16:19:49,882 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-04 16:19:49,882 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:49,882 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:49,885 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:50,344 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:19:50,347 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:19:50,347 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:50,347 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:50,347 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:50,353 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:19:50,355 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:19:50,355 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:50,355 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:50,419 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 04.03 04:19:50 BoogieIcfgContainer [2025-03-04 16:19:50,419 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-04 16:19:50,420 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-04 16:19:50,420 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-04 16:19:50,420 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-04 16:19:50,420 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:19:48" (3/4) ... [2025-03-04 16:19:50,424 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-03-04 16:19:50,474 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-04 16:19:50,474 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-04 16:19:50,475 INFO L158 Benchmark]: Toolchain (without parser) took 3065.82ms. Allocated memory is still 167.8MB. Free memory was 123.1MB in the beginning and 58.6MB in the end (delta: 64.6MB). Peak memory consumption was 65.7MB. Max. memory is 16.1GB. [2025-03-04 16:19:50,475 INFO L158 Benchmark]: CDTParser took 0.21ms. Allocated memory is still 201.3MB. Free memory is still 116.2MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:19:50,475 INFO L158 Benchmark]: CACSL2BoogieTranslator took 231.03ms. Allocated memory is still 167.8MB. Free memory was 123.1MB in the beginning and 110.0MB in the end (delta: 13.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 16:19:50,475 INFO L158 Benchmark]: Boogie Procedure Inliner took 37.77ms. Allocated memory is still 167.8MB. Free memory was 110.0MB in the beginning and 107.9MB in the end (delta: 2.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 16:19:50,475 INFO L158 Benchmark]: Boogie Preprocessor took 23.12ms. Allocated memory is still 167.8MB. Free memory was 107.9MB in the beginning and 105.7MB in the end (delta: 2.1MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:19:50,477 INFO L158 Benchmark]: IcfgBuilder took 451.68ms. Allocated memory is still 167.8MB. Free memory was 105.7MB in the beginning and 82.7MB in the end (delta: 23.0MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2025-03-04 16:19:50,478 INFO L158 Benchmark]: BuchiAutomizer took 2264.27ms. Allocated memory is still 167.8MB. Free memory was 82.7MB in the beginning and 63.9MB in the end (delta: 18.8MB). Peak memory consumption was 15.4MB. Max. memory is 16.1GB. [2025-03-04 16:19:50,480 INFO L158 Benchmark]: Witness Printer took 54.36ms. Allocated memory is still 167.8MB. Free memory was 63.9MB in the beginning and 58.6MB in the end (delta: 5.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 16:19:50,480 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21ms. Allocated memory is still 201.3MB. Free memory is still 116.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 231.03ms. Allocated memory is still 167.8MB. Free memory was 123.1MB in the beginning and 110.0MB in the end (delta: 13.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 37.77ms. Allocated memory is still 167.8MB. Free memory was 110.0MB in the beginning and 107.9MB in the end (delta: 2.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 23.12ms. Allocated memory is still 167.8MB. Free memory was 107.9MB in the beginning and 105.7MB in the end (delta: 2.1MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 451.68ms. Allocated memory is still 167.8MB. Free memory was 105.7MB in the beginning and 82.7MB in the end (delta: 23.0MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 2264.27ms. Allocated memory is still 167.8MB. Free memory was 82.7MB in the beginning and 63.9MB in the end (delta: 18.8MB). Peak memory consumption was 15.4MB. Max. memory is 16.1GB. * Witness Printer took 54.36ms. Allocated memory is still 167.8MB. Free memory was 63.9MB in the beginning and 58.6MB in the end (delta: 5.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1251 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.1s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 1.5s. Construction of modules took 0.1s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 9 MinimizatonAttempts, 146 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1174 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1174 mSDsluCounter, 3062 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1639 mSDsCounter, 64 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 208 IncrementalHoareTripleChecker+Invalid, 272 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 64 mSolverCounterUnsat, 1423 mSDtfsCounter, 208 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 279]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int C_1_pc ; [L133] int C_1_st ; [L134] int C_1_i ; [L135] int C_1_ev ; [L136] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L500] int count ; [L501] int __retres2 ; [L505] num = 0 [L506] i = 0 [L507] max_loop = 2 [L509] timer = 0 [L510] P_1_pc = 0 [L511] C_1_pc = 0 [L513] count = 0 [L514] CALL init_model() [L493] P_1_i = 1 [L494] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L514] RET init_model() [L515] CALL start_simulation() [L431] int kernel_st ; [L432] int tmp ; [L433] int tmp___0 ; [L437] kernel_st = 0 [L438] FCALL update_channels() [L439] CALL init_threads() [L236] COND TRUE (int )P_1_i == 1 [L237] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L241] COND TRUE (int )C_1_i == 1 [L242] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L439] RET init_threads() [L440] FCALL fire_delta_events() [L441] CALL activate_threads() [L375] int tmp ; [L376] int tmp___0 ; [L377] int tmp___1 ; [L381] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L381] RET, EXPR is_P_1_triggered() [L381] tmp = is_P_1_triggered() [L383] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L389] CALL, EXPR is_C_1_triggered() [L196] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L209] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L219] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L221] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L389] RET, EXPR is_C_1_triggered() [L389] tmp___1 = is_C_1_triggered() [L391] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L441] RET activate_threads() [L442] FCALL reset_delta_events() [L445] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L448] kernel_st = 1 [L449] CALL eval() [L272] int tmp ; [L273] int tmp___0 ; [L274] int tmp___1 ; [L275] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L279] COND TRUE 1 [L282] CALL, EXPR exists_runnable_thread() [L251] int __retres1 ; [L254] COND TRUE (int )P_1_st == 0 [L255] __retres1 = 1 [L268] return (__retres1); [L282] RET, EXPR exists_runnable_thread() [L282] tmp___2 = exists_runnable_thread() [L284] COND TRUE \read(tmp___2) [L289] COND TRUE (int )P_1_st == 0 [L291] tmp = __VERIFIER_nondet_int() [L293] COND FALSE !(\read(tmp)) [L304] COND TRUE (int )C_1_st == 0 [L306] tmp___1 = __VERIFIER_nondet_int() [L308] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 279]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int C_1_pc ; [L133] int C_1_st ; [L134] int C_1_i ; [L135] int C_1_ev ; [L136] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L500] int count ; [L501] int __retres2 ; [L505] num = 0 [L506] i = 0 [L507] max_loop = 2 [L509] timer = 0 [L510] P_1_pc = 0 [L511] C_1_pc = 0 [L513] count = 0 [L514] CALL init_model() [L493] P_1_i = 1 [L494] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L514] RET init_model() [L515] CALL start_simulation() [L431] int kernel_st ; [L432] int tmp ; [L433] int tmp___0 ; [L437] kernel_st = 0 [L438] FCALL update_channels() [L439] CALL init_threads() [L236] COND TRUE (int )P_1_i == 1 [L237] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L241] COND TRUE (int )C_1_i == 1 [L242] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L439] RET init_threads() [L440] FCALL fire_delta_events() [L441] CALL activate_threads() [L375] int tmp ; [L376] int tmp___0 ; [L377] int tmp___1 ; [L381] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L381] RET, EXPR is_P_1_triggered() [L381] tmp = is_P_1_triggered() [L383] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L389] CALL, EXPR is_C_1_triggered() [L196] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L199] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L209] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L219] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L221] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L389] RET, EXPR is_C_1_triggered() [L389] tmp___1 = is_C_1_triggered() [L391] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L441] RET activate_threads() [L442] FCALL reset_delta_events() [L445] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L448] kernel_st = 1 [L449] CALL eval() [L272] int tmp ; [L273] int tmp___0 ; [L274] int tmp___1 ; [L275] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L279] COND TRUE 1 [L282] CALL, EXPR exists_runnable_thread() [L251] int __retres1 ; [L254] COND TRUE (int )P_1_st == 0 [L255] __retres1 = 1 [L268] return (__retres1); [L282] RET, EXPR exists_runnable_thread() [L282] tmp___2 = exists_runnable_thread() [L284] COND TRUE \read(tmp___2) [L289] COND TRUE (int )P_1_st == 0 [L291] tmp = __VERIFIER_nondet_int() [L293] COND FALSE !(\read(tmp)) [L304] COND TRUE (int )C_1_st == 0 [L306] tmp___1 = __VERIFIER_nondet_int() [L308] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-03-04 16:19:50,495 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)