./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 15:43:17,834 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 15:43:17,884 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-04 15:43:17,888 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 15:43:17,888 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 15:43:17,888 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 15:43:17,903 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 15:43:17,904 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 15:43:17,904 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 15:43:17,904 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 15:43:17,904 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 15:43:17,905 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 15:43:17,905 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 15:43:17,905 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 15:43:17,905 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 15:43:17,905 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 15:43:17,905 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 15:43:17,905 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 15:43:17,905 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 15:43:17,905 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 15:43:17,905 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 15:43:17,906 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 15:43:17,906 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-04 15:43:17,906 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 15:43:17,906 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-04 15:43:17,906 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 15:43:17,906 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 15:43:17,906 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 15:43:17,906 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 15:43:17,906 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 15:43:17,906 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-04 15:43:17,906 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 15:43:17,906 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 15:43:17,906 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 15:43:17,907 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 15:43:17,907 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 15:43:17,907 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 15:43:17,907 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 15:43:17,907 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 15:43:17,907 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 15:43:17,907 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2025-03-04 15:43:18,143 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 15:43:18,150 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 15:43:18,153 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 15:43:18,154 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 15:43:18,154 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 15:43:18,155 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2025-03-04 15:43:19,362 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c8547235b/0fd85d608cee45839227fe7946502d8f/FLAGa324416a7 [2025-03-04 15:43:19,562 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 15:43:19,562 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2025-03-04 15:43:19,567 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c8547235b/0fd85d608cee45839227fe7946502d8f/FLAGa324416a7 [2025-03-04 15:43:19,576 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c8547235b/0fd85d608cee45839227fe7946502d8f [2025-03-04 15:43:19,578 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 15:43:19,579 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 15:43:19,580 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 15:43:19,580 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 15:43:19,582 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 15:43:19,583 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,583 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6bb58253 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19, skipping insertion in model container [2025-03-04 15:43:19,584 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,592 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 15:43:19,698 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 15:43:19,707 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 15:43:19,722 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 15:43:19,733 INFO L204 MainTranslator]: Completed translation [2025-03-04 15:43:19,734 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19 WrapperNode [2025-03-04 15:43:19,734 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 15:43:19,735 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 15:43:19,735 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 15:43:19,735 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 15:43:19,739 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,743 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,758 INFO L138 Inliner]: procedures = 18, calls = 19, calls flagged for inlining = 7, calls inlined = 8, statements flattened = 69 [2025-03-04 15:43:19,759 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 15:43:19,759 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 15:43:19,759 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 15:43:19,759 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 15:43:19,765 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,765 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,766 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,782 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [2, 5]. 71 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0]. The 1 writes are split as follows [0, 1]. [2025-03-04 15:43:19,782 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,782 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,788 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,788 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,789 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,789 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,790 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 15:43:19,791 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 15:43:19,791 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 15:43:19,791 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 15:43:19,792 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19" (1/1) ... [2025-03-04 15:43:19,795 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:19,805 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:19,818 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:19,820 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 15:43:19,837 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-04 15:43:19,837 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-04 15:43:19,837 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-03-04 15:43:19,837 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-03-04 15:43:19,837 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-03-04 15:43:19,837 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-03-04 15:43:19,837 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 15:43:19,837 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 15:43:19,838 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-03-04 15:43:19,838 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-03-04 15:43:19,838 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-04 15:43:19,884 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 15:43:19,886 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 15:43:19,993 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L23: call ULTIMATE.dealloc(main_~#array~0#1.base, main_~#array~0#1.offset);havoc main_~#array~0#1.base, main_~#array~0#1.offset; [2025-03-04 15:43:20,000 INFO L? ?]: Removed 16 outVars from TransFormulas that were not future-live. [2025-03-04 15:43:20,000 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 15:43:20,008 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 15:43:20,008 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-04 15:43:20,009 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 03:43:20 BoogieIcfgContainer [2025-03-04 15:43:20,009 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 15:43:20,009 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 15:43:20,010 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 15:43:20,013 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 15:43:20,014 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 15:43:20,014 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 03:43:19" (1/3) ... [2025-03-04 15:43:20,014 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@506a8e5d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 03:43:20, skipping insertion in model container [2025-03-04 15:43:20,015 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 15:43:20,015 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:43:19" (2/3) ... [2025-03-04 15:43:20,015 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@506a8e5d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 03:43:20, skipping insertion in model container [2025-03-04 15:43:20,015 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 15:43:20,015 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 03:43:20" (3/3) ... [2025-03-04 15:43:20,016 INFO L363 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2025-03-04 15:43:20,051 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 15:43:20,052 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 15:43:20,052 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 15:43:20,052 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 15:43:20,052 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 15:43:20,052 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 15:43:20,052 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 15:43:20,052 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 15:43:20,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:20,069 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19 [2025-03-04 15:43:20,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:20,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:20,072 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:43:20,072 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-03-04 15:43:20,072 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 15:43:20,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:20,073 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19 [2025-03-04 15:43:20,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:20,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:20,073 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:43:20,073 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-03-04 15:43:20,076 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" [2025-03-04 15:43:20,076 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" [2025-03-04 15:43:20,079 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:20,079 INFO L85 PathProgramCache]: Analyzing trace with hash 1984, now seen corresponding path program 1 times [2025-03-04 15:43:20,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:20,087 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725491021] [2025-03-04 15:43:20,088 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:43:20,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:20,134 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:43:20,145 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:43:20,146 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:20,146 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:20,146 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:20,148 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:43:20,151 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:43:20,151 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:20,151 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:20,161 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:20,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:20,163 INFO L85 PathProgramCache]: Analyzing trace with hash 61, now seen corresponding path program 1 times [2025-03-04 15:43:20,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:20,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299418049] [2025-03-04 15:43:20,163 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:43:20,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:20,174 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-04 15:43:20,178 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-04 15:43:20,178 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:20,178 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:20,178 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:20,179 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-04 15:43:20,185 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-04 15:43:20,185 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:20,185 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:20,186 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:20,187 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:20,187 INFO L85 PathProgramCache]: Analyzing trace with hash 61534, now seen corresponding path program 1 times [2025-03-04 15:43:20,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:20,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1701612523] [2025-03-04 15:43:20,187 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:43:20,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:20,194 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:20,201 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:20,201 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:20,201 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:20,201 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:20,203 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:20,211 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:20,211 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:20,211 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:20,213 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:20,437 INFO L204 LassoAnalysis]: Preferences: [2025-03-04 15:43:20,437 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-04 15:43:20,437 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-04 15:43:20,438 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-04 15:43:20,438 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-03-04 15:43:20,438 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:20,438 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-04 15:43:20,438 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-04 15:43:20,438 INFO L132 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2025-03-04 15:43:20,438 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-04 15:43:20,438 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-04 15:43:20,448 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:43:20,452 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:43:20,464 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:43:20,466 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:43:20,468 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:43:20,470 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:43:20,472 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:43:20,592 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:43:20,594 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:43:20,596 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:43:20,598 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:43:20,600 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:43:20,748 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-04 15:43:20,751 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-03-04 15:43:20,752 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:20,752 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:20,754 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:20,756 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-03-04 15:43:20,757 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:20,768 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:20,768 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 15:43:20,768 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:20,768 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:20,768 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:20,771 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 15:43:20,771 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 15:43:20,773 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:20,779 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2025-03-04 15:43:20,779 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:20,780 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:20,781 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:20,783 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-03-04 15:43:20,783 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:20,793 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:20,794 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:20,794 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:20,794 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:20,796 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-04 15:43:20,796 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-04 15:43:20,800 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:20,806 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2025-03-04 15:43:20,806 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:20,806 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:20,808 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:20,809 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-03-04 15:43:20,810 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:20,820 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:20,821 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:20,821 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:20,821 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:20,822 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-04 15:43:20,822 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-04 15:43:20,825 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:20,831 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2025-03-04 15:43:20,831 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:20,831 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:20,833 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:20,834 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-03-04 15:43:20,836 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:20,846 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:20,846 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 15:43:20,846 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:20,846 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:20,846 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:20,847 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 15:43:20,847 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 15:43:20,848 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:20,854 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2025-03-04 15:43:20,854 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:20,855 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:20,856 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:20,858 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-03-04 15:43:20,861 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:20,871 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:20,871 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 15:43:20,871 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:20,871 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:20,871 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:20,873 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 15:43:20,873 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 15:43:20,874 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:20,880 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2025-03-04 15:43:20,881 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:20,881 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:20,883 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:20,884 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-03-04 15:43:20,885 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:20,895 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:20,895 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 15:43:20,895 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:20,895 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:20,895 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:20,896 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 15:43:20,896 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 15:43:20,897 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:20,902 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2025-03-04 15:43:20,903 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:20,903 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:20,905 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:20,906 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-03-04 15:43:20,907 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:20,917 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:20,918 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 15:43:20,918 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:20,918 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:20,918 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:20,918 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 15:43:20,919 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 15:43:20,920 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:20,925 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2025-03-04 15:43:20,926 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:20,926 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:20,927 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:20,928 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-03-04 15:43:20,929 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:20,938 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:20,938 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:20,938 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:20,939 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:20,940 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-04 15:43:20,940 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-04 15:43:20,943 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:20,949 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2025-03-04 15:43:20,950 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:20,950 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:20,951 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:20,953 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2025-03-04 15:43:20,954 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:20,964 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:20,964 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 15:43:20,964 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:20,964 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:20,964 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:20,965 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 15:43:20,965 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 15:43:20,966 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:20,972 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2025-03-04 15:43:20,972 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:20,972 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:20,974 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:20,975 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2025-03-04 15:43:20,977 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:20,986 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:20,987 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:20,987 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:20,987 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:20,988 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-04 15:43:20,989 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-04 15:43:20,991 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:20,997 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2025-03-04 15:43:20,997 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:20,997 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:20,999 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:21,000 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2025-03-04 15:43:21,002 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:21,011 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:21,011 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:21,011 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:21,012 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:21,013 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-04 15:43:21,013 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-04 15:43:21,016 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:21,022 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2025-03-04 15:43:21,022 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:21,022 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:21,024 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:21,025 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2025-03-04 15:43:21,026 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:21,036 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:21,037 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:21,037 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:21,037 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:21,038 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-04 15:43:21,038 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-04 15:43:21,041 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:21,047 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2025-03-04 15:43:21,047 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:21,047 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:21,049 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:21,050 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2025-03-04 15:43:21,052 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:21,061 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:21,062 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:21,062 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:21,062 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:21,063 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-04 15:43:21,063 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-04 15:43:21,066 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:21,072 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2025-03-04 15:43:21,072 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:21,072 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:21,074 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:21,075 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2025-03-04 15:43:21,077 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:21,087 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:21,087 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:21,087 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:21,087 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:21,090 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-04 15:43:21,090 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-04 15:43:21,092 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:43:21,098 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2025-03-04 15:43:21,098 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:21,098 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:21,100 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:21,100 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2025-03-04 15:43:21,101 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:43:21,111 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:43:21,111 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:43:21,111 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:43:21,111 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:43:21,115 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-04 15:43:21,116 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-04 15:43:21,125 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-03-04 15:43:21,149 INFO L443 ModelExtractionUtils]: Simplification made 14 calls to the SMT solver. [2025-03-04 15:43:21,150 INFO L444 ModelExtractionUtils]: 6 out of 16 variables were initially zero. Simplification set additionally 6 variables to zero. [2025-03-04 15:43:21,151 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:43:21,151 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:21,154 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:43:21,156 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2025-03-04 15:43:21,157 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-03-04 15:43:21,168 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-03-04 15:43:21,168 INFO L474 LassoAnalysis]: Proved termination. [2025-03-04 15:43:21,169 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~#array~0#1.offset, v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1, ULTIMATE.start_main_~i~0#1) = -1*ULTIMATE.start_main_~#array~0#1.offset + 1*v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2025-03-04 15:43:21,175 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2025-03-04 15:43:21,189 INFO L156 tatePredicateManager]: 4 out of 4 supporting invariants were superfluous and have been removed [2025-03-04 15:43:21,195 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: #length [2025-03-04 15:43:21,195 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#length,GLOBAL] [2025-03-04 15:43:21,196 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: ~#array~0!offset [2025-03-04 15:43:21,215 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:21,221 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:43:21,225 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:43:21,225 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,225 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:21,226 INFO L256 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-03-04 15:43:21,226 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:21,238 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-04 15:43:21,240 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-04 15:43:21,240 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,240 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:21,241 INFO L256 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-03-04 15:43:21,242 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:21,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:21,264 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2025-03-04 15:43:21,265 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:21,288 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 2 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 26 states and 36 transitions. Complement of second has 3 states. [2025-03-04 15:43:21,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 2 states 1 stem states 0 non-accepting loop states 1 accepting loop states [2025-03-04 15:43:21,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:21,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 3 transitions. [2025-03-04 15:43:21,301 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 3 transitions. Stem has 2 letters. Loop has 1 letters. [2025-03-04 15:43:21,301 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 15:43:21,303 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 3 transitions. Stem has 3 letters. Loop has 1 letters. [2025-03-04 15:43:21,303 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 15:43:21,303 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 3 transitions. Stem has 2 letters. Loop has 2 letters. [2025-03-04 15:43:21,303 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 15:43:21,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 36 transitions. [2025-03-04 15:43:21,305 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2025-03-04 15:43:21,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 23 states and 33 transitions. [2025-03-04 15:43:21,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2025-03-04 15:43:21,309 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2025-03-04 15:43:21,309 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 33 transitions. [2025-03-04 15:43:21,309 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:21,309 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23 states and 33 transitions. [2025-03-04 15:43:21,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 33 transitions. [2025-03-04 15:43:21,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 22. [2025-03-04 15:43:21,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.4090909090909092) internal successors, (31), 21 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:21,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 31 transitions. [2025-03-04 15:43:21,327 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22 states and 31 transitions. [2025-03-04 15:43:21,327 INFO L432 stractBuchiCegarLoop]: Abstraction has 22 states and 31 transitions. [2025-03-04 15:43:21,327 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 15:43:21,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 31 transitions. [2025-03-04 15:43:21,328 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2025-03-04 15:43:21,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:21,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:21,329 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2025-03-04 15:43:21,329 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:21,329 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" [2025-03-04 15:43:21,329 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" [2025-03-04 15:43:21,330 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:21,331 INFO L85 PathProgramCache]: Analyzing trace with hash 61533, now seen corresponding path program 1 times [2025-03-04 15:43:21,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:21,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1747474427] [2025-03-04 15:43:21,331 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:43:21,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:21,334 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:21,340 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:21,340 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,341 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:21,341 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:21,342 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:21,345 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:21,346 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,346 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:21,347 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:21,347 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:21,347 INFO L85 PathProgramCache]: Analyzing trace with hash 57553, now seen corresponding path program 1 times [2025-03-04 15:43:21,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:21,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694982224] [2025-03-04 15:43:21,347 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:43:21,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:21,350 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:21,353 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:21,354 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,354 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:21,354 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:21,355 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:21,358 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:21,359 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,359 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:21,360 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:21,360 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:21,361 INFO L85 PathProgramCache]: Analyzing trace with hash 1833157365, now seen corresponding path program 1 times [2025-03-04 15:43:21,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:21,361 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [328846263] [2025-03-04 15:43:21,361 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:43:21,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:21,363 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-04 15:43:21,369 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-04 15:43:21,370 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,370 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:21,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:21,434 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:21,434 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [328846263] [2025-03-04 15:43:21,434 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [328846263] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:43:21,434 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:43:21,435 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 15:43:21,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [530342532] [2025-03-04 15:43:21,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:43:21,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:21,472 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 15:43:21,472 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2025-03-04 15:43:21,476 INFO L87 Difference]: Start difference. First operand 22 states and 31 transitions. cyclomatic complexity: 12 Second operand has 4 states, 4 states have (on average 1.5) internal successors, (6), 4 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:21,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:21,506 INFO L93 Difference]: Finished difference Result 38 states and 45 transitions. [2025-03-04 15:43:21,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 45 transitions. [2025-03-04 15:43:21,507 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:21,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 28 states and 34 transitions. [2025-03-04 15:43:21,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2025-03-04 15:43:21,507 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2025-03-04 15:43:21,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 34 transitions. [2025-03-04 15:43:21,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:21,508 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28 states and 34 transitions. [2025-03-04 15:43:21,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 34 transitions. [2025-03-04 15:43:21,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 17. [2025-03-04 15:43:21,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.2352941176470589) internal successors, (21), 16 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:21,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 21 transitions. [2025-03-04 15:43:21,509 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17 states and 21 transitions. [2025-03-04 15:43:21,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 15:43:21,510 INFO L432 stractBuchiCegarLoop]: Abstraction has 17 states and 21 transitions. [2025-03-04 15:43:21,510 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 15:43:21,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 21 transitions. [2025-03-04 15:43:21,510 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:21,510 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:21,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:21,510 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2025-03-04 15:43:21,510 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:21,510 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:21,511 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:21,511 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:21,511 INFO L85 PathProgramCache]: Analyzing trace with hash 59135101, now seen corresponding path program 1 times [2025-03-04 15:43:21,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:21,511 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [712296336] [2025-03-04 15:43:21,511 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:43:21,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:21,528 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-03-04 15:43:21,534 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2025-03-04 15:43:21,540 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-03-04 15:43:21,540 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,540 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:21,540 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:21,541 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-03-04 15:43:21,551 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-03-04 15:43:21,553 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,553 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:21,554 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:21,557 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:21,557 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 2 times [2025-03-04 15:43:21,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:21,557 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628527488] [2025-03-04 15:43:21,557 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:43:21,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:21,560 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:21,567 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:21,568 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:43:21,568 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:21,568 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:21,569 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:21,571 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:21,574 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,575 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:21,576 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:21,576 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:21,576 INFO L85 PathProgramCache]: Analyzing trace with hash 757229033, now seen corresponding path program 1 times [2025-03-04 15:43:21,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:21,577 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467525160] [2025-03-04 15:43:21,577 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:43:21,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:21,581 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 15:43:21,589 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 15:43:21,589 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,589 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:21,657 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:21,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:21,657 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1467525160] [2025-03-04 15:43:21,657 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1467525160] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:21,657 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [545667446] [2025-03-04 15:43:21,657 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:43:21,657 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:21,657 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:21,659 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:21,660 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2025-03-04 15:43:21,687 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 15:43:21,696 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 15:43:21,696 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,696 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:21,696 INFO L256 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjuncts are in the unsatisfiable core [2025-03-04 15:43:21,697 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:21,733 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:21,733 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:21,762 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:21,762 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [545667446] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:21,762 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:21,762 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 9 [2025-03-04 15:43:21,762 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1234367632] [2025-03-04 15:43:21,763 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:21,798 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:21,798 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-04 15:43:21,799 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2025-03-04 15:43:21,799 INFO L87 Difference]: Start difference. First operand 17 states and 21 transitions. cyclomatic complexity: 7 Second operand has 10 states, 9 states have (on average 2.111111111111111) internal successors, (19), 10 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:21,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:21,860 INFO L93 Difference]: Finished difference Result 55 states and 66 transitions. [2025-03-04 15:43:21,860 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 66 transitions. [2025-03-04 15:43:21,861 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:21,861 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 41 states and 49 transitions. [2025-03-04 15:43:21,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2025-03-04 15:43:21,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2025-03-04 15:43:21,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41 states and 49 transitions. [2025-03-04 15:43:21,862 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:21,862 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41 states and 49 transitions. [2025-03-04 15:43:21,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states and 49 transitions. [2025-03-04 15:43:21,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 24. [2025-03-04 15:43:21,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 23 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:21,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 29 transitions. [2025-03-04 15:43:21,863 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 29 transitions. [2025-03-04 15:43:21,864 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-04 15:43:21,864 INFO L432 stractBuchiCegarLoop]: Abstraction has 24 states and 29 transitions. [2025-03-04 15:43:21,864 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 15:43:21,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 29 transitions. [2025-03-04 15:43:21,865 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:21,865 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:21,865 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:21,866 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1] [2025-03-04 15:43:21,866 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:21,866 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:21,866 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:21,866 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:21,866 INFO L85 PathProgramCache]: Analyzing trace with hash 2028855303, now seen corresponding path program 2 times [2025-03-04 15:43:21,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:21,866 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783568250] [2025-03-04 15:43:21,867 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:43:21,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:21,872 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 9 statements into 2 equivalence classes. [2025-03-04 15:43:21,887 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 9 of 9 statements. [2025-03-04 15:43:21,887 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:43:21,887 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:21,887 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:21,889 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-04 15:43:21,894 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-04 15:43:21,894 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,894 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:21,896 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:21,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:21,896 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 3 times [2025-03-04 15:43:21,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:21,896 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [83984885] [2025-03-04 15:43:21,896 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:21,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:21,898 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:21,899 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:21,900 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 15:43:21,900 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:21,900 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:21,900 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:21,901 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:21,901 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:21,901 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:21,904 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:21,904 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:21,904 INFO L85 PathProgramCache]: Analyzing trace with hash -1446398433, now seen corresponding path program 3 times [2025-03-04 15:43:21,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:21,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1489258893] [2025-03-04 15:43:21,904 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:21,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:21,909 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 12 statements into 3 equivalence classes. [2025-03-04 15:43:21,917 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 12 of 12 statements. [2025-03-04 15:43:21,918 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-03-04 15:43:21,918 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:22,008 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:22,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:22,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1489258893] [2025-03-04 15:43:22,008 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1489258893] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:22,009 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [134839326] [2025-03-04 15:43:22,009 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:22,009 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:22,009 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:22,010 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:22,011 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2025-03-04 15:43:22,036 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 12 statements into 3 equivalence classes. [2025-03-04 15:43:22,045 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 12 of 12 statements. [2025-03-04 15:43:22,045 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-03-04 15:43:22,045 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:22,046 INFO L256 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 8 conjuncts are in the unsatisfiable core [2025-03-04 15:43:22,046 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:22,108 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:22,108 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:22,141 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:22,141 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [134839326] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:22,141 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:22,141 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 12 [2025-03-04 15:43:22,141 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054694201] [2025-03-04 15:43:22,141 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:22,176 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:22,176 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-04 15:43:22,176 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=109, Unknown=0, NotChecked=0, Total=156 [2025-03-04 15:43:22,177 INFO L87 Difference]: Start difference. First operand 24 states and 29 transitions. cyclomatic complexity: 8 Second operand has 13 states, 12 states have (on average 2.1666666666666665) internal successors, (26), 13 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:22,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:22,267 INFO L93 Difference]: Finished difference Result 80 states and 95 transitions. [2025-03-04 15:43:22,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80 states and 95 transitions. [2025-03-04 15:43:22,269 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:22,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80 states to 54 states and 64 transitions. [2025-03-04 15:43:22,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2025-03-04 15:43:22,269 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2025-03-04 15:43:22,269 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54 states and 64 transitions. [2025-03-04 15:43:22,270 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:22,270 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54 states and 64 transitions. [2025-03-04 15:43:22,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states and 64 transitions. [2025-03-04 15:43:22,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 31. [2025-03-04 15:43:22,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.1935483870967742) internal successors, (37), 30 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:22,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 37 transitions. [2025-03-04 15:43:22,275 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31 states and 37 transitions. [2025-03-04 15:43:22,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-04 15:43:22,276 INFO L432 stractBuchiCegarLoop]: Abstraction has 31 states and 37 transitions. [2025-03-04 15:43:22,276 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 15:43:22,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 37 transitions. [2025-03-04 15:43:22,276 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:22,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:22,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:22,277 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 1, 1, 1] [2025-03-04 15:43:22,277 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:22,277 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:22,277 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:22,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:22,277 INFO L85 PathProgramCache]: Analyzing trace with hash -789647043, now seen corresponding path program 4 times [2025-03-04 15:43:22,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:22,277 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1868794363] [2025-03-04 15:43:22,277 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:43:22,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:22,282 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 13 statements into 2 equivalence classes. [2025-03-04 15:43:22,291 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 13 of 13 statements. [2025-03-04 15:43:22,291 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:43:22,291 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:22,291 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:22,293 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-03-04 15:43:22,302 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-03-04 15:43:22,302 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:22,303 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:22,305 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:22,305 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:22,305 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 4 times [2025-03-04 15:43:22,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:22,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958371816] [2025-03-04 15:43:22,305 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:43:22,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:22,307 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-03-04 15:43:22,309 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:22,309 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:43:22,309 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:22,309 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:22,309 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:22,310 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:22,310 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:22,311 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:22,311 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:22,312 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:22,312 INFO L85 PathProgramCache]: Analyzing trace with hash -839151319, now seen corresponding path program 5 times [2025-03-04 15:43:22,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:22,312 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001386983] [2025-03-04 15:43:22,312 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:22,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:22,317 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 16 statements into 4 equivalence classes. [2025-03-04 15:43:22,326 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 16 of 16 statements. [2025-03-04 15:43:22,327 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-03-04 15:43:22,327 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:22,416 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:22,416 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:22,417 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2001386983] [2025-03-04 15:43:22,417 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2001386983] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:22,417 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [740995095] [2025-03-04 15:43:22,417 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:22,417 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:22,417 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:22,419 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:22,420 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2025-03-04 15:43:22,448 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 16 statements into 4 equivalence classes. [2025-03-04 15:43:22,462 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 16 of 16 statements. [2025-03-04 15:43:22,463 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-03-04 15:43:22,463 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:22,463 INFO L256 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 10 conjuncts are in the unsatisfiable core [2025-03-04 15:43:22,464 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:22,535 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:22,535 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:22,577 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:22,577 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [740995095] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:22,577 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:22,577 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 13 [2025-03-04 15:43:22,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [733449962] [2025-03-04 15:43:22,577 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:22,611 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:22,611 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2025-03-04 15:43:22,612 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2025-03-04 15:43:22,612 INFO L87 Difference]: Start difference. First operand 31 states and 37 transitions. cyclomatic complexity: 9 Second operand has 14 states, 13 states have (on average 2.076923076923077) internal successors, (27), 14 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:22,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:22,726 INFO L93 Difference]: Finished difference Result 105 states and 124 transitions. [2025-03-04 15:43:22,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 124 transitions. [2025-03-04 15:43:22,727 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:22,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 67 states and 79 transitions. [2025-03-04 15:43:22,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63 [2025-03-04 15:43:22,728 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63 [2025-03-04 15:43:22,728 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 79 transitions. [2025-03-04 15:43:22,728 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:22,728 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67 states and 79 transitions. [2025-03-04 15:43:22,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 79 transitions. [2025-03-04 15:43:22,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 38. [2025-03-04 15:43:22,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.1842105263157894) internal successors, (45), 37 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:22,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 45 transitions. [2025-03-04 15:43:22,729 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38 states and 45 transitions. [2025-03-04 15:43:22,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 15:43:22,730 INFO L432 stractBuchiCegarLoop]: Abstraction has 38 states and 45 transitions. [2025-03-04 15:43:22,730 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 15:43:22,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 45 transitions. [2025-03-04 15:43:22,730 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:22,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:22,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:22,731 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 1, 1, 1] [2025-03-04 15:43:22,731 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:22,731 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:22,731 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:22,731 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:22,731 INFO L85 PathProgramCache]: Analyzing trace with hash 464653639, now seen corresponding path program 6 times [2025-03-04 15:43:22,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:22,731 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1696216165] [2025-03-04 15:43:22,732 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:43:22,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:22,738 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 17 statements into 4 equivalence classes. [2025-03-04 15:43:22,758 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) and asserted 17 of 17 statements. [2025-03-04 15:43:22,759 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2025-03-04 15:43:22,759 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:22,759 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:22,760 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes. [2025-03-04 15:43:22,767 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements. [2025-03-04 15:43:22,767 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:22,767 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:22,769 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:22,769 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:22,769 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 5 times [2025-03-04 15:43:22,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:22,769 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107591155] [2025-03-04 15:43:22,769 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:22,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:22,771 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:22,771 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:22,771 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:43:22,772 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:22,772 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:22,772 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:22,773 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:22,773 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:22,773 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:22,773 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:22,774 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:22,774 INFO L85 PathProgramCache]: Analyzing trace with hash -183009057, now seen corresponding path program 7 times [2025-03-04 15:43:22,774 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:22,774 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612541930] [2025-03-04 15:43:22,774 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:22,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:22,780 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-03-04 15:43:22,798 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-03-04 15:43:22,798 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:22,798 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:22,934 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 12 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:22,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:22,934 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612541930] [2025-03-04 15:43:22,935 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [612541930] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:22,935 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [735146437] [2025-03-04 15:43:22,935 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:22,935 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:22,935 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:22,937 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:22,942 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2025-03-04 15:43:22,974 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-03-04 15:43:22,986 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-03-04 15:43:22,986 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:22,986 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:22,987 INFO L256 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 12 conjuncts are in the unsatisfiable core [2025-03-04 15:43:22,988 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:23,084 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 22 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:23,084 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:23,144 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 22 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:23,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [735146437] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:23,144 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:23,144 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 18 [2025-03-04 15:43:23,145 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462289843] [2025-03-04 15:43:23,145 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:23,180 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:23,181 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2025-03-04 15:43:23,181 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=249, Unknown=0, NotChecked=0, Total=342 [2025-03-04 15:43:23,181 INFO L87 Difference]: Start difference. First operand 38 states and 45 transitions. cyclomatic complexity: 10 Second operand has 19 states, 18 states have (on average 2.2222222222222223) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:23,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:23,346 INFO L93 Difference]: Finished difference Result 130 states and 153 transitions. [2025-03-04 15:43:23,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130 states and 153 transitions. [2025-03-04 15:43:23,347 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:23,347 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130 states to 80 states and 94 transitions. [2025-03-04 15:43:23,347 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75 [2025-03-04 15:43:23,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75 [2025-03-04 15:43:23,348 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 94 transitions. [2025-03-04 15:43:23,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:23,348 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80 states and 94 transitions. [2025-03-04 15:43:23,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 94 transitions. [2025-03-04 15:43:23,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 45. [2025-03-04 15:43:23,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.1777777777777778) internal successors, (53), 44 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:23,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 53 transitions. [2025-03-04 15:43:23,354 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 53 transitions. [2025-03-04 15:43:23,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2025-03-04 15:43:23,355 INFO L432 stractBuchiCegarLoop]: Abstraction has 45 states and 53 transitions. [2025-03-04 15:43:23,355 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-04 15:43:23,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 53 transitions. [2025-03-04 15:43:23,357 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:23,357 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:23,357 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:23,357 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 1, 1, 1] [2025-03-04 15:43:23,357 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:23,358 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:23,358 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:23,358 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:23,358 INFO L85 PathProgramCache]: Analyzing trace with hash 1289141757, now seen corresponding path program 8 times [2025-03-04 15:43:23,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:23,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005776478] [2025-03-04 15:43:23,358 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:43:23,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:23,366 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 21 statements into 2 equivalence classes. [2025-03-04 15:43:23,389 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 21 of 21 statements. [2025-03-04 15:43:23,391 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:43:23,391 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:23,391 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:23,394 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-04 15:43:23,406 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-04 15:43:23,408 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:23,408 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:23,411 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:23,413 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:23,413 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 6 times [2025-03-04 15:43:23,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:23,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863386822] [2025-03-04 15:43:23,413 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:43:23,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:23,414 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:23,415 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:23,417 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 15:43:23,417 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:23,417 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:23,417 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:23,418 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:23,420 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:23,420 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:23,420 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:23,421 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:23,421 INFO L85 PathProgramCache]: Analyzing trace with hash -775451543, now seen corresponding path program 9 times [2025-03-04 15:43:23,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:23,421 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803456450] [2025-03-04 15:43:23,421 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:23,421 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:23,427 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 24 statements into 6 equivalence classes. [2025-03-04 15:43:23,466 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 15:43:23,467 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-03-04 15:43:23,467 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:23,627 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 22 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:23,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:23,627 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1803456450] [2025-03-04 15:43:23,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1803456450] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:23,627 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1427899637] [2025-03-04 15:43:23,627 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:23,627 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:23,627 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:23,629 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:23,630 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2025-03-04 15:43:23,661 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 24 statements into 6 equivalence classes. [2025-03-04 15:43:23,684 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 15:43:23,685 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-03-04 15:43:23,685 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:23,685 INFO L256 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 14 conjuncts are in the unsatisfiable core [2025-03-04 15:43:23,686 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:23,826 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 35 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:23,826 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:23,903 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 35 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:23,903 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1427899637] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:23,903 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:23,903 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 21 [2025-03-04 15:43:23,903 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080899882] [2025-03-04 15:43:23,903 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:23,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:23,939 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-03-04 15:43:23,939 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=340, Unknown=0, NotChecked=0, Total=462 [2025-03-04 15:43:23,939 INFO L87 Difference]: Start difference. First operand 45 states and 53 transitions. cyclomatic complexity: 11 Second operand has 22 states, 21 states have (on average 2.238095238095238) internal successors, (47), 22 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:24,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:24,128 INFO L93 Difference]: Finished difference Result 155 states and 182 transitions. [2025-03-04 15:43:24,128 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155 states and 182 transitions. [2025-03-04 15:43:24,129 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:24,130 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155 states to 93 states and 109 transitions. [2025-03-04 15:43:24,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 87 [2025-03-04 15:43:24,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 87 [2025-03-04 15:43:24,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93 states and 109 transitions. [2025-03-04 15:43:24,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:24,130 INFO L218 hiAutomatonCegarLoop]: Abstraction has 93 states and 109 transitions. [2025-03-04 15:43:24,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states and 109 transitions. [2025-03-04 15:43:24,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 52. [2025-03-04 15:43:24,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.1730769230769231) internal successors, (61), 51 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:24,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 61 transitions. [2025-03-04 15:43:24,134 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 61 transitions. [2025-03-04 15:43:24,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2025-03-04 15:43:24,135 INFO L432 stractBuchiCegarLoop]: Abstraction has 52 states and 61 transitions. [2025-03-04 15:43:24,135 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-04 15:43:24,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 61 transitions. [2025-03-04 15:43:24,135 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:24,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:24,135 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:24,136 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 1, 1, 1] [2025-03-04 15:43:24,136 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:24,136 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:24,136 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:24,136 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:24,136 INFO L85 PathProgramCache]: Analyzing trace with hash -1891169657, now seen corresponding path program 10 times [2025-03-04 15:43:24,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:24,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969469054] [2025-03-04 15:43:24,136 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:43:24,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:24,141 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 25 statements into 2 equivalence classes. [2025-03-04 15:43:24,154 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 25 of 25 statements. [2025-03-04 15:43:24,155 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:43:24,155 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:24,155 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:24,156 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 25 statements into 1 equivalence classes. [2025-03-04 15:43:24,168 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 25 of 25 statements. [2025-03-04 15:43:24,169 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:24,169 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:24,171 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:24,171 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:24,172 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 7 times [2025-03-04 15:43:24,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:24,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45425402] [2025-03-04 15:43:24,172 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:24,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:24,173 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:24,174 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:24,174 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:24,174 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:24,174 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:24,175 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:24,175 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:24,175 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:24,175 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:24,176 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:24,176 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:24,177 INFO L85 PathProgramCache]: Analyzing trace with hash 1545763743, now seen corresponding path program 11 times [2025-03-04 15:43:24,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:24,177 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1132489888] [2025-03-04 15:43:24,177 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:24,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:24,181 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 28 statements into 7 equivalence classes. [2025-03-04 15:43:24,197 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 15:43:24,197 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2025-03-04 15:43:24,197 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:24,360 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 51 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:24,360 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:24,360 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1132489888] [2025-03-04 15:43:24,360 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1132489888] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:24,360 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1413795084] [2025-03-04 15:43:24,360 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:24,361 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:24,361 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:24,362 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:24,364 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2025-03-04 15:43:24,395 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 28 statements into 7 equivalence classes. [2025-03-04 15:43:24,427 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 15:43:24,427 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2025-03-04 15:43:24,427 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:24,428 INFO L256 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 17 conjuncts are in the unsatisfiable core [2025-03-04 15:43:24,429 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:24,656 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 45 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:24,656 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:24,856 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 45 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:24,857 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1413795084] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:24,858 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:24,858 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 16] total 38 [2025-03-04 15:43:24,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479538808] [2025-03-04 15:43:24,858 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:24,891 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:24,891 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2025-03-04 15:43:24,892 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=265, Invalid=1217, Unknown=0, NotChecked=0, Total=1482 [2025-03-04 15:43:24,893 INFO L87 Difference]: Start difference. First operand 52 states and 61 transitions. cyclomatic complexity: 12 Second operand has 39 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 39 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:25,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:25,252 INFO L93 Difference]: Finished difference Result 217 states and 253 transitions. [2025-03-04 15:43:25,252 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217 states and 253 transitions. [2025-03-04 15:43:25,254 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:25,254 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217 states to 106 states and 124 transitions. [2025-03-04 15:43:25,254 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99 [2025-03-04 15:43:25,254 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99 [2025-03-04 15:43:25,254 INFO L73 IsDeterministic]: Start isDeterministic. Operand 106 states and 124 transitions. [2025-03-04 15:43:25,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:25,255 INFO L218 hiAutomatonCegarLoop]: Abstraction has 106 states and 124 transitions. [2025-03-04 15:43:25,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states and 124 transitions. [2025-03-04 15:43:25,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 59. [2025-03-04 15:43:25,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.1694915254237288) internal successors, (69), 58 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:25,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 69 transitions. [2025-03-04 15:43:25,257 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59 states and 69 transitions. [2025-03-04 15:43:25,261 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2025-03-04 15:43:25,262 INFO L432 stractBuchiCegarLoop]: Abstraction has 59 states and 69 transitions. [2025-03-04 15:43:25,262 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-04 15:43:25,262 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 69 transitions. [2025-03-04 15:43:25,262 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:25,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:25,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:25,263 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 6, 1, 1, 1] [2025-03-04 15:43:25,263 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:25,263 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:25,263 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:25,264 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:25,264 INFO L85 PathProgramCache]: Analyzing trace with hash 861518525, now seen corresponding path program 12 times [2025-03-04 15:43:25,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:25,264 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969376197] [2025-03-04 15:43:25,264 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:43:25,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:25,272 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 29 statements into 7 equivalence classes. [2025-03-04 15:43:25,317 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) and asserted 29 of 29 statements. [2025-03-04 15:43:25,317 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2025-03-04 15:43:25,317 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:25,317 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:25,319 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-04 15:43:25,335 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-04 15:43:25,335 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:25,335 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:25,341 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:25,341 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:25,341 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 8 times [2025-03-04 15:43:25,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:25,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274127419] [2025-03-04 15:43:25,342 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:43:25,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:25,344 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:25,345 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:25,345 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:43:25,345 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:25,345 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:25,346 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:25,346 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:25,346 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:25,346 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:25,347 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:25,347 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:25,348 INFO L85 PathProgramCache]: Analyzing trace with hash -1226156119, now seen corresponding path program 13 times [2025-03-04 15:43:25,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:25,348 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427423153] [2025-03-04 15:43:25,348 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:25,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:25,352 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-03-04 15:43:25,362 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-03-04 15:43:25,362 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:25,362 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:25,586 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 51 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:25,587 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:25,587 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427423153] [2025-03-04 15:43:25,587 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [427423153] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:25,587 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2006362093] [2025-03-04 15:43:25,587 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:25,587 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:25,587 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:25,589 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:25,590 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2025-03-04 15:43:25,624 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-03-04 15:43:25,640 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-03-04 15:43:25,640 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:25,640 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:25,641 INFO L256 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 18 conjuncts are in the unsatisfiable core [2025-03-04 15:43:25,642 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:25,799 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 70 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:25,799 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:25,913 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 70 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:25,913 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2006362093] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:25,913 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:25,913 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 27 [2025-03-04 15:43:25,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [764350659] [2025-03-04 15:43:25,913 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:25,939 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:25,940 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2025-03-04 15:43:25,940 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=564, Unknown=0, NotChecked=0, Total=756 [2025-03-04 15:43:25,940 INFO L87 Difference]: Start difference. First operand 59 states and 69 transitions. cyclomatic complexity: 13 Second operand has 28 states, 27 states have (on average 2.259259259259259) internal successors, (61), 28 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:26,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:26,151 INFO L93 Difference]: Finished difference Result 205 states and 240 transitions. [2025-03-04 15:43:26,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 205 states and 240 transitions. [2025-03-04 15:43:26,152 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:26,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 205 states to 119 states and 139 transitions. [2025-03-04 15:43:26,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 111 [2025-03-04 15:43:26,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 111 [2025-03-04 15:43:26,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119 states and 139 transitions. [2025-03-04 15:43:26,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:26,156 INFO L218 hiAutomatonCegarLoop]: Abstraction has 119 states and 139 transitions. [2025-03-04 15:43:26,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states and 139 transitions. [2025-03-04 15:43:26,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 66. [2025-03-04 15:43:26,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.1666666666666667) internal successors, (77), 65 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:26,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 77 transitions. [2025-03-04 15:43:26,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66 states and 77 transitions. [2025-03-04 15:43:26,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2025-03-04 15:43:26,163 INFO L432 stractBuchiCegarLoop]: Abstraction has 66 states and 77 transitions. [2025-03-04 15:43:26,163 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-04 15:43:26,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 77 transitions. [2025-03-04 15:43:26,163 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:26,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:26,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:26,164 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 7, 1, 1, 1] [2025-03-04 15:43:26,164 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:26,164 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:26,164 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:26,164 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:26,164 INFO L85 PathProgramCache]: Analyzing trace with hash -1810835513, now seen corresponding path program 14 times [2025-03-04 15:43:26,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:26,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1868854096] [2025-03-04 15:43:26,164 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:43:26,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:26,173 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 33 statements into 2 equivalence classes. [2025-03-04 15:43:26,201 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 33 of 33 statements. [2025-03-04 15:43:26,201 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:43:26,201 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:26,201 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:26,203 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-03-04 15:43:26,218 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-03-04 15:43:26,218 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:26,218 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:26,221 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:26,221 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:26,221 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 9 times [2025-03-04 15:43:26,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:26,221 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053901385] [2025-03-04 15:43:26,221 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:26,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:26,223 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:26,224 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:26,224 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 15:43:26,224 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:26,224 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:26,224 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:26,225 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:26,225 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:26,225 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:26,226 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:26,226 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:26,226 INFO L85 PathProgramCache]: Analyzing trace with hash -1811503521, now seen corresponding path program 15 times [2025-03-04 15:43:26,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:26,226 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119314741] [2025-03-04 15:43:26,226 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:26,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:26,231 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 36 statements into 9 equivalence classes. [2025-03-04 15:43:26,270 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) and asserted 36 of 36 statements. [2025-03-04 15:43:26,270 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2025-03-04 15:43:26,270 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:26,542 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 70 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:26,542 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:26,542 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [119314741] [2025-03-04 15:43:26,542 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [119314741] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:26,542 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1661972053] [2025-03-04 15:43:26,542 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:26,542 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:26,543 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:26,545 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:26,546 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2025-03-04 15:43:26,586 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 36 statements into 9 equivalence classes. [2025-03-04 15:43:26,630 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) and asserted 36 of 36 statements. [2025-03-04 15:43:26,630 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2025-03-04 15:43:26,630 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:26,632 INFO L256 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 20 conjuncts are in the unsatisfiable core [2025-03-04 15:43:26,632 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:26,823 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 92 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:26,823 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:26,960 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 92 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:26,960 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1661972053] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:26,960 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:26,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 30 [2025-03-04 15:43:26,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988890456] [2025-03-04 15:43:26,960 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:26,988 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:26,989 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2025-03-04 15:43:26,989 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=233, Invalid=697, Unknown=0, NotChecked=0, Total=930 [2025-03-04 15:43:26,989 INFO L87 Difference]: Start difference. First operand 66 states and 77 transitions. cyclomatic complexity: 14 Second operand has 31 states, 30 states have (on average 2.2666666666666666) internal successors, (68), 31 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:27,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:27,226 INFO L93 Difference]: Finished difference Result 230 states and 269 transitions. [2025-03-04 15:43:27,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 269 transitions. [2025-03-04 15:43:27,228 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:27,228 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 132 states and 154 transitions. [2025-03-04 15:43:27,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123 [2025-03-04 15:43:27,229 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123 [2025-03-04 15:43:27,229 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132 states and 154 transitions. [2025-03-04 15:43:27,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:27,229 INFO L218 hiAutomatonCegarLoop]: Abstraction has 132 states and 154 transitions. [2025-03-04 15:43:27,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states and 154 transitions. [2025-03-04 15:43:27,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 73. [2025-03-04 15:43:27,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.1643835616438356) internal successors, (85), 72 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:27,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 85 transitions. [2025-03-04 15:43:27,234 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73 states and 85 transitions. [2025-03-04 15:43:27,235 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2025-03-04 15:43:27,235 INFO L432 stractBuchiCegarLoop]: Abstraction has 73 states and 85 transitions. [2025-03-04 15:43:27,235 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-04 15:43:27,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 85 transitions. [2025-03-04 15:43:27,237 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:27,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:27,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:27,238 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 8, 1, 1, 1] [2025-03-04 15:43:27,238 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:27,238 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:27,238 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:27,238 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:27,238 INFO L85 PathProgramCache]: Analyzing trace with hash 2073290621, now seen corresponding path program 16 times [2025-03-04 15:43:27,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:27,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752132314] [2025-03-04 15:43:27,239 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:43:27,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:27,246 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 37 statements into 2 equivalence classes. [2025-03-04 15:43:27,270 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 37 of 37 statements. [2025-03-04 15:43:27,270 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:43:27,270 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:27,270 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:27,273 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-03-04 15:43:27,290 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-03-04 15:43:27,291 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:27,291 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:27,296 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:27,296 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:27,296 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 10 times [2025-03-04 15:43:27,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:27,296 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798686960] [2025-03-04 15:43:27,296 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:43:27,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:27,301 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-03-04 15:43:27,302 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:27,302 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:43:27,302 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:27,302 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:27,302 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:27,303 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:27,303 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:27,303 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:27,304 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:27,304 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:27,304 INFO L85 PathProgramCache]: Analyzing trace with hash -523767063, now seen corresponding path program 17 times [2025-03-04 15:43:27,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:27,304 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853841611] [2025-03-04 15:43:27,304 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:27,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:27,310 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 40 statements into 10 equivalence classes. [2025-03-04 15:43:27,329 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 15:43:27,329 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2025-03-04 15:43:27,329 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:27,647 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 108 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:27,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:27,648 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1853841611] [2025-03-04 15:43:27,648 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1853841611] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:27,648 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [507486556] [2025-03-04 15:43:27,648 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:27,648 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:27,648 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:27,650 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:27,652 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2025-03-04 15:43:27,694 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 40 statements into 10 equivalence classes. [2025-03-04 15:43:27,745 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 15:43:27,745 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2025-03-04 15:43:27,745 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:27,746 INFO L256 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 22 conjuncts are in the unsatisfiable core [2025-03-04 15:43:27,748 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:28,103 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 117 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:28,103 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:28,324 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 117 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:28,324 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [507486556] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:28,324 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:28,324 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21, 21] total 42 [2025-03-04 15:43:28,324 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2080116498] [2025-03-04 15:43:28,324 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:28,352 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:28,352 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2025-03-04 15:43:28,353 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=318, Invalid=1488, Unknown=0, NotChecked=0, Total=1806 [2025-03-04 15:43:28,353 INFO L87 Difference]: Start difference. First operand 73 states and 85 transitions. cyclomatic complexity: 15 Second operand has 43 states, 42 states have (on average 1.9285714285714286) internal successors, (81), 43 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:29,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:29,141 INFO L93 Difference]: Finished difference Result 310 states and 361 transitions. [2025-03-04 15:43:29,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 310 states and 361 transitions. [2025-03-04 15:43:29,142 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:29,143 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 310 states to 145 states and 169 transitions. [2025-03-04 15:43:29,143 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 135 [2025-03-04 15:43:29,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 135 [2025-03-04 15:43:29,143 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145 states and 169 transitions. [2025-03-04 15:43:29,143 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:29,143 INFO L218 hiAutomatonCegarLoop]: Abstraction has 145 states and 169 transitions. [2025-03-04 15:43:29,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states and 169 transitions. [2025-03-04 15:43:29,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 80. [2025-03-04 15:43:29,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.1625) internal successors, (93), 79 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:29,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 93 transitions. [2025-03-04 15:43:29,160 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 93 transitions. [2025-03-04 15:43:29,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2025-03-04 15:43:29,162 INFO L432 stractBuchiCegarLoop]: Abstraction has 80 states and 93 transitions. [2025-03-04 15:43:29,163 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-04 15:43:29,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 93 transitions. [2025-03-04 15:43:29,163 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:29,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:29,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:29,164 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 9, 9, 1, 1, 1] [2025-03-04 15:43:29,165 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:29,166 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:29,166 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:29,166 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:29,166 INFO L85 PathProgramCache]: Analyzing trace with hash -814516985, now seen corresponding path program 18 times [2025-03-04 15:43:29,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:29,166 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413824112] [2025-03-04 15:43:29,166 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:43:29,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:29,173 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 41 statements into 10 equivalence classes. [2025-03-04 15:43:29,215 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 15:43:29,215 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2025-03-04 15:43:29,215 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:29,215 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:29,218 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 15:43:29,236 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 15:43:29,237 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:29,237 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:29,240 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:29,240 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:29,240 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 11 times [2025-03-04 15:43:29,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:29,240 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459944006] [2025-03-04 15:43:29,240 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:29,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:29,242 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:29,242 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:29,243 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:43:29,243 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:29,243 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:29,243 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:29,243 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:29,243 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:29,243 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:29,244 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:29,245 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:29,245 INFO L85 PathProgramCache]: Analyzing trace with hash 1289748767, now seen corresponding path program 19 times [2025-03-04 15:43:29,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:29,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112406879] [2025-03-04 15:43:29,245 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:29,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:29,252 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 15:43:29,259 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 15:43:29,259 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:29,259 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:29,565 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 117 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:29,565 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:29,565 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2112406879] [2025-03-04 15:43:29,565 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2112406879] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:29,565 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [416145337] [2025-03-04 15:43:29,566 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:29,566 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:29,566 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:29,568 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:29,569 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2025-03-04 15:43:29,614 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 15:43:29,636 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 15:43:29,637 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:29,637 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:29,638 INFO L256 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 24 conjuncts are in the unsatisfiable core [2025-03-04 15:43:29,639 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:29,899 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 145 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:29,900 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:30,083 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 145 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:30,084 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [416145337] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:30,084 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:30,084 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23] total 36 [2025-03-04 15:43:30,084 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [797716371] [2025-03-04 15:43:30,084 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:30,109 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:30,110 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2025-03-04 15:43:30,110 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=327, Invalid=1005, Unknown=0, NotChecked=0, Total=1332 [2025-03-04 15:43:30,110 INFO L87 Difference]: Start difference. First operand 80 states and 93 transitions. cyclomatic complexity: 16 Second operand has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 37 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:30,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:30,425 INFO L93 Difference]: Finished difference Result 280 states and 327 transitions. [2025-03-04 15:43:30,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 280 states and 327 transitions. [2025-03-04 15:43:30,427 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:30,428 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 280 states to 158 states and 184 transitions. [2025-03-04 15:43:30,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147 [2025-03-04 15:43:30,428 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147 [2025-03-04 15:43:30,428 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 184 transitions. [2025-03-04 15:43:30,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:30,428 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158 states and 184 transitions. [2025-03-04 15:43:30,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 184 transitions. [2025-03-04 15:43:30,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 87. [2025-03-04 15:43:30,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 87 states have (on average 1.160919540229885) internal successors, (101), 86 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:30,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 101 transitions. [2025-03-04 15:43:30,436 INFO L240 hiAutomatonCegarLoop]: Abstraction has 87 states and 101 transitions. [2025-03-04 15:43:30,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2025-03-04 15:43:30,436 INFO L432 stractBuchiCegarLoop]: Abstraction has 87 states and 101 transitions. [2025-03-04 15:43:30,437 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-04 15:43:30,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 101 transitions. [2025-03-04 15:43:30,437 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:30,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:30,437 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:30,438 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 10, 1, 1, 1] [2025-03-04 15:43:30,438 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:30,438 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:30,438 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:30,439 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:30,439 INFO L85 PathProgramCache]: Analyzing trace with hash 396444733, now seen corresponding path program 20 times [2025-03-04 15:43:30,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:30,439 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498025420] [2025-03-04 15:43:30,439 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:43:30,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:30,447 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 45 statements into 2 equivalence classes. [2025-03-04 15:43:30,482 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 45 of 45 statements. [2025-03-04 15:43:30,482 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:43:30,482 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:30,482 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:30,485 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 45 statements into 1 equivalence classes. [2025-03-04 15:43:30,505 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 45 of 45 statements. [2025-03-04 15:43:30,505 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:30,505 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:30,512 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:30,512 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:30,513 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 12 times [2025-03-04 15:43:30,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:30,513 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39548667] [2025-03-04 15:43:30,513 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:43:30,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:30,515 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:30,516 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:30,517 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 15:43:30,517 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:30,517 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:30,517 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:30,518 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:30,518 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:30,518 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:30,519 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:30,520 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:30,520 INFO L85 PathProgramCache]: Analyzing trace with hash -674996695, now seen corresponding path program 21 times [2025-03-04 15:43:30,520 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:30,520 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162375593] [2025-03-04 15:43:30,520 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:30,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:30,527 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 48 statements into 12 equivalence classes. [2025-03-04 15:43:30,603 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) and asserted 48 of 48 statements. [2025-03-04 15:43:30,603 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2025-03-04 15:43:30,603 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:30,936 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 145 proven. 97 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:30,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:30,936 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162375593] [2025-03-04 15:43:30,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162375593] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:30,936 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [416614417] [2025-03-04 15:43:30,936 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:30,936 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:30,937 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:30,938 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:30,940 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2025-03-04 15:43:30,989 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 48 statements into 12 equivalence classes. [2025-03-04 15:43:31,165 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) and asserted 48 of 48 statements. [2025-03-04 15:43:31,165 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2025-03-04 15:43:31,165 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:31,167 INFO L256 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-03-04 15:43:31,168 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:31,455 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 176 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:31,455 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:31,650 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 176 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:31,650 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [416614417] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:31,650 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:31,650 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 39 [2025-03-04 15:43:31,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [914132804] [2025-03-04 15:43:31,650 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:31,682 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:31,683 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2025-03-04 15:43:31,683 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=380, Invalid=1180, Unknown=0, NotChecked=0, Total=1560 [2025-03-04 15:43:31,683 INFO L87 Difference]: Start difference. First operand 87 states and 101 transitions. cyclomatic complexity: 17 Second operand has 40 states, 39 states have (on average 2.282051282051282) internal successors, (89), 40 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:31,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:31,984 INFO L93 Difference]: Finished difference Result 305 states and 356 transitions. [2025-03-04 15:43:31,984 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 305 states and 356 transitions. [2025-03-04 15:43:31,986 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:31,987 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 305 states to 171 states and 199 transitions. [2025-03-04 15:43:31,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 159 [2025-03-04 15:43:31,987 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 159 [2025-03-04 15:43:31,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 171 states and 199 transitions. [2025-03-04 15:43:31,987 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:31,987 INFO L218 hiAutomatonCegarLoop]: Abstraction has 171 states and 199 transitions. [2025-03-04 15:43:31,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states and 199 transitions. [2025-03-04 15:43:31,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 94. [2025-03-04 15:43:31,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 94 states, 94 states have (on average 1.1595744680851063) internal successors, (109), 93 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:31,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 109 transitions. [2025-03-04 15:43:31,989 INFO L240 hiAutomatonCegarLoop]: Abstraction has 94 states and 109 transitions. [2025-03-04 15:43:31,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2025-03-04 15:43:31,993 INFO L432 stractBuchiCegarLoop]: Abstraction has 94 states and 109 transitions. [2025-03-04 15:43:31,993 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-04 15:43:31,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94 states and 109 transitions. [2025-03-04 15:43:31,993 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:31,993 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:31,993 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:31,994 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 11, 1, 1, 1] [2025-03-04 15:43:31,994 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:31,994 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:31,994 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:31,994 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:31,994 INFO L85 PathProgramCache]: Analyzing trace with hash 198369863, now seen corresponding path program 22 times [2025-03-04 15:43:31,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:31,994 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114920474] [2025-03-04 15:43:31,994 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:43:31,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:32,001 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 49 statements into 2 equivalence classes. [2025-03-04 15:43:32,025 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 49 of 49 statements. [2025-03-04 15:43:32,026 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:43:32,026 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:32,026 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:32,030 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-03-04 15:43:32,051 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-03-04 15:43:32,051 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:32,051 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:32,057 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:32,058 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:32,058 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 13 times [2025-03-04 15:43:32,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:32,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768052791] [2025-03-04 15:43:32,058 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:32,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:32,060 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:32,061 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:32,061 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:32,061 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:32,061 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:32,061 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:32,062 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:32,062 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:32,062 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:32,063 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:32,064 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:32,064 INFO L85 PathProgramCache]: Analyzing trace with hash -238384161, now seen corresponding path program 23 times [2025-03-04 15:43:32,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:32,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44447832] [2025-03-04 15:43:32,064 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:32,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:32,072 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 52 statements into 13 equivalence classes. [2025-03-04 15:43:32,095 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) and asserted 52 of 52 statements. [2025-03-04 15:43:32,095 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2025-03-04 15:43:32,095 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:32,459 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:32,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:32,459 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [44447832] [2025-03-04 15:43:32,460 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [44447832] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:32,460 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1434089580] [2025-03-04 15:43:32,460 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:32,460 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:32,460 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:32,462 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:32,463 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2025-03-04 15:43:32,512 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 52 statements into 13 equivalence classes. [2025-03-04 15:43:32,586 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) and asserted 52 of 52 statements. [2025-03-04 15:43:32,586 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2025-03-04 15:43:32,586 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:32,588 INFO L256 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 28 conjuncts are in the unsatisfiable core [2025-03-04 15:43:32,589 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:32,893 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:32,893 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:33,104 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:33,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1434089580] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:33,104 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:33,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27] total 40 [2025-03-04 15:43:33,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [216107553] [2025-03-04 15:43:33,105 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:33,135 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:33,135 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2025-03-04 15:43:33,136 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=404, Invalid=1236, Unknown=0, NotChecked=0, Total=1640 [2025-03-04 15:43:33,136 INFO L87 Difference]: Start difference. First operand 94 states and 109 transitions. cyclomatic complexity: 18 Second operand has 41 states, 40 states have (on average 2.25) internal successors, (90), 41 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:33,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:33,438 INFO L93 Difference]: Finished difference Result 330 states and 385 transitions. [2025-03-04 15:43:33,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 330 states and 385 transitions. [2025-03-04 15:43:33,440 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:33,440 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 330 states to 184 states and 214 transitions. [2025-03-04 15:43:33,440 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 171 [2025-03-04 15:43:33,440 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 171 [2025-03-04 15:43:33,441 INFO L73 IsDeterministic]: Start isDeterministic. Operand 184 states and 214 transitions. [2025-03-04 15:43:33,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:33,441 INFO L218 hiAutomatonCegarLoop]: Abstraction has 184 states and 214 transitions. [2025-03-04 15:43:33,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states and 214 transitions. [2025-03-04 15:43:33,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 101. [2025-03-04 15:43:33,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 101 states have (on average 1.1584158415841583) internal successors, (117), 100 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:33,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 117 transitions. [2025-03-04 15:43:33,444 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101 states and 117 transitions. [2025-03-04 15:43:33,444 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2025-03-04 15:43:33,445 INFO L432 stractBuchiCegarLoop]: Abstraction has 101 states and 117 transitions. [2025-03-04 15:43:33,445 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-04 15:43:33,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101 states and 117 transitions. [2025-03-04 15:43:33,446 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:33,446 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:33,446 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:33,447 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 12, 12, 1, 1, 1] [2025-03-04 15:43:33,447 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:33,447 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:33,447 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:33,447 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:33,447 INFO L85 PathProgramCache]: Analyzing trace with hash -1264725763, now seen corresponding path program 24 times [2025-03-04 15:43:33,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:33,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [182336201] [2025-03-04 15:43:33,447 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:43:33,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:33,454 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 53 statements into 13 equivalence classes. [2025-03-04 15:43:33,517 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) and asserted 53 of 53 statements. [2025-03-04 15:43:33,517 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2025-03-04 15:43:33,517 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:33,517 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:33,520 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 53 statements into 1 equivalence classes. [2025-03-04 15:43:33,540 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 53 of 53 statements. [2025-03-04 15:43:33,540 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:33,540 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:33,545 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:33,545 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:33,545 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 14 times [2025-03-04 15:43:33,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:33,545 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1641442532] [2025-03-04 15:43:33,545 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:43:33,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:33,547 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:33,547 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:33,548 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:43:33,548 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:33,548 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:33,549 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:33,550 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:33,550 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:33,550 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:33,551 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:33,551 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:33,551 INFO L85 PathProgramCache]: Analyzing trace with hash -1992058519, now seen corresponding path program 25 times [2025-03-04 15:43:33,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:33,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437597434] [2025-03-04 15:43:33,551 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:33,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:33,579 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-03-04 15:43:33,585 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-03-04 15:43:33,585 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:33,585 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:34,037 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 210 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:34,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:34,038 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437597434] [2025-03-04 15:43:34,038 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437597434] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:34,038 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1806175200] [2025-03-04 15:43:34,038 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:34,038 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:34,038 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:34,041 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:34,042 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2025-03-04 15:43:34,116 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-03-04 15:43:34,142 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-03-04 15:43:34,142 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:34,142 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:34,143 INFO L256 TraceCheckSpWp]: Trace formula consists of 314 conjuncts, 30 conjuncts are in the unsatisfiable core [2025-03-04 15:43:34,144 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:34,514 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 247 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:34,514 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:34,783 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 247 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:34,783 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1806175200] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:34,783 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:34,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29] total 45 [2025-03-04 15:43:34,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1696465780] [2025-03-04 15:43:34,783 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:34,813 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:34,813 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2025-03-04 15:43:34,813 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=498, Invalid=1572, Unknown=0, NotChecked=0, Total=2070 [2025-03-04 15:43:34,814 INFO L87 Difference]: Start difference. First operand 101 states and 117 transitions. cyclomatic complexity: 19 Second operand has 46 states, 45 states have (on average 2.2888888888888888) internal successors, (103), 46 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:35,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:35,202 INFO L93 Difference]: Finished difference Result 355 states and 414 transitions. [2025-03-04 15:43:35,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 355 states and 414 transitions. [2025-03-04 15:43:35,204 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:35,204 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 355 states to 197 states and 229 transitions. [2025-03-04 15:43:35,205 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 183 [2025-03-04 15:43:35,205 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 183 [2025-03-04 15:43:35,205 INFO L73 IsDeterministic]: Start isDeterministic. Operand 197 states and 229 transitions. [2025-03-04 15:43:35,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:35,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 197 states and 229 transitions. [2025-03-04 15:43:35,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states and 229 transitions. [2025-03-04 15:43:35,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 108. [2025-03-04 15:43:35,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.1574074074074074) internal successors, (125), 107 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:35,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 125 transitions. [2025-03-04 15:43:35,207 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 125 transitions. [2025-03-04 15:43:35,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2025-03-04 15:43:35,207 INFO L432 stractBuchiCegarLoop]: Abstraction has 108 states and 125 transitions. [2025-03-04 15:43:35,207 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-04 15:43:35,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 125 transitions. [2025-03-04 15:43:35,208 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:35,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:35,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:35,208 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [14, 14, 13, 13, 1, 1, 1] [2025-03-04 15:43:35,209 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:35,209 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:35,209 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:35,209 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:35,209 INFO L85 PathProgramCache]: Analyzing trace with hash 2022907783, now seen corresponding path program 26 times [2025-03-04 15:43:35,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:35,209 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313010492] [2025-03-04 15:43:35,209 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:43:35,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:35,218 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 57 statements into 2 equivalence classes. [2025-03-04 15:43:35,241 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 57 of 57 statements. [2025-03-04 15:43:35,241 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:43:35,241 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:35,241 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:35,244 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 57 statements into 1 equivalence classes. [2025-03-04 15:43:35,272 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 57 of 57 statements. [2025-03-04 15:43:35,272 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:35,272 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:35,276 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:35,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:35,277 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 15 times [2025-03-04 15:43:35,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:35,277 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [806992231] [2025-03-04 15:43:35,277 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:35,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:35,279 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:35,295 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:35,296 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 15:43:35,296 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:35,296 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:35,296 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:35,297 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:35,297 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:35,297 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:35,299 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:35,299 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:35,299 INFO L85 PathProgramCache]: Analyzing trace with hash 1759659679, now seen corresponding path program 27 times [2025-03-04 15:43:35,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:35,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165331029] [2025-03-04 15:43:35,299 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:35,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:35,310 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 60 statements into 15 equivalence classes. [2025-03-04 15:43:35,411 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) and asserted 60 of 60 statements. [2025-03-04 15:43:35,411 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2025-03-04 15:43:35,411 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:35,914 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 247 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:35,915 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:35,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1165331029] [2025-03-04 15:43:35,915 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1165331029] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:35,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [191150617] [2025-03-04 15:43:35,915 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:35,915 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:35,915 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:35,917 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:35,919 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2025-03-04 15:43:35,982 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 60 statements into 15 equivalence classes. [2025-03-04 15:43:36,395 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) and asserted 60 of 60 statements. [2025-03-04 15:43:36,395 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2025-03-04 15:43:36,395 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:36,398 INFO L256 TraceCheckSpWp]: Trace formula consists of 335 conjuncts, 32 conjuncts are in the unsatisfiable core [2025-03-04 15:43:36,399 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:36,743 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 287 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:36,743 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:37,020 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 287 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:37,020 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [191150617] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:37,020 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:37,020 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31] total 48 [2025-03-04 15:43:37,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942972310] [2025-03-04 15:43:37,020 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:37,056 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:37,057 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2025-03-04 15:43:37,057 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=563, Invalid=1789, Unknown=0, NotChecked=0, Total=2352 [2025-03-04 15:43:37,057 INFO L87 Difference]: Start difference. First operand 108 states and 125 transitions. cyclomatic complexity: 20 Second operand has 49 states, 48 states have (on average 2.2916666666666665) internal successors, (110), 49 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:37,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:37,447 INFO L93 Difference]: Finished difference Result 380 states and 443 transitions. [2025-03-04 15:43:37,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 380 states and 443 transitions. [2025-03-04 15:43:37,449 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:37,450 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 380 states to 210 states and 244 transitions. [2025-03-04 15:43:37,450 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-03-04 15:43:37,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2025-03-04 15:43:37,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 210 states and 244 transitions. [2025-03-04 15:43:37,451 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:37,451 INFO L218 hiAutomatonCegarLoop]: Abstraction has 210 states and 244 transitions. [2025-03-04 15:43:37,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states and 244 transitions. [2025-03-04 15:43:37,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 115. [2025-03-04 15:43:37,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 115 states have (on average 1.1565217391304348) internal successors, (133), 114 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:37,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 133 transitions. [2025-03-04 15:43:37,457 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115 states and 133 transitions. [2025-03-04 15:43:37,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2025-03-04 15:43:37,458 INFO L432 stractBuchiCegarLoop]: Abstraction has 115 states and 133 transitions. [2025-03-04 15:43:37,458 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-04 15:43:37,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115 states and 133 transitions. [2025-03-04 15:43:37,458 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:37,458 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:37,458 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:37,459 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 14, 14, 1, 1, 1] [2025-03-04 15:43:37,459 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:37,459 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:37,459 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:37,459 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:37,459 INFO L85 PathProgramCache]: Analyzing trace with hash 2057670077, now seen corresponding path program 28 times [2025-03-04 15:43:37,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:37,460 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372133115] [2025-03-04 15:43:37,460 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:43:37,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:37,468 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 61 statements into 2 equivalence classes. [2025-03-04 15:43:37,503 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 61 of 61 statements. [2025-03-04 15:43:37,503 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:43:37,503 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:37,503 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:37,508 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 61 statements into 1 equivalence classes. [2025-03-04 15:43:37,533 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 61 of 61 statements. [2025-03-04 15:43:37,533 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:37,533 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:37,538 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:37,539 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:37,539 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 16 times [2025-03-04 15:43:37,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:37,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330069836] [2025-03-04 15:43:37,539 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:43:37,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:37,541 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-03-04 15:43:37,542 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:37,542 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:43:37,542 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:37,542 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:37,543 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:37,543 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:37,543 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:37,543 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:37,545 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:37,545 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:37,545 INFO L85 PathProgramCache]: Analyzing trace with hash -2018925399, now seen corresponding path program 29 times [2025-03-04 15:43:37,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:37,545 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245216457] [2025-03-04 15:43:37,545 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:37,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:37,555 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 64 statements into 16 equivalence classes. [2025-03-04 15:43:37,582 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) and asserted 64 of 64 statements. [2025-03-04 15:43:37,582 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2025-03-04 15:43:37,583 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:38,091 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:38,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:38,091 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1245216457] [2025-03-04 15:43:38,091 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1245216457] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:38,091 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2037914252] [2025-03-04 15:43:38,091 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:38,092 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:38,092 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:38,094 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:38,097 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2025-03-04 15:43:38,180 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 64 statements into 16 equivalence classes. [2025-03-04 15:43:38,327 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) and asserted 64 of 64 statements. [2025-03-04 15:43:38,328 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2025-03-04 15:43:38,328 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:38,330 INFO L256 TraceCheckSpWp]: Trace formula consists of 356 conjuncts, 34 conjuncts are in the unsatisfiable core [2025-03-04 15:43:38,333 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:38,773 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:38,773 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:39,050 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:39,050 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2037914252] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:39,050 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:39,050 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33] total 49 [2025-03-04 15:43:39,050 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1019503471] [2025-03-04 15:43:39,050 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:39,083 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:39,083 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2025-03-04 15:43:39,084 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=593, Invalid=1857, Unknown=0, NotChecked=0, Total=2450 [2025-03-04 15:43:39,084 INFO L87 Difference]: Start difference. First operand 115 states and 133 transitions. cyclomatic complexity: 21 Second operand has 50 states, 49 states have (on average 2.2653061224489797) internal successors, (111), 50 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:39,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:39,478 INFO L93 Difference]: Finished difference Result 405 states and 472 transitions. [2025-03-04 15:43:39,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 405 states and 472 transitions. [2025-03-04 15:43:39,479 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:39,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 405 states to 223 states and 259 transitions. [2025-03-04 15:43:39,480 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 207 [2025-03-04 15:43:39,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 207 [2025-03-04 15:43:39,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223 states and 259 transitions. [2025-03-04 15:43:39,481 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:39,481 INFO L218 hiAutomatonCegarLoop]: Abstraction has 223 states and 259 transitions. [2025-03-04 15:43:39,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states and 259 transitions. [2025-03-04 15:43:39,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 122. [2025-03-04 15:43:39,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122 states, 122 states have (on average 1.1557377049180328) internal successors, (141), 121 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:39,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 141 transitions. [2025-03-04 15:43:39,482 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122 states and 141 transitions. [2025-03-04 15:43:39,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2025-03-04 15:43:39,483 INFO L432 stractBuchiCegarLoop]: Abstraction has 122 states and 141 transitions. [2025-03-04 15:43:39,483 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-04 15:43:39,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122 states and 141 transitions. [2025-03-04 15:43:39,484 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:39,484 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:39,484 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:39,484 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [16, 16, 15, 15, 1, 1, 1] [2025-03-04 15:43:39,484 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:39,484 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:39,485 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:39,485 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:39,485 INFO L85 PathProgramCache]: Analyzing trace with hash -367514425, now seen corresponding path program 30 times [2025-03-04 15:43:39,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:39,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [97628673] [2025-03-04 15:43:39,485 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:43:39,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:39,494 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 65 statements into 16 equivalence classes. [2025-03-04 15:43:39,601 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) and asserted 65 of 65 statements. [2025-03-04 15:43:39,601 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2025-03-04 15:43:39,601 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:39,601 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:39,604 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 65 statements into 1 equivalence classes. [2025-03-04 15:43:39,626 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 65 of 65 statements. [2025-03-04 15:43:39,626 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:39,626 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:39,631 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:39,631 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:39,631 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 17 times [2025-03-04 15:43:39,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:39,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977039571] [2025-03-04 15:43:39,631 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:39,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:39,633 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:39,633 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:39,634 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:43:39,634 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:39,634 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:39,634 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:39,634 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:39,634 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:39,635 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:39,636 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:39,636 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:39,636 INFO L85 PathProgramCache]: Analyzing trace with hash -750571169, now seen corresponding path program 31 times [2025-03-04 15:43:39,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:39,636 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1582955160] [2025-03-04 15:43:39,636 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:39,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:39,644 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 68 statements into 1 equivalence classes. [2025-03-04 15:43:39,651 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 68 of 68 statements. [2025-03-04 15:43:39,651 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:39,651 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:40,203 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 330 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:40,204 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:40,204 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1582955160] [2025-03-04 15:43:40,204 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1582955160] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:40,204 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [871313367] [2025-03-04 15:43:40,204 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:40,204 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:40,204 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:40,206 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:40,208 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2025-03-04 15:43:40,279 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 68 statements into 1 equivalence classes. [2025-03-04 15:43:40,310 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 68 of 68 statements. [2025-03-04 15:43:40,310 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:40,310 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:40,317 INFO L256 TraceCheckSpWp]: Trace formula consists of 377 conjuncts, 36 conjuncts are in the unsatisfiable core [2025-03-04 15:43:40,318 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:40,743 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 376 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:40,743 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:41,076 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 376 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:41,076 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [871313367] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:41,076 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:41,076 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35] total 54 [2025-03-04 15:43:41,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1053390732] [2025-03-04 15:43:41,076 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:41,100 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:41,101 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2025-03-04 15:43:41,101 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=705, Invalid=2265, Unknown=0, NotChecked=0, Total=2970 [2025-03-04 15:43:41,101 INFO L87 Difference]: Start difference. First operand 122 states and 141 transitions. cyclomatic complexity: 22 Second operand has 55 states, 54 states have (on average 2.2962962962962963) internal successors, (124), 55 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:41,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:41,541 INFO L93 Difference]: Finished difference Result 430 states and 501 transitions. [2025-03-04 15:43:41,541 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 501 transitions. [2025-03-04 15:43:41,542 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:41,543 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 236 states and 274 transitions. [2025-03-04 15:43:41,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 219 [2025-03-04 15:43:41,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 219 [2025-03-04 15:43:41,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 236 states and 274 transitions. [2025-03-04 15:43:41,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:41,543 INFO L218 hiAutomatonCegarLoop]: Abstraction has 236 states and 274 transitions. [2025-03-04 15:43:41,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states and 274 transitions. [2025-03-04 15:43:41,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 129. [2025-03-04 15:43:41,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 129 states, 129 states have (on average 1.1550387596899225) internal successors, (149), 128 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:41,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 149 transitions. [2025-03-04 15:43:41,545 INFO L240 hiAutomatonCegarLoop]: Abstraction has 129 states and 149 transitions. [2025-03-04 15:43:41,545 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2025-03-04 15:43:41,546 INFO L432 stractBuchiCegarLoop]: Abstraction has 129 states and 149 transitions. [2025-03-04 15:43:41,546 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-04 15:43:41,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 129 states and 149 transitions. [2025-03-04 15:43:41,546 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:41,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:41,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:41,546 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [17, 17, 16, 16, 1, 1, 1] [2025-03-04 15:43:41,546 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:41,547 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:41,547 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:41,547 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:41,547 INFO L85 PathProgramCache]: Analyzing trace with hash -858490243, now seen corresponding path program 32 times [2025-03-04 15:43:41,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:41,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947362837] [2025-03-04 15:43:41,547 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:43:41,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:41,555 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 69 statements into 2 equivalence classes. [2025-03-04 15:43:41,584 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 69 of 69 statements. [2025-03-04 15:43:41,584 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:43:41,584 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:41,584 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:41,587 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 69 statements into 1 equivalence classes. [2025-03-04 15:43:41,613 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 69 of 69 statements. [2025-03-04 15:43:41,613 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:41,613 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:41,617 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:41,618 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:41,618 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 18 times [2025-03-04 15:43:41,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:41,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541019747] [2025-03-04 15:43:41,618 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:43:41,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:41,620 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:41,621 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:41,621 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 15:43:41,621 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:41,621 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:41,621 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:41,621 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:41,622 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:41,622 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:41,623 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:41,623 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:41,623 INFO L85 PathProgramCache]: Analyzing trace with hash 1247444969, now seen corresponding path program 33 times [2025-03-04 15:43:41,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:41,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236270934] [2025-03-04 15:43:41,623 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:41,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:41,632 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 72 statements into 18 equivalence classes. [2025-03-04 15:43:41,772 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) and asserted 72 of 72 statements. [2025-03-04 15:43:41,773 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2025-03-04 15:43:41,773 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:42,356 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 376 proven. 202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:42,357 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:42,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1236270934] [2025-03-04 15:43:42,357 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1236270934] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:42,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1583116709] [2025-03-04 15:43:42,357 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:42,357 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:42,357 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:42,359 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:42,360 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2025-03-04 15:43:42,431 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 72 statements into 18 equivalence classes. [2025-03-04 15:43:42,813 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) and asserted 72 of 72 statements. [2025-03-04 15:43:42,813 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2025-03-04 15:43:42,813 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:42,815 INFO L256 TraceCheckSpWp]: Trace formula consists of 398 conjuncts, 38 conjuncts are in the unsatisfiable core [2025-03-04 15:43:42,817 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:43,258 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 425 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:43,258 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:43,611 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 425 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:43,612 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1583116709] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:43,612 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:43,612 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37] total 57 [2025-03-04 15:43:43,612 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86898693] [2025-03-04 15:43:43,612 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:43,657 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:43,657 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2025-03-04 15:43:43,658 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=782, Invalid=2524, Unknown=0, NotChecked=0, Total=3306 [2025-03-04 15:43:43,658 INFO L87 Difference]: Start difference. First operand 129 states and 149 transitions. cyclomatic complexity: 23 Second operand has 58 states, 57 states have (on average 2.2982456140350878) internal successors, (131), 58 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:44,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:44,190 INFO L93 Difference]: Finished difference Result 455 states and 530 transitions. [2025-03-04 15:43:44,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 455 states and 530 transitions. [2025-03-04 15:43:44,192 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:44,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 455 states to 249 states and 289 transitions. [2025-03-04 15:43:44,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 231 [2025-03-04 15:43:44,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 231 [2025-03-04 15:43:44,193 INFO L73 IsDeterministic]: Start isDeterministic. Operand 249 states and 289 transitions. [2025-03-04 15:43:44,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:44,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 249 states and 289 transitions. [2025-03-04 15:43:44,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states and 289 transitions. [2025-03-04 15:43:44,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 136. [2025-03-04 15:43:44,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 136 states, 136 states have (on average 1.1544117647058822) internal successors, (157), 135 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:44,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 157 transitions. [2025-03-04 15:43:44,196 INFO L240 hiAutomatonCegarLoop]: Abstraction has 136 states and 157 transitions. [2025-03-04 15:43:44,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2025-03-04 15:43:44,196 INFO L432 stractBuchiCegarLoop]: Abstraction has 136 states and 157 transitions. [2025-03-04 15:43:44,196 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-04 15:43:44,196 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 136 states and 157 transitions. [2025-03-04 15:43:44,197 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:44,197 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:44,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:44,198 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [18, 18, 17, 17, 1, 1, 1] [2025-03-04 15:43:44,198 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:44,198 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:44,198 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:44,198 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:44,198 INFO L85 PathProgramCache]: Analyzing trace with hash 432409095, now seen corresponding path program 34 times [2025-03-04 15:43:44,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:44,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943808604] [2025-03-04 15:43:44,199 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:43:44,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:44,212 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 73 statements into 2 equivalence classes. [2025-03-04 15:43:44,275 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 73 of 73 statements. [2025-03-04 15:43:44,275 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:43:44,275 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:44,275 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:44,279 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 73 statements into 1 equivalence classes. [2025-03-04 15:43:44,329 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 73 of 73 statements. [2025-03-04 15:43:44,329 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:44,329 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:44,335 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:44,336 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:44,336 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 19 times [2025-03-04 15:43:44,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:44,336 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [528421286] [2025-03-04 15:43:44,336 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:44,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:44,339 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:44,339 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:44,339 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:44,339 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:44,339 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:44,340 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:44,340 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:44,340 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:44,340 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:44,342 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:44,342 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:44,342 INFO L85 PathProgramCache]: Analyzing trace with hash 1292454943, now seen corresponding path program 35 times [2025-03-04 15:43:44,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:44,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335706515] [2025-03-04 15:43:44,342 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:44,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:44,355 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 76 statements into 19 equivalence classes. [2025-03-04 15:43:44,390 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) and asserted 76 of 76 statements. [2025-03-04 15:43:44,390 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2025-03-04 15:43:44,390 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:44,988 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:44,989 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:44,989 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1335706515] [2025-03-04 15:43:44,989 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1335706515] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:44,989 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1235066133] [2025-03-04 15:43:44,989 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:44,989 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:44,989 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:44,991 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:44,992 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2025-03-04 15:43:45,072 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 76 statements into 19 equivalence classes. [2025-03-04 15:43:45,351 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) and asserted 76 of 76 statements. [2025-03-04 15:43:45,352 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2025-03-04 15:43:45,352 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:45,354 INFO L256 TraceCheckSpWp]: Trace formula consists of 419 conjuncts, 40 conjuncts are in the unsatisfiable core [2025-03-04 15:43:45,356 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:45,920 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:45,920 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:46,348 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:46,349 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1235066133] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:46,349 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:46,349 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39] total 58 [2025-03-04 15:43:46,349 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [303075967] [2025-03-04 15:43:46,349 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:46,373 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:46,373 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2025-03-04 15:43:46,374 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=818, Invalid=2604, Unknown=0, NotChecked=0, Total=3422 [2025-03-04 15:43:46,374 INFO L87 Difference]: Start difference. First operand 136 states and 157 transitions. cyclomatic complexity: 24 Second operand has 59 states, 58 states have (on average 2.2758620689655173) internal successors, (132), 59 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:46,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:46,961 INFO L93 Difference]: Finished difference Result 480 states and 559 transitions. [2025-03-04 15:43:46,961 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 559 transitions. [2025-03-04 15:43:46,962 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:46,963 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 262 states and 304 transitions. [2025-03-04 15:43:46,963 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 243 [2025-03-04 15:43:46,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 243 [2025-03-04 15:43:46,963 INFO L73 IsDeterministic]: Start isDeterministic. Operand 262 states and 304 transitions. [2025-03-04 15:43:46,964 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:46,964 INFO L218 hiAutomatonCegarLoop]: Abstraction has 262 states and 304 transitions. [2025-03-04 15:43:46,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 262 states and 304 transitions. [2025-03-04 15:43:46,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 262 to 143. [2025-03-04 15:43:46,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 143 states, 143 states have (on average 1.1538461538461537) internal successors, (165), 142 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:46,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 165 transitions. [2025-03-04 15:43:46,966 INFO L240 hiAutomatonCegarLoop]: Abstraction has 143 states and 165 transitions. [2025-03-04 15:43:46,966 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2025-03-04 15:43:46,967 INFO L432 stractBuchiCegarLoop]: Abstraction has 143 states and 165 transitions. [2025-03-04 15:43:46,967 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-03-04 15:43:46,967 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 143 states and 165 transitions. [2025-03-04 15:43:46,967 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:46,967 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:46,967 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:46,968 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [19, 19, 18, 18, 1, 1, 1] [2025-03-04 15:43:46,968 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:46,968 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:46,968 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:46,968 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:46,968 INFO L85 PathProgramCache]: Analyzing trace with hash 155621181, now seen corresponding path program 36 times [2025-03-04 15:43:46,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:46,968 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926994461] [2025-03-04 15:43:46,968 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:43:46,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:46,977 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 77 statements into 19 equivalence classes. [2025-03-04 15:43:47,066 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) and asserted 77 of 77 statements. [2025-03-04 15:43:47,067 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2025-03-04 15:43:47,067 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:47,067 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:47,071 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-04 15:43:47,100 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-04 15:43:47,100 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:47,100 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:47,105 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:47,106 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:47,106 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 20 times [2025-03-04 15:43:47,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:47,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205005350] [2025-03-04 15:43:47,106 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:43:47,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:47,108 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:47,109 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:47,109 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:43:47,109 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:47,109 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:47,109 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:47,110 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:47,110 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:47,110 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:47,111 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:47,111 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:47,111 INFO L85 PathProgramCache]: Analyzing trace with hash 1840917289, now seen corresponding path program 37 times [2025-03-04 15:43:47,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:47,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [461203256] [2025-03-04 15:43:47,112 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:47,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:47,121 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-04 15:43:47,129 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-04 15:43:47,129 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:47,129 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:47,752 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 477 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:47,752 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:47,752 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [461203256] [2025-03-04 15:43:47,752 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [461203256] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:47,752 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [116322386] [2025-03-04 15:43:47,752 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:47,752 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:47,752 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:47,754 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:47,755 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2025-03-04 15:43:47,837 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-04 15:43:47,873 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-04 15:43:47,873 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:47,873 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:47,874 INFO L256 TraceCheckSpWp]: Trace formula consists of 440 conjuncts, 42 conjuncts are in the unsatisfiable core [2025-03-04 15:43:47,876 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:48,446 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 532 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:48,446 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:48,855 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 532 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:48,855 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [116322386] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:48,855 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:48,855 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41, 41] total 63 [2025-03-04 15:43:48,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564484333] [2025-03-04 15:43:48,856 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:48,879 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:48,880 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2025-03-04 15:43:48,880 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=948, Invalid=3084, Unknown=0, NotChecked=0, Total=4032 [2025-03-04 15:43:48,880 INFO L87 Difference]: Start difference. First operand 143 states and 165 transitions. cyclomatic complexity: 25 Second operand has 64 states, 63 states have (on average 2.3015873015873014) internal successors, (145), 64 states have internal predecessors, (145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:49,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:49,430 INFO L93 Difference]: Finished difference Result 505 states and 588 transitions. [2025-03-04 15:43:49,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 505 states and 588 transitions. [2025-03-04 15:43:49,432 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:49,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 505 states to 275 states and 319 transitions. [2025-03-04 15:43:49,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 255 [2025-03-04 15:43:49,433 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 255 [2025-03-04 15:43:49,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 275 states and 319 transitions. [2025-03-04 15:43:49,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:49,433 INFO L218 hiAutomatonCegarLoop]: Abstraction has 275 states and 319 transitions. [2025-03-04 15:43:49,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 275 states and 319 transitions. [2025-03-04 15:43:49,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 275 to 150. [2025-03-04 15:43:49,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 150 states, 150 states have (on average 1.1533333333333333) internal successors, (173), 149 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:49,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 173 transitions. [2025-03-04 15:43:49,435 INFO L240 hiAutomatonCegarLoop]: Abstraction has 150 states and 173 transitions. [2025-03-04 15:43:49,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2025-03-04 15:43:49,437 INFO L432 stractBuchiCegarLoop]: Abstraction has 150 states and 173 transitions. [2025-03-04 15:43:49,437 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-03-04 15:43:49,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 150 states and 173 transitions. [2025-03-04 15:43:49,438 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:49,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:49,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:49,438 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [20, 20, 19, 19, 1, 1, 1] [2025-03-04 15:43:49,438 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:49,438 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:49,439 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:49,439 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:49,439 INFO L85 PathProgramCache]: Analyzing trace with hash -436160697, now seen corresponding path program 38 times [2025-03-04 15:43:49,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:49,439 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345868011] [2025-03-04 15:43:49,439 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:43:49,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:49,450 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 81 statements into 2 equivalence classes. [2025-03-04 15:43:49,478 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 81 of 81 statements. [2025-03-04 15:43:49,479 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:43:49,479 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:49,479 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:49,482 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-04 15:43:49,517 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-04 15:43:49,517 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:49,517 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:49,523 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:49,523 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:49,524 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 21 times [2025-03-04 15:43:49,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:49,524 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213782799] [2025-03-04 15:43:49,524 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:49,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:49,526 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:49,526 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:49,526 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 15:43:49,526 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:49,526 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:49,527 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:49,527 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:49,527 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:49,527 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:49,528 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:49,529 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:49,529 INFO L85 PathProgramCache]: Analyzing trace with hash -1387227425, now seen corresponding path program 39 times [2025-03-04 15:43:49,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:49,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285317740] [2025-03-04 15:43:49,529 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:49,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:49,539 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 84 statements into 21 equivalence classes. [2025-03-04 15:43:49,772 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) and asserted 84 of 84 statements. [2025-03-04 15:43:49,772 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2025-03-04 15:43:49,772 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:50,620 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 532 proven. 268 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:50,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:50,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285317740] [2025-03-04 15:43:50,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285317740] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:50,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1269496719] [2025-03-04 15:43:50,621 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:43:50,621 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:50,621 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:50,624 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:50,625 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2025-03-04 15:43:50,726 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 84 statements into 21 equivalence classes. [2025-03-04 15:43:51,577 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) and asserted 84 of 84 statements. [2025-03-04 15:43:51,577 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2025-03-04 15:43:51,577 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:51,580 INFO L256 TraceCheckSpWp]: Trace formula consists of 461 conjuncts, 44 conjuncts are in the unsatisfiable core [2025-03-04 15:43:51,582 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:52,150 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 590 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:52,151 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:52,606 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 590 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:52,607 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1269496719] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:52,607 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:52,607 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43, 43] total 66 [2025-03-04 15:43:52,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1002072472] [2025-03-04 15:43:52,607 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:52,632 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:52,633 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2025-03-04 15:43:52,634 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1037, Invalid=3385, Unknown=0, NotChecked=0, Total=4422 [2025-03-04 15:43:52,634 INFO L87 Difference]: Start difference. First operand 150 states and 173 transitions. cyclomatic complexity: 26 Second operand has 67 states, 66 states have (on average 2.303030303030303) internal successors, (152), 67 states have internal predecessors, (152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:53,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:53,278 INFO L93 Difference]: Finished difference Result 530 states and 617 transitions. [2025-03-04 15:43:53,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 530 states and 617 transitions. [2025-03-04 15:43:53,280 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:53,281 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 530 states to 288 states and 334 transitions. [2025-03-04 15:43:53,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 267 [2025-03-04 15:43:53,281 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 267 [2025-03-04 15:43:53,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 334 transitions. [2025-03-04 15:43:53,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:53,281 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 334 transitions. [2025-03-04 15:43:53,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 334 transitions. [2025-03-04 15:43:53,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 157. [2025-03-04 15:43:53,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 157 states, 157 states have (on average 1.1528662420382165) internal successors, (181), 156 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:53,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 181 transitions. [2025-03-04 15:43:53,283 INFO L240 hiAutomatonCegarLoop]: Abstraction has 157 states and 181 transitions. [2025-03-04 15:43:53,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2025-03-04 15:43:53,284 INFO L432 stractBuchiCegarLoop]: Abstraction has 157 states and 181 transitions. [2025-03-04 15:43:53,284 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-03-04 15:43:53,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 157 states and 181 transitions. [2025-03-04 15:43:53,284 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:53,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:53,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:53,285 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [21, 21, 20, 20, 1, 1, 1] [2025-03-04 15:43:53,285 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:53,285 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:53,285 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:53,285 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:53,285 INFO L85 PathProgramCache]: Analyzing trace with hash 1226302461, now seen corresponding path program 40 times [2025-03-04 15:43:53,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:53,285 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659590115] [2025-03-04 15:43:53,285 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:43:53,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:53,295 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 85 statements into 2 equivalence classes. [2025-03-04 15:43:53,337 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 85 of 85 statements. [2025-03-04 15:43:53,337 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:43:53,337 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:53,337 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:53,341 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 85 statements into 1 equivalence classes. [2025-03-04 15:43:53,376 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 85 of 85 statements. [2025-03-04 15:43:53,376 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:53,376 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:53,382 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:53,383 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:53,383 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 22 times [2025-03-04 15:43:53,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:53,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111862253] [2025-03-04 15:43:53,383 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:43:53,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:53,385 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-03-04 15:43:53,385 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:53,386 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:43:53,386 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:53,386 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:53,386 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:53,386 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:53,386 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:53,386 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:53,388 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:53,388 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:53,389 INFO L85 PathProgramCache]: Analyzing trace with hash -215177623, now seen corresponding path program 41 times [2025-03-04 15:43:53,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:53,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144618966] [2025-03-04 15:43:53,389 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:53,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:53,400 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 88 statements into 22 equivalence classes. [2025-03-04 15:43:53,437 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) and asserted 88 of 88 statements. [2025-03-04 15:43:53,437 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2025-03-04 15:43:53,438 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:54,241 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:54,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:54,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2144618966] [2025-03-04 15:43:54,242 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2144618966] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:54,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1087483135] [2025-03-04 15:43:54,242 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:54,242 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:54,242 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:54,244 INFO L229 MonitoredProcess]: Starting monitored process 38 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:54,244 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2025-03-04 15:43:54,344 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 88 statements into 22 equivalence classes. [2025-03-04 15:43:55,346 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) and asserted 88 of 88 statements. [2025-03-04 15:43:55,346 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2025-03-04 15:43:55,346 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:55,351 INFO L256 TraceCheckSpWp]: Trace formula consists of 482 conjuncts, 46 conjuncts are in the unsatisfiable core [2025-03-04 15:43:55,352 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:55,980 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:55,981 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:56,467 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:56,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1087483135] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:56,467 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:56,467 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45, 45] total 67 [2025-03-04 15:43:56,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1897210578] [2025-03-04 15:43:56,467 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:56,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:56,492 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2025-03-04 15:43:56,493 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1079, Invalid=3477, Unknown=0, NotChecked=0, Total=4556 [2025-03-04 15:43:56,493 INFO L87 Difference]: Start difference. First operand 157 states and 181 transitions. cyclomatic complexity: 27 Second operand has 68 states, 67 states have (on average 2.283582089552239) internal successors, (153), 68 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:57,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:43:57,121 INFO L93 Difference]: Finished difference Result 555 states and 646 transitions. [2025-03-04 15:43:57,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 555 states and 646 transitions. [2025-03-04 15:43:57,123 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:57,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 555 states to 301 states and 349 transitions. [2025-03-04 15:43:57,124 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 279 [2025-03-04 15:43:57,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 279 [2025-03-04 15:43:57,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 301 states and 349 transitions. [2025-03-04 15:43:57,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:43:57,124 INFO L218 hiAutomatonCegarLoop]: Abstraction has 301 states and 349 transitions. [2025-03-04 15:43:57,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 301 states and 349 transitions. [2025-03-04 15:43:57,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 301 to 164. [2025-03-04 15:43:57,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 164 states, 164 states have (on average 1.1524390243902438) internal successors, (189), 163 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:43:57,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 189 transitions. [2025-03-04 15:43:57,127 INFO L240 hiAutomatonCegarLoop]: Abstraction has 164 states and 189 transitions. [2025-03-04 15:43:57,127 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2025-03-04 15:43:57,127 INFO L432 stractBuchiCegarLoop]: Abstraction has 164 states and 189 transitions. [2025-03-04 15:43:57,127 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-03-04 15:43:57,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 164 states and 189 transitions. [2025-03-04 15:43:57,128 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:43:57,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:43:57,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:43:57,128 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 21, 21, 1, 1, 1] [2025-03-04 15:43:57,128 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:43:57,128 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:57,129 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:43:57,131 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:57,131 INFO L85 PathProgramCache]: Analyzing trace with hash -1842596729, now seen corresponding path program 42 times [2025-03-04 15:43:57,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:57,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022287451] [2025-03-04 15:43:57,131 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:43:57,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:57,145 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 89 statements into 22 equivalence classes. [2025-03-04 15:43:57,318 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 15:43:57,318 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2025-03-04 15:43:57,318 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:57,318 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:57,323 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 15:43:57,373 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 15:43:57,374 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:57,374 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:57,386 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:57,389 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:57,389 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 23 times [2025-03-04 15:43:57,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:57,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832191580] [2025-03-04 15:43:57,389 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:43:57,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:57,391 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:57,392 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:57,392 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:43:57,392 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:57,392 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:43:57,392 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:43:57,393 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:43:57,393 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:57,393 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:43:57,395 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:43:57,395 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:43:57,395 INFO L85 PathProgramCache]: Analyzing trace with hash 1177883039, now seen corresponding path program 43 times [2025-03-04 15:43:57,395 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:43:57,395 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261248620] [2025-03-04 15:43:57,396 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:57,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:43:57,405 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes. [2025-03-04 15:43:57,414 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements. [2025-03-04 15:43:57,414 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:57,414 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:58,328 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 651 proven. 317 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:58,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:43:58,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261248620] [2025-03-04 15:43:58,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1261248620] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:43:58,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1906197195] [2025-03-04 15:43:58,328 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:43:58,328 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:43:58,328 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:43:58,330 INFO L229 MonitoredProcess]: Starting monitored process 39 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:43:58,331 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2025-03-04 15:43:58,431 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes. [2025-03-04 15:43:58,470 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements. [2025-03-04 15:43:58,470 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:43:58,470 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:43:58,472 INFO L256 TraceCheckSpWp]: Trace formula consists of 503 conjuncts, 48 conjuncts are in the unsatisfiable core [2025-03-04 15:43:58,473 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:43:59,150 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 715 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:59,150 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:43:59,646 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 715 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:43:59,646 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1906197195] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:43:59,647 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:43:59,647 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47, 47] total 72 [2025-03-04 15:43:59,647 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2097778080] [2025-03-04 15:43:59,647 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:43:59,676 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:43:59,677 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2025-03-04 15:43:59,678 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1227, Invalid=4029, Unknown=0, NotChecked=0, Total=5256 [2025-03-04 15:43:59,678 INFO L87 Difference]: Start difference. First operand 164 states and 189 transitions. cyclomatic complexity: 28 Second operand has 73 states, 72 states have (on average 2.3055555555555554) internal successors, (166), 73 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:00,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:44:00,330 INFO L93 Difference]: Finished difference Result 580 states and 675 transitions. [2025-03-04 15:44:00,331 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 580 states and 675 transitions. [2025-03-04 15:44:00,332 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:00,333 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 580 states to 314 states and 364 transitions. [2025-03-04 15:44:00,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291 [2025-03-04 15:44:00,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291 [2025-03-04 15:44:00,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 314 states and 364 transitions. [2025-03-04 15:44:00,334 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:44:00,334 INFO L218 hiAutomatonCegarLoop]: Abstraction has 314 states and 364 transitions. [2025-03-04 15:44:00,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314 states and 364 transitions. [2025-03-04 15:44:00,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314 to 171. [2025-03-04 15:44:00,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 171 states, 171 states have (on average 1.152046783625731) internal successors, (197), 170 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:00,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 197 transitions. [2025-03-04 15:44:00,336 INFO L240 hiAutomatonCegarLoop]: Abstraction has 171 states and 197 transitions. [2025-03-04 15:44:00,336 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2025-03-04 15:44:00,337 INFO L432 stractBuchiCegarLoop]: Abstraction has 171 states and 197 transitions. [2025-03-04 15:44:00,337 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-03-04 15:44:00,337 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 171 states and 197 transitions. [2025-03-04 15:44:00,337 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:00,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:44:00,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:44:00,338 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 23, 22, 22, 1, 1, 1] [2025-03-04 15:44:00,338 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:44:00,338 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:00,338 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:00,338 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:00,338 INFO L85 PathProgramCache]: Analyzing trace with hash 543449277, now seen corresponding path program 44 times [2025-03-04 15:44:00,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:00,339 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114060496] [2025-03-04 15:44:00,339 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:44:00,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:00,348 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 93 statements into 2 equivalence classes. [2025-03-04 15:44:00,391 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 93 of 93 statements. [2025-03-04 15:44:00,392 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:44:00,392 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:00,392 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:00,396 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 93 statements into 1 equivalence classes. [2025-03-04 15:44:00,491 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 93 of 93 statements. [2025-03-04 15:44:00,491 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:00,491 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:00,501 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:00,501 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:00,501 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 24 times [2025-03-04 15:44:00,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:00,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [388809339] [2025-03-04 15:44:00,501 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:44:00,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:00,505 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:00,505 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:00,505 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 15:44:00,506 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:00,506 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:00,506 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:00,507 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:00,507 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:00,507 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:00,509 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:00,509 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:00,509 INFO L85 PathProgramCache]: Analyzing trace with hash -2129268311, now seen corresponding path program 45 times [2025-03-04 15:44:00,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:00,509 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947569050] [2025-03-04 15:44:00,509 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:44:00,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:00,523 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 96 statements into 24 equivalence classes. [2025-03-04 15:44:00,950 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) and asserted 96 of 96 statements. [2025-03-04 15:44:00,950 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2025-03-04 15:44:00,950 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:01,813 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 715 proven. 343 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:01,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:44:01,814 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1947569050] [2025-03-04 15:44:01,814 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1947569050] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:44:01,814 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [948121538] [2025-03-04 15:44:01,814 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:44:01,814 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:44:01,814 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:44:01,816 INFO L229 MonitoredProcess]: Starting monitored process 40 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:44:01,817 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2025-03-04 15:44:01,922 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 96 statements into 24 equivalence classes. [2025-03-04 15:44:04,103 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) and asserted 96 of 96 statements. [2025-03-04 15:44:04,104 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2025-03-04 15:44:04,104 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:04,109 INFO L256 TraceCheckSpWp]: Trace formula consists of 524 conjuncts, 50 conjuncts are in the unsatisfiable core [2025-03-04 15:44:04,111 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:44:04,834 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 782 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:04,834 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:44:05,398 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 782 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:05,399 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [948121538] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:44:05,399 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:44:05,399 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49] total 75 [2025-03-04 15:44:05,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1376935903] [2025-03-04 15:44:05,399 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:44:05,423 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:44:05,424 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2025-03-04 15:44:05,425 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1328, Invalid=4372, Unknown=0, NotChecked=0, Total=5700 [2025-03-04 15:44:05,425 INFO L87 Difference]: Start difference. First operand 171 states and 197 transitions. cyclomatic complexity: 29 Second operand has 76 states, 75 states have (on average 2.3066666666666666) internal successors, (173), 76 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:06,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:44:06,120 INFO L93 Difference]: Finished difference Result 605 states and 704 transitions. [2025-03-04 15:44:06,120 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 605 states and 704 transitions. [2025-03-04 15:44:06,121 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:06,122 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 605 states to 327 states and 379 transitions. [2025-03-04 15:44:06,122 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2025-03-04 15:44:06,122 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2025-03-04 15:44:06,122 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 379 transitions. [2025-03-04 15:44:06,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:44:06,123 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 379 transitions. [2025-03-04 15:44:06,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 379 transitions. [2025-03-04 15:44:06,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 178. [2025-03-04 15:44:06,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.151685393258427) internal successors, (205), 177 states have internal predecessors, (205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:06,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 205 transitions. [2025-03-04 15:44:06,125 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 205 transitions. [2025-03-04 15:44:06,125 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2025-03-04 15:44:06,126 INFO L432 stractBuchiCegarLoop]: Abstraction has 178 states and 205 transitions. [2025-03-04 15:44:06,126 INFO L338 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2025-03-04 15:44:06,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 205 transitions. [2025-03-04 15:44:06,126 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:06,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:44:06,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:44:06,126 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 24, 23, 23, 1, 1, 1] [2025-03-04 15:44:06,127 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:44:06,127 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:06,127 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:06,127 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:06,127 INFO L85 PathProgramCache]: Analyzing trace with hash 111968711, now seen corresponding path program 46 times [2025-03-04 15:44:06,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:06,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942919008] [2025-03-04 15:44:06,127 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:44:06,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:06,139 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 97 statements into 2 equivalence classes. [2025-03-04 15:44:06,219 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 97 of 97 statements. [2025-03-04 15:44:06,219 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:44:06,219 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:06,219 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:06,223 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 97 statements into 1 equivalence classes. [2025-03-04 15:44:06,272 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 97 of 97 statements. [2025-03-04 15:44:06,272 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:06,272 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:06,278 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:06,279 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:06,279 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 25 times [2025-03-04 15:44:06,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:06,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [660842153] [2025-03-04 15:44:06,279 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:44:06,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:06,282 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:06,282 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:06,282 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:06,282 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:06,282 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:06,283 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:06,283 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:06,283 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:06,283 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:06,285 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:06,285 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:06,285 INFO L85 PathProgramCache]: Analyzing trace with hash -1529693089, now seen corresponding path program 47 times [2025-03-04 15:44:06,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:06,285 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400937487] [2025-03-04 15:44:06,285 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:44:06,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:06,297 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 100 statements into 25 equivalence classes. [2025-03-04 15:44:06,334 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) and asserted 100 of 100 statements. [2025-03-04 15:44:06,334 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2025-03-04 15:44:06,334 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:07,246 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:07,246 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:44:07,246 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400937487] [2025-03-04 15:44:07,246 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1400937487] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:44:07,246 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [706396763] [2025-03-04 15:44:07,246 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:44:07,246 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:44:07,246 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:44:07,248 INFO L229 MonitoredProcess]: Starting monitored process 41 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:44:07,249 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2025-03-04 15:44:07,364 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 100 statements into 25 equivalence classes. [2025-03-04 15:44:10,280 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) and asserted 100 of 100 statements. [2025-03-04 15:44:10,280 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2025-03-04 15:44:10,280 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:10,285 INFO L256 TraceCheckSpWp]: Trace formula consists of 545 conjuncts, 52 conjuncts are in the unsatisfiable core [2025-03-04 15:44:10,287 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:44:11,044 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:11,044 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:44:11,625 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:11,625 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [706396763] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:44:11,625 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:44:11,625 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51, 51] total 76 [2025-03-04 15:44:11,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [132834253] [2025-03-04 15:44:11,625 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:44:11,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:44:11,651 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2025-03-04 15:44:11,652 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1376, Invalid=4476, Unknown=0, NotChecked=0, Total=5852 [2025-03-04 15:44:11,653 INFO L87 Difference]: Start difference. First operand 178 states and 205 transitions. cyclomatic complexity: 30 Second operand has 77 states, 76 states have (on average 2.289473684210526) internal successors, (174), 77 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:12,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:44:12,380 INFO L93 Difference]: Finished difference Result 630 states and 733 transitions. [2025-03-04 15:44:12,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 630 states and 733 transitions. [2025-03-04 15:44:12,382 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:12,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 630 states to 340 states and 394 transitions. [2025-03-04 15:44:12,383 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 315 [2025-03-04 15:44:12,383 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 315 [2025-03-04 15:44:12,383 INFO L73 IsDeterministic]: Start isDeterministic. Operand 340 states and 394 transitions. [2025-03-04 15:44:12,383 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:44:12,383 INFO L218 hiAutomatonCegarLoop]: Abstraction has 340 states and 394 transitions. [2025-03-04 15:44:12,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states and 394 transitions. [2025-03-04 15:44:12,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 185. [2025-03-04 15:44:12,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 185 states, 185 states have (on average 1.1513513513513514) internal successors, (213), 184 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:12,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 213 transitions. [2025-03-04 15:44:12,385 INFO L240 hiAutomatonCegarLoop]: Abstraction has 185 states and 213 transitions. [2025-03-04 15:44:12,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2025-03-04 15:44:12,386 INFO L432 stractBuchiCegarLoop]: Abstraction has 185 states and 213 transitions. [2025-03-04 15:44:12,386 INFO L338 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2025-03-04 15:44:12,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 185 states and 213 transitions. [2025-03-04 15:44:12,386 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:12,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:44:12,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:44:12,387 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [25, 25, 24, 24, 1, 1, 1] [2025-03-04 15:44:12,387 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:44:12,387 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:12,387 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:12,387 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:12,387 INFO L85 PathProgramCache]: Analyzing trace with hash 1581780349, now seen corresponding path program 48 times [2025-03-04 15:44:12,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:12,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074009969] [2025-03-04 15:44:12,387 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:44:12,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:12,400 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 101 statements into 25 equivalence classes. [2025-03-04 15:44:12,597 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) and asserted 101 of 101 statements. [2025-03-04 15:44:12,598 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2025-03-04 15:44:12,598 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:12,598 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:12,601 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 101 statements into 1 equivalence classes. [2025-03-04 15:44:12,649 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 101 of 101 statements. [2025-03-04 15:44:12,649 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:12,649 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:12,655 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:12,656 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:12,656 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 26 times [2025-03-04 15:44:12,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:12,656 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [951738893] [2025-03-04 15:44:12,656 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:44:12,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:12,658 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:12,659 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:12,659 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:44:12,659 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:12,659 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:12,659 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:12,660 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:12,660 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:12,660 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:12,661 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:12,662 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:12,662 INFO L85 PathProgramCache]: Analyzing trace with hash -1562768151, now seen corresponding path program 49 times [2025-03-04 15:44:12,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:12,662 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093748936] [2025-03-04 15:44:12,662 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:44:12,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:12,674 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 104 statements into 1 equivalence classes. [2025-03-04 15:44:12,683 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 104 of 104 statements. [2025-03-04 15:44:12,684 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:12,684 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:13,629 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 852 proven. 398 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:13,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:44:13,629 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093748936] [2025-03-04 15:44:13,629 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1093748936] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:44:13,629 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [531744520] [2025-03-04 15:44:13,629 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:44:13,629 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:44:13,629 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:44:13,631 INFO L229 MonitoredProcess]: Starting monitored process 42 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:44:13,632 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2025-03-04 15:44:13,750 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 104 statements into 1 equivalence classes. [2025-03-04 15:44:13,790 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 104 of 104 statements. [2025-03-04 15:44:13,790 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:13,790 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:13,792 INFO L256 TraceCheckSpWp]: Trace formula consists of 566 conjuncts, 54 conjuncts are in the unsatisfiable core [2025-03-04 15:44:13,794 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:44:14,606 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 925 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:14,606 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:44:15,239 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 925 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:15,239 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [531744520] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:44:15,239 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:44:15,240 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53, 53] total 81 [2025-03-04 15:44:15,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1686879163] [2025-03-04 15:44:15,240 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:44:15,272 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:44:15,273 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2025-03-04 15:44:15,274 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1542, Invalid=5100, Unknown=0, NotChecked=0, Total=6642 [2025-03-04 15:44:15,274 INFO L87 Difference]: Start difference. First operand 185 states and 213 transitions. cyclomatic complexity: 31 Second operand has 82 states, 81 states have (on average 2.308641975308642) internal successors, (187), 82 states have internal predecessors, (187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:16,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:44:16,065 INFO L93 Difference]: Finished difference Result 655 states and 762 transitions. [2025-03-04 15:44:16,065 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 655 states and 762 transitions. [2025-03-04 15:44:16,066 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:16,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 655 states to 353 states and 409 transitions. [2025-03-04 15:44:16,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2025-03-04 15:44:16,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2025-03-04 15:44:16,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 353 states and 409 transitions. [2025-03-04 15:44:16,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:44:16,068 INFO L218 hiAutomatonCegarLoop]: Abstraction has 353 states and 409 transitions. [2025-03-04 15:44:16,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353 states and 409 transitions. [2025-03-04 15:44:16,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353 to 192. [2025-03-04 15:44:16,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 192 states, 192 states have (on average 1.1510416666666667) internal successors, (221), 191 states have internal predecessors, (221), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:16,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 221 transitions. [2025-03-04 15:44:16,070 INFO L240 hiAutomatonCegarLoop]: Abstraction has 192 states and 221 transitions. [2025-03-04 15:44:16,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2025-03-04 15:44:16,071 INFO L432 stractBuchiCegarLoop]: Abstraction has 192 states and 221 transitions. [2025-03-04 15:44:16,071 INFO L338 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2025-03-04 15:44:16,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 192 states and 221 transitions. [2025-03-04 15:44:16,071 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:16,071 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:44:16,071 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:44:16,072 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [26, 26, 25, 25, 1, 1, 1] [2025-03-04 15:44:16,072 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:44:16,072 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:16,072 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:16,072 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:16,072 INFO L85 PathProgramCache]: Analyzing trace with hash 283483911, now seen corresponding path program 50 times [2025-03-04 15:44:16,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:16,072 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972615589] [2025-03-04 15:44:16,072 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:44:16,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:16,083 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 105 statements into 2 equivalence classes. [2025-03-04 15:44:16,130 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 105 of 105 statements. [2025-03-04 15:44:16,130 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:44:16,130 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:16,130 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:16,136 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 105 statements into 1 equivalence classes. [2025-03-04 15:44:16,196 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 105 of 105 statements. [2025-03-04 15:44:16,197 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:16,197 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:16,207 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:16,207 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:16,207 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 27 times [2025-03-04 15:44:16,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:16,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1678298706] [2025-03-04 15:44:16,208 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:44:16,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:16,210 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:16,211 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:16,211 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 15:44:16,211 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:16,211 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:16,211 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:16,211 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:16,212 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:16,212 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:16,213 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:16,213 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:16,214 INFO L85 PathProgramCache]: Analyzing trace with hash 1363515167, now seen corresponding path program 51 times [2025-03-04 15:44:16,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:16,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668925237] [2025-03-04 15:44:16,214 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:44:16,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:16,226 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 108 statements into 27 equivalence classes. [2025-03-04 15:44:16,702 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) and asserted 108 of 108 statements. [2025-03-04 15:44:16,702 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2025-03-04 15:44:16,702 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:17,702 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 925 proven. 427 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:17,702 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:44:17,702 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1668925237] [2025-03-04 15:44:17,702 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1668925237] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:44:17,702 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1879516539] [2025-03-04 15:44:17,702 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:44:17,702 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:44:17,702 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:44:17,704 INFO L229 MonitoredProcess]: Starting monitored process 43 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:44:17,706 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2025-03-04 15:44:17,840 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 108 statements into 27 equivalence classes. [2025-03-04 15:44:20,230 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) and asserted 108 of 108 statements. [2025-03-04 15:44:20,230 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2025-03-04 15:44:20,230 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:20,236 INFO L256 TraceCheckSpWp]: Trace formula consists of 587 conjuncts, 56 conjuncts are in the unsatisfiable core [2025-03-04 15:44:20,238 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:44:21,182 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 1001 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:21,182 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:44:21,888 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 1001 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:21,888 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1879516539] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:44:21,888 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:44:21,888 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55, 55] total 84 [2025-03-04 15:44:21,888 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795129405] [2025-03-04 15:44:21,888 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:44:21,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:44:21,915 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2025-03-04 15:44:21,916 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1655, Invalid=5485, Unknown=0, NotChecked=0, Total=7140 [2025-03-04 15:44:21,916 INFO L87 Difference]: Start difference. First operand 192 states and 221 transitions. cyclomatic complexity: 32 Second operand has 85 states, 84 states have (on average 2.3095238095238093) internal successors, (194), 85 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:22,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:44:22,871 INFO L93 Difference]: Finished difference Result 680 states and 791 transitions. [2025-03-04 15:44:22,871 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 680 states and 791 transitions. [2025-03-04 15:44:22,874 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:22,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 680 states to 366 states and 424 transitions. [2025-03-04 15:44:22,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 339 [2025-03-04 15:44:22,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 339 [2025-03-04 15:44:22,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 366 states and 424 transitions. [2025-03-04 15:44:22,875 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:44:22,875 INFO L218 hiAutomatonCegarLoop]: Abstraction has 366 states and 424 transitions. [2025-03-04 15:44:22,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states and 424 transitions. [2025-03-04 15:44:22,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 199. [2025-03-04 15:44:22,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 199 states, 199 states have (on average 1.150753768844221) internal successors, (229), 198 states have internal predecessors, (229), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:22,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 229 transitions. [2025-03-04 15:44:22,878 INFO L240 hiAutomatonCegarLoop]: Abstraction has 199 states and 229 transitions. [2025-03-04 15:44:22,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2025-03-04 15:44:22,881 INFO L432 stractBuchiCegarLoop]: Abstraction has 199 states and 229 transitions. [2025-03-04 15:44:22,881 INFO L338 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2025-03-04 15:44:22,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 199 states and 229 transitions. [2025-03-04 15:44:22,881 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:22,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:44:22,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:44:22,882 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [27, 27, 26, 26, 1, 1, 1] [2025-03-04 15:44:22,882 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:44:22,882 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:22,884 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:22,885 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:22,885 INFO L85 PathProgramCache]: Analyzing trace with hash -857806275, now seen corresponding path program 52 times [2025-03-04 15:44:22,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:22,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711370839] [2025-03-04 15:44:22,885 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:44:22,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:22,901 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 109 statements into 2 equivalence classes. [2025-03-04 15:44:23,018 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 109 of 109 statements. [2025-03-04 15:44:23,018 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:44:23,018 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:23,018 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:23,022 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 109 statements into 1 equivalence classes. [2025-03-04 15:44:23,088 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 109 of 109 statements. [2025-03-04 15:44:23,089 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:23,089 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:23,096 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:23,096 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:23,096 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 28 times [2025-03-04 15:44:23,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:23,096 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [677970166] [2025-03-04 15:44:23,097 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:44:23,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:23,100 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-03-04 15:44:23,101 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:23,101 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:44:23,101 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:23,101 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:23,102 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:23,102 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:23,102 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:23,102 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:23,103 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:23,104 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:23,104 INFO L85 PathProgramCache]: Analyzing trace with hash 148699177, now seen corresponding path program 53 times [2025-03-04 15:44:23,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:23,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1226271784] [2025-03-04 15:44:23,104 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:44:23,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:23,116 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 112 statements into 28 equivalence classes. [2025-03-04 15:44:23,172 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) and asserted 112 of 112 statements. [2025-03-04 15:44:23,172 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2025-03-04 15:44:23,172 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:24,249 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1080 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:24,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:44:24,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1226271784] [2025-03-04 15:44:24,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1226271784] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:44:24,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [749073771] [2025-03-04 15:44:24,250 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:44:24,250 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:44:24,250 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:44:24,252 INFO L229 MonitoredProcess]: Starting monitored process 44 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:44:24,252 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2025-03-04 15:44:24,388 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 112 statements into 28 equivalence classes. [2025-03-04 15:44:25,348 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) and asserted 112 of 112 statements. [2025-03-04 15:44:25,348 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2025-03-04 15:44:25,349 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:25,355 INFO L256 TraceCheckSpWp]: Trace formula consists of 608 conjuncts, 58 conjuncts are in the unsatisfiable core [2025-03-04 15:44:25,357 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:44:26,359 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1080 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:26,359 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:44:27,072 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1080 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:27,073 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [749073771] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:44:27,073 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:44:27,073 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57, 57] total 85 [2025-03-04 15:44:27,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280359245] [2025-03-04 15:44:27,073 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:44:27,097 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:44:27,098 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2025-03-04 15:44:27,099 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1709, Invalid=5601, Unknown=0, NotChecked=0, Total=7310 [2025-03-04 15:44:27,099 INFO L87 Difference]: Start difference. First operand 199 states and 229 transitions. cyclomatic complexity: 33 Second operand has 86 states, 85 states have (on average 2.2941176470588234) internal successors, (195), 86 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:28,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:44:28,098 INFO L93 Difference]: Finished difference Result 705 states and 820 transitions. [2025-03-04 15:44:28,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 705 states and 820 transitions. [2025-03-04 15:44:28,100 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:28,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 705 states to 379 states and 439 transitions. [2025-03-04 15:44:28,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 351 [2025-03-04 15:44:28,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 351 [2025-03-04 15:44:28,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 379 states and 439 transitions. [2025-03-04 15:44:28,102 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:44:28,102 INFO L218 hiAutomatonCegarLoop]: Abstraction has 379 states and 439 transitions. [2025-03-04 15:44:28,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 379 states and 439 transitions. [2025-03-04 15:44:28,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 379 to 206. [2025-03-04 15:44:28,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 206 states, 206 states have (on average 1.1504854368932038) internal successors, (237), 205 states have internal predecessors, (237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:28,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 237 transitions. [2025-03-04 15:44:28,104 INFO L240 hiAutomatonCegarLoop]: Abstraction has 206 states and 237 transitions. [2025-03-04 15:44:28,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2025-03-04 15:44:28,105 INFO L432 stractBuchiCegarLoop]: Abstraction has 206 states and 237 transitions. [2025-03-04 15:44:28,105 INFO L338 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2025-03-04 15:44:28,105 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 206 states and 237 transitions. [2025-03-04 15:44:28,105 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:28,106 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:44:28,106 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:44:28,106 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [28, 28, 27, 27, 1, 1, 1] [2025-03-04 15:44:28,106 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:44:28,106 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:28,106 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:28,107 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:28,107 INFO L85 PathProgramCache]: Analyzing trace with hash -1556378553, now seen corresponding path program 54 times [2025-03-04 15:44:28,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:28,107 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330842269] [2025-03-04 15:44:28,107 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:44:28,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:28,118 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 113 statements into 28 equivalence classes. [2025-03-04 15:44:28,435 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) and asserted 113 of 113 statements. [2025-03-04 15:44:28,435 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) [2025-03-04 15:44:28,435 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:28,435 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:28,439 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 113 statements into 1 equivalence classes. [2025-03-04 15:44:28,499 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 113 of 113 statements. [2025-03-04 15:44:28,499 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:28,499 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:28,505 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:28,505 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:28,506 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 29 times [2025-03-04 15:44:28,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:28,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1570909768] [2025-03-04 15:44:28,506 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:44:28,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:28,508 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:28,508 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:28,508 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:44:28,508 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:28,508 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:28,509 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:28,509 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:28,509 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:28,509 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:28,510 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:28,510 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:28,510 INFO L85 PathProgramCache]: Analyzing trace with hash -1901485601, now seen corresponding path program 55 times [2025-03-04 15:44:28,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:28,511 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963655766] [2025-03-04 15:44:28,511 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:44:28,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:28,521 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 116 statements into 1 equivalence classes. [2025-03-04 15:44:28,533 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 116 of 116 statements. [2025-03-04 15:44:28,533 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:28,533 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:29,738 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1080 proven. 488 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:29,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:44:29,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1963655766] [2025-03-04 15:44:29,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1963655766] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:44:29,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1477948047] [2025-03-04 15:44:29,739 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:44:29,739 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:44:29,739 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:44:29,741 INFO L229 MonitoredProcess]: Starting monitored process 45 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:44:29,741 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2025-03-04 15:44:29,883 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 116 statements into 1 equivalence classes. [2025-03-04 15:44:29,928 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 116 of 116 statements. [2025-03-04 15:44:29,928 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:29,928 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:29,931 INFO L256 TraceCheckSpWp]: Trace formula consists of 629 conjuncts, 60 conjuncts are in the unsatisfiable core [2025-03-04 15:44:29,933 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:44:30,930 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1162 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:30,930 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:44:31,697 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1162 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:31,697 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1477948047] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:44:31,697 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:44:31,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59] total 90 [2025-03-04 15:44:31,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1937661147] [2025-03-04 15:44:31,697 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:44:31,720 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:44:31,721 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2025-03-04 15:44:31,722 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1893, Invalid=6297, Unknown=0, NotChecked=0, Total=8190 [2025-03-04 15:44:31,722 INFO L87 Difference]: Start difference. First operand 206 states and 237 transitions. cyclomatic complexity: 34 Second operand has 91 states, 90 states have (on average 2.311111111111111) internal successors, (208), 91 states have internal predecessors, (208), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:32,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:44:32,648 INFO L93 Difference]: Finished difference Result 730 states and 849 transitions. [2025-03-04 15:44:32,648 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 730 states and 849 transitions. [2025-03-04 15:44:32,650 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:32,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 730 states to 392 states and 454 transitions. [2025-03-04 15:44:32,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 363 [2025-03-04 15:44:32,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 363 [2025-03-04 15:44:32,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 392 states and 454 transitions. [2025-03-04 15:44:32,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:44:32,652 INFO L218 hiAutomatonCegarLoop]: Abstraction has 392 states and 454 transitions. [2025-03-04 15:44:32,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states and 454 transitions. [2025-03-04 15:44:32,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 213. [2025-03-04 15:44:32,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 213 states, 213 states have (on average 1.1502347417840375) internal successors, (245), 212 states have internal predecessors, (245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:32,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 245 transitions. [2025-03-04 15:44:32,654 INFO L240 hiAutomatonCegarLoop]: Abstraction has 213 states and 245 transitions. [2025-03-04 15:44:32,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2025-03-04 15:44:32,654 INFO L432 stractBuchiCegarLoop]: Abstraction has 213 states and 245 transitions. [2025-03-04 15:44:32,654 INFO L338 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2025-03-04 15:44:32,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 213 states and 245 transitions. [2025-03-04 15:44:32,655 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:32,655 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:44:32,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:44:32,655 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [29, 29, 28, 28, 1, 1, 1] [2025-03-04 15:44:32,655 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:44:32,656 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:32,656 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:32,656 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:32,656 INFO L85 PathProgramCache]: Analyzing trace with hash -247138563, now seen corresponding path program 56 times [2025-03-04 15:44:32,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:32,656 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [379067377] [2025-03-04 15:44:32,656 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:44:32,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:32,669 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 117 statements into 2 equivalence classes. [2025-03-04 15:44:32,732 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 117 of 117 statements. [2025-03-04 15:44:32,732 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:44:32,732 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:32,732 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:32,737 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 117 statements into 1 equivalence classes. [2025-03-04 15:44:32,839 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 117 of 117 statements. [2025-03-04 15:44:32,839 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:32,839 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:32,845 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:32,845 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:32,845 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 30 times [2025-03-04 15:44:32,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:32,845 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1069362370] [2025-03-04 15:44:32,845 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:44:32,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:32,849 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:32,849 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:32,849 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 15:44:32,849 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:32,849 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:32,850 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:32,850 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:32,850 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:32,850 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:32,851 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:32,852 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:32,852 INFO L85 PathProgramCache]: Analyzing trace with hash -930958487, now seen corresponding path program 57 times [2025-03-04 15:44:32,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:32,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720093375] [2025-03-04 15:44:32,853 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:44:32,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:32,866 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 120 statements into 30 equivalence classes. [2025-03-04 15:44:33,494 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) and asserted 120 of 120 statements. [2025-03-04 15:44:33,494 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2025-03-04 15:44:33,494 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:34,717 INFO L134 CoverageAnalysis]: Checked inductivity of 1682 backedges. 1162 proven. 520 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:34,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:44:34,717 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [720093375] [2025-03-04 15:44:34,717 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [720093375] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:44:34,717 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [516990658] [2025-03-04 15:44:34,717 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:44:34,717 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:44:34,717 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:44:34,720 INFO L229 MonitoredProcess]: Starting monitored process 46 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:44:34,720 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2025-03-04 15:44:34,873 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 120 statements into 30 equivalence classes. [2025-03-04 15:44:38,743 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) and asserted 120 of 120 statements. [2025-03-04 15:44:38,743 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2025-03-04 15:44:38,743 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:38,749 INFO L256 TraceCheckSpWp]: Trace formula consists of 650 conjuncts, 62 conjuncts are in the unsatisfiable core [2025-03-04 15:44:38,750 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:44:39,800 INFO L134 CoverageAnalysis]: Checked inductivity of 1682 backedges. 1247 proven. 435 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:39,801 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:44:40,657 INFO L134 CoverageAnalysis]: Checked inductivity of 1682 backedges. 1247 proven. 435 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:40,657 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [516990658] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:44:40,657 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:44:40,657 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61, 61] total 93 [2025-03-04 15:44:40,658 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840192786] [2025-03-04 15:44:40,658 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:44:40,691 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:44:40,691 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2025-03-04 15:44:40,692 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=2018, Invalid=6724, Unknown=0, NotChecked=0, Total=8742 [2025-03-04 15:44:40,692 INFO L87 Difference]: Start difference. First operand 213 states and 245 transitions. cyclomatic complexity: 35 Second operand has 94 states, 93 states have (on average 2.3118279569892475) internal successors, (215), 94 states have internal predecessors, (215), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:41,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:44:41,673 INFO L93 Difference]: Finished difference Result 755 states and 878 transitions. [2025-03-04 15:44:41,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 755 states and 878 transitions. [2025-03-04 15:44:41,675 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:41,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 755 states to 405 states and 469 transitions. [2025-03-04 15:44:41,676 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 375 [2025-03-04 15:44:41,676 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 375 [2025-03-04 15:44:41,676 INFO L73 IsDeterministic]: Start isDeterministic. Operand 405 states and 469 transitions. [2025-03-04 15:44:41,676 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:44:41,676 INFO L218 hiAutomatonCegarLoop]: Abstraction has 405 states and 469 transitions. [2025-03-04 15:44:41,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 405 states and 469 transitions. [2025-03-04 15:44:41,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 405 to 220. [2025-03-04 15:44:41,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 220 states, 220 states have (on average 1.15) internal successors, (253), 219 states have internal predecessors, (253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:44:41,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 253 transitions. [2025-03-04 15:44:41,679 INFO L240 hiAutomatonCegarLoop]: Abstraction has 220 states and 253 transitions. [2025-03-04 15:44:41,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2025-03-04 15:44:41,679 INFO L432 stractBuchiCegarLoop]: Abstraction has 220 states and 253 transitions. [2025-03-04 15:44:41,679 INFO L338 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2025-03-04 15:44:41,679 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 220 states and 253 transitions. [2025-03-04 15:44:41,680 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-03-04 15:44:41,680 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:44:41,680 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:44:41,680 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [30, 30, 29, 29, 1, 1, 1] [2025-03-04 15:44:41,680 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:44:41,680 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:41,681 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-03-04 15:44:41,681 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:41,681 INFO L85 PathProgramCache]: Analyzing trace with hash 353520007, now seen corresponding path program 58 times [2025-03-04 15:44:41,681 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:41,681 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703137060] [2025-03-04 15:44:41,681 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:44:41,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:41,695 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 121 statements into 2 equivalence classes. [2025-03-04 15:44:41,787 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 121 of 121 statements. [2025-03-04 15:44:41,787 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:44:41,787 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:41,787 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:41,792 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 121 statements into 1 equivalence classes. [2025-03-04 15:44:41,882 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 121 of 121 statements. [2025-03-04 15:44:41,882 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:41,882 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:41,890 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:41,890 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:41,890 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 31 times [2025-03-04 15:44:41,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:41,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506696240] [2025-03-04 15:44:41,890 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:44:41,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:41,893 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:41,893 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:41,893 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:41,893 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:41,893 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:44:41,894 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:44:41,894 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:44:41,894 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:44:41,894 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:44:41,895 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:44:41,895 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:44:41,896 INFO L85 PathProgramCache]: Analyzing trace with hash 454745247, now seen corresponding path program 59 times [2025-03-04 15:44:41,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:44:41,896 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76006025] [2025-03-04 15:44:41,896 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:44:41,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:44:41,907 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 124 statements into 31 equivalence classes. [2025-03-04 15:44:41,962 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 31 check-sat command(s) and asserted 124 of 124 statements. [2025-03-04 15:44:41,962 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 31 check-sat command(s) [2025-03-04 15:44:41,962 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:44:43,280 INFO L134 CoverageAnalysis]: Checked inductivity of 1800 backedges. 1335 proven. 465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:44:43,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:44:43,280 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [76006025] [2025-03-04 15:44:43,280 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [76006025] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:44:43,280 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [405335585] [2025-03-04 15:44:43,280 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:44:43,280 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:44:43,281 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:44:43,283 INFO L229 MonitoredProcess]: Starting monitored process 47 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:44:43,283 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2025-03-04 15:44:43,440 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 124 statements into 31 equivalence classes.