./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/locks/test_locks_14-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/locks/test_locks_14-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1e1f6c8a80d54f6d4b7b413368cc99af6eca243b930331d178961d851b56afbd --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 15:46:39,729 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 15:46:39,778 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-04 15:46:39,781 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 15:46:39,782 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 15:46:39,782 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 15:46:39,797 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 15:46:39,798 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 15:46:39,798 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 15:46:39,798 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 15:46:39,798 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 15:46:39,798 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 15:46:39,798 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 15:46:39,798 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 15:46:39,798 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 15:46:39,799 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 15:46:39,799 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 15:46:39,799 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 15:46:39,799 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 15:46:39,799 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 15:46:39,799 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 15:46:39,799 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 15:46:39,799 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-04 15:46:39,799 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 15:46:39,799 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-04 15:46:39,799 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 15:46:39,800 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 15:46:39,800 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 15:46:39,800 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 15:46:39,800 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 15:46:39,800 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-04 15:46:39,800 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 15:46:39,800 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 15:46:39,800 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 15:46:39,800 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 15:46:39,800 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 15:46:39,801 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 15:46:39,801 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 15:46:39,801 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 15:46:39,801 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 15:46:39,801 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1e1f6c8a80d54f6d4b7b413368cc99af6eca243b930331d178961d851b56afbd [2025-03-04 15:46:39,982 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 15:46:39,988 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 15:46:39,989 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 15:46:39,990 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 15:46:39,990 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 15:46:39,990 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/locks/test_locks_14-1.c [2025-03-04 15:46:41,118 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a2e9ac71d/1b895a69539048a381f847575086730c/FLAGdb1c0091c [2025-03-04 15:46:41,370 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 15:46:41,370 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/locks/test_locks_14-1.c [2025-03-04 15:46:41,380 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a2e9ac71d/1b895a69539048a381f847575086730c/FLAGdb1c0091c [2025-03-04 15:46:41,688 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a2e9ac71d/1b895a69539048a381f847575086730c [2025-03-04 15:46:41,689 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 15:46:41,690 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 15:46:41,691 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 15:46:41,691 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 15:46:41,694 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 15:46:41,695 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,695 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3640cd11 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41, skipping insertion in model container [2025-03-04 15:46:41,695 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,707 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 15:46:41,805 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 15:46:41,812 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 15:46:41,827 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 15:46:41,836 INFO L204 MainTranslator]: Completed translation [2025-03-04 15:46:41,836 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41 WrapperNode [2025-03-04 15:46:41,836 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 15:46:41,837 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 15:46:41,837 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 15:46:41,837 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 15:46:41,841 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,846 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,857 INFO L138 Inliner]: procedures = 12, calls = 8, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 179 [2025-03-04 15:46:41,857 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 15:46:41,858 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 15:46:41,858 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 15:46:41,858 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 15:46:41,863 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,864 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,865 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,873 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-04 15:46:41,873 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,874 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,876 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,876 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,877 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,877 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,878 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 15:46:41,879 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 15:46:41,879 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 15:46:41,879 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 15:46:41,880 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41" (1/1) ... [2025-03-04 15:46:41,883 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:46:41,895 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:46:41,907 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:46:41,909 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 15:46:41,929 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-04 15:46:41,929 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 15:46:41,929 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 15:46:41,929 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-04 15:46:41,970 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 15:46:41,971 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 15:46:42,142 INFO L? ?]: Removed 32 outVars from TransFormulas that were not future-live. [2025-03-04 15:46:42,142 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 15:46:42,152 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 15:46:42,152 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-04 15:46:42,153 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 03:46:42 BoogieIcfgContainer [2025-03-04 15:46:42,153 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 15:46:42,153 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 15:46:42,153 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 15:46:42,157 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 15:46:42,157 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 15:46:42,157 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 03:46:41" (1/3) ... [2025-03-04 15:46:42,158 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@16e8e9c8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 03:46:42, skipping insertion in model container [2025-03-04 15:46:42,158 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 15:46:42,158 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:46:41" (2/3) ... [2025-03-04 15:46:42,158 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@16e8e9c8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 03:46:42, skipping insertion in model container [2025-03-04 15:46:42,158 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 15:46:42,158 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 03:46:42" (3/3) ... [2025-03-04 15:46:42,159 INFO L363 chiAutomizerObserver]: Analyzing ICFG test_locks_14-1.c [2025-03-04 15:46:42,192 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 15:46:42,192 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 15:46:42,192 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 15:46:42,192 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 15:46:42,192 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 15:46:42,192 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 15:46:42,192 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 15:46:42,192 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 15:46:42,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 52 states, 51 states have (on average 1.8627450980392157) internal successors, (95), 51 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:42,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 44 [2025-03-04 15:46:42,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:42,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:42,218 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:42,218 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:42,218 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 15:46:42,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 52 states, 51 states have (on average 1.8627450980392157) internal successors, (95), 51 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:42,224 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 44 [2025-03-04 15:46:42,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:42,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:42,224 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:42,224 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:42,230 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:46:42,231 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume 0 != main_~p1~0#1;main_~lk1~0#1 := 1;" "assume 0 != main_~p2~0#1;main_~lk2~0#1 := 1;" "assume 0 != main_~p3~0#1;main_~lk3~0#1 := 1;" "assume 0 != main_~p4~0#1;main_~lk4~0#1 := 1;" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:46:42,235 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:42,235 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 1 times [2025-03-04 15:46:42,241 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:42,241 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58212765] [2025-03-04 15:46:42,241 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:42,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:42,285 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:42,293 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:42,294 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:42,295 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:42,295 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:46:42,299 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:42,301 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:42,302 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:42,302 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:42,316 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:46:42,318 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:42,318 INFO L85 PathProgramCache]: Analyzing trace with hash 1123980545, now seen corresponding path program 1 times [2025-03-04 15:46:42,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:42,318 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445900759] [2025-03-04 15:46:42,318 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:42,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:42,330 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:46:42,346 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:46:42,346 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:42,346 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:46:42,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:46:42,446 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:46:42,447 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445900759] [2025-03-04 15:46:42,447 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1445900759] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:46:42,448 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:46:42,448 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:46:42,448 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1896436131] [2025-03-04 15:46:42,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:46:42,451 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:46:42,453 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:46:42,472 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:46:42,472 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:46:42,474 INFO L87 Difference]: Start difference. First operand has 52 states, 51 states have (on average 1.8627450980392157) internal successors, (95), 51 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:42,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:46:42,513 INFO L93 Difference]: Finished difference Result 97 states and 177 transitions. [2025-03-04 15:46:42,514 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 177 transitions. [2025-03-04 15:46:42,517 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87 [2025-03-04 15:46:42,523 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 89 states and 143 transitions. [2025-03-04 15:46:42,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89 [2025-03-04 15:46:42,525 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89 [2025-03-04 15:46:42,525 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89 states and 143 transitions. [2025-03-04 15:46:42,526 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:46:42,526 INFO L218 hiAutomatonCegarLoop]: Abstraction has 89 states and 143 transitions. [2025-03-04 15:46:42,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states and 143 transitions. [2025-03-04 15:46:42,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 89. [2025-03-04 15:46:42,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89 states, 89 states have (on average 1.6067415730337078) internal successors, (143), 88 states have internal predecessors, (143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:42,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 143 transitions. [2025-03-04 15:46:42,555 INFO L240 hiAutomatonCegarLoop]: Abstraction has 89 states and 143 transitions. [2025-03-04 15:46:42,556 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:46:42,558 INFO L432 stractBuchiCegarLoop]: Abstraction has 89 states and 143 transitions. [2025-03-04 15:46:42,561 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 15:46:42,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89 states and 143 transitions. [2025-03-04 15:46:42,562 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87 [2025-03-04 15:46:42,563 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:42,563 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:42,563 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:42,563 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:42,563 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:46:42,563 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume 0 != main_~p2~0#1;main_~lk2~0#1 := 1;" "assume 0 != main_~p3~0#1;main_~lk3~0#1 := 1;" "assume 0 != main_~p4~0#1;main_~lk4~0#1 := 1;" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:46:42,564 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:42,564 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 2 times [2025-03-04 15:46:42,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:42,564 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770899317] [2025-03-04 15:46:42,564 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:46:42,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:42,568 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:42,570 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:42,572 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:46:42,572 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:42,572 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:46:42,573 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:42,575 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:42,577 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:42,577 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:42,579 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:46:42,580 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:42,581 INFO L85 PathProgramCache]: Analyzing trace with hash 869244000, now seen corresponding path program 1 times [2025-03-04 15:46:42,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:42,581 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249596070] [2025-03-04 15:46:42,581 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:42,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:42,588 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:46:42,597 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:46:42,597 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:42,597 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:46:42,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:46:42,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:46:42,627 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249596070] [2025-03-04 15:46:42,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1249596070] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:46:42,628 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:46:42,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:46:42,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550243474] [2025-03-04 15:46:42,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:46:42,628 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:46:42,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:46:42,628 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:46:42,629 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:46:42,629 INFO L87 Difference]: Start difference. First operand 89 states and 143 transitions. cyclomatic complexity: 56 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:42,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:46:42,656 INFO L93 Difference]: Finished difference Result 174 states and 278 transitions. [2025-03-04 15:46:42,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 174 states and 278 transitions. [2025-03-04 15:46:42,658 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 172 [2025-03-04 15:46:42,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 174 states to 174 states and 278 transitions. [2025-03-04 15:46:42,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 174 [2025-03-04 15:46:42,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 174 [2025-03-04 15:46:42,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 174 states and 278 transitions. [2025-03-04 15:46:42,664 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:46:42,664 INFO L218 hiAutomatonCegarLoop]: Abstraction has 174 states and 278 transitions. [2025-03-04 15:46:42,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states and 278 transitions. [2025-03-04 15:46:42,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2025-03-04 15:46:42,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 174 states, 174 states have (on average 1.5977011494252873) internal successors, (278), 173 states have internal predecessors, (278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:42,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 278 transitions. [2025-03-04 15:46:42,670 INFO L240 hiAutomatonCegarLoop]: Abstraction has 174 states and 278 transitions. [2025-03-04 15:46:42,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:46:42,671 INFO L432 stractBuchiCegarLoop]: Abstraction has 174 states and 278 transitions. [2025-03-04 15:46:42,671 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 15:46:42,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 174 states and 278 transitions. [2025-03-04 15:46:42,673 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 172 [2025-03-04 15:46:42,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:42,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:42,673 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:42,673 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:42,673 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:46:42,673 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume 0 != main_~p3~0#1;main_~lk3~0#1 := 1;" "assume 0 != main_~p4~0#1;main_~lk4~0#1 := 1;" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:46:42,674 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:42,674 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 3 times [2025-03-04 15:46:42,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:42,674 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785124216] [2025-03-04 15:46:42,674 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:46:42,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:42,679 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:42,680 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:42,681 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 15:46:42,681 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:42,681 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:46:42,682 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:42,685 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:42,687 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:42,688 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:42,689 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:46:42,691 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:42,691 INFO L85 PathProgramCache]: Analyzing trace with hash 1830858017, now seen corresponding path program 1 times [2025-03-04 15:46:42,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:42,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598518703] [2025-03-04 15:46:42,692 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:42,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:42,701 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:46:42,704 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:46:42,705 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:42,705 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:46:42,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:46:42,726 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:46:42,726 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598518703] [2025-03-04 15:46:42,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598518703] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:46:42,726 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:46:42,726 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:46:42,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1399854230] [2025-03-04 15:46:42,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:46:42,726 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:46:42,726 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:46:42,727 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:46:42,727 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:46:42,727 INFO L87 Difference]: Start difference. First operand 174 states and 278 transitions. cyclomatic complexity: 108 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:42,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:46:42,741 INFO L93 Difference]: Finished difference Result 342 states and 542 transitions. [2025-03-04 15:46:42,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342 states and 542 transitions. [2025-03-04 15:46:42,747 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 340 [2025-03-04 15:46:42,753 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342 states to 342 states and 542 transitions. [2025-03-04 15:46:42,754 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 342 [2025-03-04 15:46:42,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 342 [2025-03-04 15:46:42,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342 states and 542 transitions. [2025-03-04 15:46:42,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:46:42,755 INFO L218 hiAutomatonCegarLoop]: Abstraction has 342 states and 542 transitions. [2025-03-04 15:46:42,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states and 542 transitions. [2025-03-04 15:46:42,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 342. [2025-03-04 15:46:42,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 342 states, 342 states have (on average 1.5847953216374269) internal successors, (542), 341 states have internal predecessors, (542), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:42,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 342 states to 342 states and 542 transitions. [2025-03-04 15:46:42,777 INFO L240 hiAutomatonCegarLoop]: Abstraction has 342 states and 542 transitions. [2025-03-04 15:46:42,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:46:42,778 INFO L432 stractBuchiCegarLoop]: Abstraction has 342 states and 542 transitions. [2025-03-04 15:46:42,779 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 15:46:42,779 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 342 states and 542 transitions. [2025-03-04 15:46:42,780 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 340 [2025-03-04 15:46:42,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:42,780 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:42,781 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:42,781 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:42,781 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:46:42,781 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume 0 != main_~p4~0#1;main_~lk4~0#1 := 1;" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:46:42,781 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:42,783 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 4 times [2025-03-04 15:46:42,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:42,783 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342879358] [2025-03-04 15:46:42,783 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:46:42,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:42,788 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 15:46:42,789 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:42,789 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:46:42,790 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:42,790 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:46:42,791 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:42,794 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:42,794 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:42,794 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:42,796 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:46:42,796 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:42,796 INFO L85 PathProgramCache]: Analyzing trace with hash 1861877824, now seen corresponding path program 1 times [2025-03-04 15:46:42,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:42,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [972503275] [2025-03-04 15:46:42,797 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:42,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:42,803 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:46:42,809 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:46:42,814 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:42,814 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:46:42,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:46:42,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:46:42,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [972503275] [2025-03-04 15:46:42,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [972503275] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:46:42,836 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:46:42,836 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:46:42,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1291459425] [2025-03-04 15:46:42,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:46:42,836 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:46:42,836 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:46:42,837 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:46:42,837 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:46:42,837 INFO L87 Difference]: Start difference. First operand 342 states and 542 transitions. cyclomatic complexity: 208 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:42,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:46:42,852 INFO L93 Difference]: Finished difference Result 674 states and 1058 transitions. [2025-03-04 15:46:42,853 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 674 states and 1058 transitions. [2025-03-04 15:46:42,861 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 672 [2025-03-04 15:46:42,865 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 674 states to 674 states and 1058 transitions. [2025-03-04 15:46:42,866 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 674 [2025-03-04 15:46:42,867 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 674 [2025-03-04 15:46:42,867 INFO L73 IsDeterministic]: Start isDeterministic. Operand 674 states and 1058 transitions. [2025-03-04 15:46:42,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:46:42,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 674 states and 1058 transitions. [2025-03-04 15:46:42,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 674 states and 1058 transitions. [2025-03-04 15:46:42,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 674 to 674. [2025-03-04 15:46:42,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 674 states, 674 states have (on average 1.5697329376854599) internal successors, (1058), 673 states have internal predecessors, (1058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:42,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 1058 transitions. [2025-03-04 15:46:42,891 INFO L240 hiAutomatonCegarLoop]: Abstraction has 674 states and 1058 transitions. [2025-03-04 15:46:42,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:46:42,892 INFO L432 stractBuchiCegarLoop]: Abstraction has 674 states and 1058 transitions. [2025-03-04 15:46:42,892 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 15:46:42,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 674 states and 1058 transitions. [2025-03-04 15:46:42,898 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 672 [2025-03-04 15:46:42,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:42,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:42,899 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:42,899 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:42,899 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:46:42,899 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:46:42,900 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:42,900 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 5 times [2025-03-04 15:46:42,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:42,900 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54886116] [2025-03-04 15:46:42,900 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:46:42,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:42,903 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:42,904 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:42,904 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:46:42,904 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:42,904 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:46:42,907 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:42,908 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:42,909 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:42,909 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:42,925 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:46:42,926 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:42,926 INFO L85 PathProgramCache]: Analyzing trace with hash -215331519, now seen corresponding path program 1 times [2025-03-04 15:46:42,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:42,926 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095731557] [2025-03-04 15:46:42,926 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:42,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:42,933 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:46:42,938 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:46:42,939 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:42,939 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:46:42,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:46:42,955 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:46:42,955 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095731557] [2025-03-04 15:46:42,955 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095731557] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:46:42,955 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:46:42,955 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:46:42,955 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [650325871] [2025-03-04 15:46:42,955 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:46:42,956 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:46:42,956 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:46:42,956 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:46:42,956 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:46:42,957 INFO L87 Difference]: Start difference. First operand 674 states and 1058 transitions. cyclomatic complexity: 400 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:42,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:46:42,981 INFO L93 Difference]: Finished difference Result 1330 states and 2066 transitions. [2025-03-04 15:46:42,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1330 states and 2066 transitions. [2025-03-04 15:46:42,988 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 1328 [2025-03-04 15:46:42,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1330 states to 1330 states and 2066 transitions. [2025-03-04 15:46:42,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1330 [2025-03-04 15:46:42,995 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1330 [2025-03-04 15:46:42,995 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1330 states and 2066 transitions. [2025-03-04 15:46:42,996 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:46:42,996 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1330 states and 2066 transitions. [2025-03-04 15:46:42,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1330 states and 2066 transitions. [2025-03-04 15:46:43,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1330 to 1330. [2025-03-04 15:46:43,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1330 states, 1330 states have (on average 1.5533834586466166) internal successors, (2066), 1329 states have internal predecessors, (2066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:43,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1330 states to 1330 states and 2066 transitions. [2025-03-04 15:46:43,019 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1330 states and 2066 transitions. [2025-03-04 15:46:43,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:46:43,020 INFO L432 stractBuchiCegarLoop]: Abstraction has 1330 states and 2066 transitions. [2025-03-04 15:46:43,020 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 15:46:43,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1330 states and 2066 transitions. [2025-03-04 15:46:43,024 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 1328 [2025-03-04 15:46:43,024 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:43,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:43,025 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:43,025 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:43,025 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:46:43,025 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:46:43,025 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:43,026 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 6 times [2025-03-04 15:46:43,026 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:43,026 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252898883] [2025-03-04 15:46:43,026 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:46:43,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:43,029 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:43,030 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:43,030 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 15:46:43,030 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:43,030 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:46:43,031 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:43,032 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:43,032 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:43,032 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:43,033 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:46:43,033 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:43,033 INFO L85 PathProgramCache]: Analyzing trace with hash -282338272, now seen corresponding path program 1 times [2025-03-04 15:46:43,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:43,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213290868] [2025-03-04 15:46:43,034 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:43,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:43,037 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:46:43,039 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:46:43,039 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:43,039 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:46:43,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:46:43,064 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:46:43,064 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1213290868] [2025-03-04 15:46:43,064 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1213290868] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:46:43,064 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:46:43,064 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:46:43,064 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1587720367] [2025-03-04 15:46:43,064 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:46:43,064 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:46:43,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:46:43,064 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:46:43,064 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:46:43,065 INFO L87 Difference]: Start difference. First operand 1330 states and 2066 transitions. cyclomatic complexity: 768 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:43,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:46:43,089 INFO L93 Difference]: Finished difference Result 2626 states and 4034 transitions. [2025-03-04 15:46:43,089 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2626 states and 4034 transitions. [2025-03-04 15:46:43,106 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 2624 [2025-03-04 15:46:43,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2626 states to 2626 states and 4034 transitions. [2025-03-04 15:46:43,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2626 [2025-03-04 15:46:43,120 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2626 [2025-03-04 15:46:43,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2626 states and 4034 transitions. [2025-03-04 15:46:43,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:46:43,123 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2626 states and 4034 transitions. [2025-03-04 15:46:43,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2626 states and 4034 transitions. [2025-03-04 15:46:43,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2626 to 2626. [2025-03-04 15:46:43,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2626 states, 2626 states have (on average 1.5361766945925361) internal successors, (4034), 2625 states have internal predecessors, (4034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:43,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 4034 transitions. [2025-03-04 15:46:43,160 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2626 states and 4034 transitions. [2025-03-04 15:46:43,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:46:43,161 INFO L432 stractBuchiCegarLoop]: Abstraction has 2626 states and 4034 transitions. [2025-03-04 15:46:43,161 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-04 15:46:43,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2626 states and 4034 transitions. [2025-03-04 15:46:43,169 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 2624 [2025-03-04 15:46:43,169 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:43,169 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:43,170 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:43,170 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:43,170 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:46:43,170 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:46:43,170 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:43,170 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 7 times [2025-03-04 15:46:43,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:43,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289685460] [2025-03-04 15:46:43,171 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:46:43,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:43,173 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:43,174 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:43,174 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:43,174 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:43,174 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:46:43,176 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:43,176 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:43,176 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:43,176 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:43,177 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:46:43,178 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:43,178 INFO L85 PathProgramCache]: Analyzing trace with hash 962426209, now seen corresponding path program 1 times [2025-03-04 15:46:43,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:43,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298602414] [2025-03-04 15:46:43,178 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:43,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:43,182 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:46:43,185 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:46:43,185 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:43,185 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:46:43,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:46:43,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:46:43,207 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1298602414] [2025-03-04 15:46:43,207 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1298602414] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:46:43,207 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:46:43,207 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:46:43,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [28935339] [2025-03-04 15:46:43,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:46:43,207 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:46:43,207 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:46:43,207 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:46:43,207 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:46:43,208 INFO L87 Difference]: Start difference. First operand 2626 states and 4034 transitions. cyclomatic complexity: 1472 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:43,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:46:43,237 INFO L93 Difference]: Finished difference Result 5186 states and 7874 transitions. [2025-03-04 15:46:43,237 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5186 states and 7874 transitions. [2025-03-04 15:46:43,285 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 5184 [2025-03-04 15:46:43,300 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5186 states to 5186 states and 7874 transitions. [2025-03-04 15:46:43,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5186 [2025-03-04 15:46:43,303 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5186 [2025-03-04 15:46:43,303 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5186 states and 7874 transitions. [2025-03-04 15:46:43,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:46:43,308 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5186 states and 7874 transitions. [2025-03-04 15:46:43,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5186 states and 7874 transitions. [2025-03-04 15:46:43,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5186 to 5186. [2025-03-04 15:46:43,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5186 states, 5186 states have (on average 1.5183185499421519) internal successors, (7874), 5185 states have internal predecessors, (7874), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:43,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5186 states to 5186 states and 7874 transitions. [2025-03-04 15:46:43,386 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5186 states and 7874 transitions. [2025-03-04 15:46:43,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:46:43,388 INFO L432 stractBuchiCegarLoop]: Abstraction has 5186 states and 7874 transitions. [2025-03-04 15:46:43,388 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-04 15:46:43,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5186 states and 7874 transitions. [2025-03-04 15:46:43,408 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 5184 [2025-03-04 15:46:43,408 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:43,408 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:43,409 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:43,409 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:43,409 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:46:43,409 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:46:43,409 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:43,409 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 8 times [2025-03-04 15:46:43,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:43,409 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1173162826] [2025-03-04 15:46:43,409 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:46:43,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:43,411 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:43,412 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:43,412 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:46:43,412 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:43,412 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:46:43,416 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:43,417 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:43,417 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:43,417 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:43,419 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:46:43,419 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:43,420 INFO L85 PathProgramCache]: Analyzing trace with hash -1075630080, now seen corresponding path program 1 times [2025-03-04 15:46:43,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:43,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309301727] [2025-03-04 15:46:43,420 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:43,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:43,423 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:46:43,427 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:46:43,427 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:43,427 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:46:43,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:46:43,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:46:43,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309301727] [2025-03-04 15:46:43,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1309301727] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:46:43,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:46:43,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:46:43,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1633357072] [2025-03-04 15:46:43,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:46:43,443 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:46:43,444 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:46:43,444 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:46:43,444 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:46:43,444 INFO L87 Difference]: Start difference. First operand 5186 states and 7874 transitions. cyclomatic complexity: 2816 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:43,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:46:43,486 INFO L93 Difference]: Finished difference Result 10242 states and 15362 transitions. [2025-03-04 15:46:43,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10242 states and 15362 transitions. [2025-03-04 15:46:43,557 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 10240 [2025-03-04 15:46:43,588 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10242 states to 10242 states and 15362 transitions. [2025-03-04 15:46:43,588 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10242 [2025-03-04 15:46:43,593 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10242 [2025-03-04 15:46:43,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10242 states and 15362 transitions. [2025-03-04 15:46:43,603 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:46:43,603 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10242 states and 15362 transitions. [2025-03-04 15:46:43,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10242 states and 15362 transitions. [2025-03-04 15:46:43,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10242 to 10242. [2025-03-04 15:46:43,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10242 states, 10242 states have (on average 1.4999023628197619) internal successors, (15362), 10241 states have internal predecessors, (15362), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:43,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10242 states to 10242 states and 15362 transitions. [2025-03-04 15:46:43,766 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10242 states and 15362 transitions. [2025-03-04 15:46:43,767 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:46:43,769 INFO L432 stractBuchiCegarLoop]: Abstraction has 10242 states and 15362 transitions. [2025-03-04 15:46:43,770 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-04 15:46:43,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10242 states and 15362 transitions. [2025-03-04 15:46:43,795 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 10240 [2025-03-04 15:46:43,795 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:43,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:43,796 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:43,796 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:43,796 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:46:43,796 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:46:43,796 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:43,796 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 9 times [2025-03-04 15:46:43,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:43,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1087067870] [2025-03-04 15:46:43,797 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:46:43,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:43,799 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:43,799 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:43,799 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 15:46:43,800 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:43,800 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:46:43,800 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:43,802 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:43,802 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:43,802 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:43,804 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:46:43,806 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:43,806 INFO L85 PathProgramCache]: Analyzing trace with hash -864279167, now seen corresponding path program 1 times [2025-03-04 15:46:43,806 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:43,806 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524358750] [2025-03-04 15:46:43,806 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:43,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:43,810 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:46:43,811 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:46:43,813 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:43,813 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:46:43,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:46:43,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:46:43,825 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524358750] [2025-03-04 15:46:43,825 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [524358750] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:46:43,825 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:46:43,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:46:43,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934045264] [2025-03-04 15:46:43,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:46:43,826 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:46:43,826 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:46:43,826 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:46:43,826 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:46:43,827 INFO L87 Difference]: Start difference. First operand 10242 states and 15362 transitions. cyclomatic complexity: 5376 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:43,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:46:43,911 INFO L93 Difference]: Finished difference Result 20226 states and 29954 transitions. [2025-03-04 15:46:43,911 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20226 states and 29954 transitions. [2025-03-04 15:46:44,014 INFO L131 ngComponentsAnalysis]: Automaton has 512 accepting balls. 20224 [2025-03-04 15:46:44,106 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20226 states to 20226 states and 29954 transitions. [2025-03-04 15:46:44,106 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20226 [2025-03-04 15:46:44,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20226 [2025-03-04 15:46:44,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20226 states and 29954 transitions. [2025-03-04 15:46:44,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:46:44,142 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20226 states and 29954 transitions. [2025-03-04 15:46:44,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20226 states and 29954 transitions. [2025-03-04 15:46:44,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20226 to 20226. [2025-03-04 15:46:44,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20226 states, 20226 states have (on average 1.4809650944329082) internal successors, (29954), 20225 states have internal predecessors, (29954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:44,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20226 states to 20226 states and 29954 transitions. [2025-03-04 15:46:44,449 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20226 states and 29954 transitions. [2025-03-04 15:46:44,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:46:44,451 INFO L432 stractBuchiCegarLoop]: Abstraction has 20226 states and 29954 transitions. [2025-03-04 15:46:44,451 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-04 15:46:44,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20226 states and 29954 transitions. [2025-03-04 15:46:44,499 INFO L131 ngComponentsAnalysis]: Automaton has 512 accepting balls. 20224 [2025-03-04 15:46:44,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:44,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:44,499 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:44,499 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:44,500 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:46:44,500 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:46:44,500 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:44,500 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 10 times [2025-03-04 15:46:44,500 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:44,500 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760284185] [2025-03-04 15:46:44,501 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:46:44,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:44,504 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 15:46:44,506 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:44,506 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:46:44,506 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:44,507 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:46:44,507 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:44,508 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:44,508 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:44,508 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:44,509 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:46:44,512 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:44,512 INFO L85 PathProgramCache]: Analyzing trace with hash -1273103392, now seen corresponding path program 1 times [2025-03-04 15:46:44,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:44,512 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598958149] [2025-03-04 15:46:44,513 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:44,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:44,516 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:46:44,518 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:46:44,518 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:44,518 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:46:44,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:46:44,534 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:46:44,534 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598958149] [2025-03-04 15:46:44,534 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598958149] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:46:44,534 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:46:44,534 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:46:44,536 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2030531132] [2025-03-04 15:46:44,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:46:44,536 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:46:44,536 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:46:44,537 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:46:44,537 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:46:44,538 INFO L87 Difference]: Start difference. First operand 20226 states and 29954 transitions. cyclomatic complexity: 10240 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:44,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:46:44,682 INFO L93 Difference]: Finished difference Result 39938 states and 58370 transitions. [2025-03-04 15:46:44,682 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39938 states and 58370 transitions. [2025-03-04 15:46:44,884 INFO L131 ngComponentsAnalysis]: Automaton has 1024 accepting balls. 39936 [2025-03-04 15:46:44,984 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39938 states to 39938 states and 58370 transitions. [2025-03-04 15:46:44,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39938 [2025-03-04 15:46:45,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39938 [2025-03-04 15:46:45,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39938 states and 58370 transitions. [2025-03-04 15:46:45,088 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:46:45,089 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39938 states and 58370 transitions. [2025-03-04 15:46:45,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39938 states and 58370 transitions. [2025-03-04 15:46:45,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39938 to 39938. [2025-03-04 15:46:45,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39938 states, 39938 states have (on average 1.4615153487906254) internal successors, (58370), 39937 states have internal predecessors, (58370), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:45,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39938 states to 39938 states and 58370 transitions. [2025-03-04 15:46:45,767 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39938 states and 58370 transitions. [2025-03-04 15:46:45,768 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:46:45,769 INFO L432 stractBuchiCegarLoop]: Abstraction has 39938 states and 58370 transitions. [2025-03-04 15:46:45,769 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-04 15:46:45,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39938 states and 58370 transitions. [2025-03-04 15:46:45,889 INFO L131 ngComponentsAnalysis]: Automaton has 1024 accepting balls. 39936 [2025-03-04 15:46:45,889 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:45,889 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:45,890 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:45,890 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:45,890 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:46:45,891 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:46:45,891 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:45,891 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 11 times [2025-03-04 15:46:45,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:45,891 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175542788] [2025-03-04 15:46:45,891 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:46:45,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:45,895 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:45,898 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:45,898 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:46:45,899 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:45,899 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:46:45,900 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:45,901 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:45,901 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:45,902 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:45,903 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:46:45,904 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:45,904 INFO L85 PathProgramCache]: Analyzing trace with hash -2117575263, now seen corresponding path program 1 times [2025-03-04 15:46:45,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:45,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [880167561] [2025-03-04 15:46:45,904 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:45,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:45,908 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:46:45,909 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:46:45,910 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:45,910 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:46:45,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:46:45,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:46:45,927 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [880167561] [2025-03-04 15:46:45,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [880167561] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:46:45,928 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:46:45,928 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:46:45,928 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [939961124] [2025-03-04 15:46:45,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:46:45,928 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:46:45,928 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:46:45,930 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:46:45,930 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:46:45,930 INFO L87 Difference]: Start difference. First operand 39938 states and 58370 transitions. cyclomatic complexity: 19456 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:46,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:46:46,203 INFO L93 Difference]: Finished difference Result 78850 states and 113666 transitions. [2025-03-04 15:46:46,203 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78850 states and 113666 transitions. [2025-03-04 15:46:46,558 INFO L131 ngComponentsAnalysis]: Automaton has 2048 accepting balls. 78848 [2025-03-04 15:46:46,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78850 states to 78850 states and 113666 transitions. [2025-03-04 15:46:46,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78850 [2025-03-04 15:46:46,761 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78850 [2025-03-04 15:46:46,761 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78850 states and 113666 transitions. [2025-03-04 15:46:46,805 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:46:46,806 INFO L218 hiAutomatonCegarLoop]: Abstraction has 78850 states and 113666 transitions. [2025-03-04 15:46:46,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78850 states and 113666 transitions. [2025-03-04 15:46:47,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78850 to 78850. [2025-03-04 15:46:47,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78850 states, 78850 states have (on average 1.4415472415979709) internal successors, (113666), 78849 states have internal predecessors, (113666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:47,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78850 states to 78850 states and 113666 transitions. [2025-03-04 15:46:47,867 INFO L240 hiAutomatonCegarLoop]: Abstraction has 78850 states and 113666 transitions. [2025-03-04 15:46:47,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:46:47,868 INFO L432 stractBuchiCegarLoop]: Abstraction has 78850 states and 113666 transitions. [2025-03-04 15:46:47,868 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-04 15:46:47,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78850 states and 113666 transitions. [2025-03-04 15:46:48,201 INFO L131 ngComponentsAnalysis]: Automaton has 2048 accepting balls. 78848 [2025-03-04 15:46:48,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:48,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:48,207 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:48,207 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:48,208 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:46:48,208 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:46:48,208 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:48,208 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 12 times [2025-03-04 15:46:48,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:48,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544344741] [2025-03-04 15:46:48,208 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:46:48,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:48,213 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:48,221 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:48,221 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 15:46:48,221 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:48,221 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:46:48,222 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:48,223 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:48,223 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:48,223 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:48,224 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:46:48,227 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:48,227 INFO L85 PathProgramCache]: Analyzing trace with hash 1180319680, now seen corresponding path program 1 times [2025-03-04 15:46:48,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:48,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [128919819] [2025-03-04 15:46:48,231 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:48,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:48,234 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:46:48,235 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:46:48,238 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:48,238 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:46:48,257 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:46:48,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:46:48,258 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [128919819] [2025-03-04 15:46:48,258 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [128919819] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:46:48,258 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:46:48,258 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:46:48,258 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1897484369] [2025-03-04 15:46:48,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:46:48,258 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:46:48,259 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:46:48,260 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:46:48,260 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:46:48,260 INFO L87 Difference]: Start difference. First operand 78850 states and 113666 transitions. cyclomatic complexity: 36864 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:48,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:46:48,665 INFO L93 Difference]: Finished difference Result 155650 states and 221186 transitions. [2025-03-04 15:46:48,665 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155650 states and 221186 transitions. [2025-03-04 15:46:49,440 INFO L131 ngComponentsAnalysis]: Automaton has 4096 accepting balls. 155648 [2025-03-04 15:46:49,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155650 states to 155650 states and 221186 transitions. [2025-03-04 15:46:49,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 155650 [2025-03-04 15:46:49,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 155650 [2025-03-04 15:46:49,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 155650 states and 221186 transitions. [2025-03-04 15:46:49,936 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:46:49,936 INFO L218 hiAutomatonCegarLoop]: Abstraction has 155650 states and 221186 transitions. [2025-03-04 15:46:49,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155650 states and 221186 transitions. [2025-03-04 15:46:51,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155650 to 155650. [2025-03-04 15:46:51,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 155650 states, 155650 states have (on average 1.4210472213299068) internal successors, (221186), 155649 states have internal predecessors, (221186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:51,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155650 states to 155650 states and 221186 transitions. [2025-03-04 15:46:51,863 INFO L240 hiAutomatonCegarLoop]: Abstraction has 155650 states and 221186 transitions. [2025-03-04 15:46:51,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:46:51,864 INFO L432 stractBuchiCegarLoop]: Abstraction has 155650 states and 221186 transitions. [2025-03-04 15:46:51,864 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-04 15:46:51,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 155650 states and 221186 transitions. [2025-03-04 15:46:52,328 INFO L131 ngComponentsAnalysis]: Automaton has 4096 accepting balls. 155648 [2025-03-04 15:46:52,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:46:52,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:46:52,330 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:46:52,330 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:46:52,330 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:46:52,330 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:46:52,331 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:52,331 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 13 times [2025-03-04 15:46:52,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:52,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475191626] [2025-03-04 15:46:52,331 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:46:52,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:52,335 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:52,336 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:52,336 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:52,336 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:52,336 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:46:52,336 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:46:52,337 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:46:52,337 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:52,337 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:46:52,338 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:46:52,338 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:46:52,340 INFO L85 PathProgramCache]: Analyzing trace with hash -1761337919, now seen corresponding path program 1 times [2025-03-04 15:46:52,340 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:46:52,340 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782286271] [2025-03-04 15:46:52,340 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:46:52,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:46:52,343 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:46:52,344 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:46:52,344 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:46:52,344 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:46:52,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:46:52,362 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:46:52,362 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782286271] [2025-03-04 15:46:52,362 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [782286271] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:46:52,362 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:46:52,363 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:46:52,363 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1220291758] [2025-03-04 15:46:52,363 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:46:52,364 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:46:52,364 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:46:52,364 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:46:52,364 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:46:52,364 INFO L87 Difference]: Start difference. First operand 155650 states and 221186 transitions. cyclomatic complexity: 69632 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:53,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:46:53,190 INFO L93 Difference]: Finished difference Result 307202 states and 430082 transitions. [2025-03-04 15:46:53,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 307202 states and 430082 transitions. [2025-03-04 15:46:54,620 INFO L131 ngComponentsAnalysis]: Automaton has 8192 accepting balls. 307200 [2025-03-04 15:46:55,364 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 307202 states to 307202 states and 430082 transitions. [2025-03-04 15:46:55,364 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 307202 [2025-03-04 15:46:55,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 307202 [2025-03-04 15:46:55,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 307202 states and 430082 transitions. [2025-03-04 15:46:55,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:46:55,590 INFO L218 hiAutomatonCegarLoop]: Abstraction has 307202 states and 430082 transitions. [2025-03-04 15:46:55,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307202 states and 430082 transitions. [2025-03-04 15:46:58,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307202 to 307202. [2025-03-04 15:46:58,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 307202 states, 307202 states have (on average 1.3999973958502874) internal successors, (430082), 307201 states have internal predecessors, (430082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:46:59,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307202 states to 307202 states and 430082 transitions. [2025-03-04 15:46:59,220 INFO L240 hiAutomatonCegarLoop]: Abstraction has 307202 states and 430082 transitions. [2025-03-04 15:46:59,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:46:59,220 INFO L432 stractBuchiCegarLoop]: Abstraction has 307202 states and 430082 transitions. [2025-03-04 15:46:59,220 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-04 15:46:59,221 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 307202 states and 430082 transitions. [2025-03-04 15:47:00,382 INFO L131 ngComponentsAnalysis]: Automaton has 8192 accepting balls. 307200 [2025-03-04 15:47:00,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:47:00,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:47:00,387 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:47:00,387 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:47:00,387 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:47:00,387 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:47:00,387 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:47:00,387 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 14 times [2025-03-04 15:47:00,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:47:00,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088558040] [2025-03-04 15:47:00,387 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:47:00,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:47:00,391 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:47:00,392 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:47:00,393 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:47:00,393 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:47:00,393 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:47:00,394 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:47:00,394 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:47:00,394 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:47:00,395 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:47:00,396 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:47:00,397 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:47:00,397 INFO L85 PathProgramCache]: Analyzing trace with hash 2023095200, now seen corresponding path program 1 times [2025-03-04 15:47:00,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:47:00,397 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1537842408] [2025-03-04 15:47:00,397 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:47:00,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:47:00,399 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:47:00,400 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:47:00,400 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:47:00,400 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:47:00,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:47:00,413 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:47:00,413 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1537842408] [2025-03-04 15:47:00,413 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1537842408] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:47:00,413 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:47:00,413 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 15:47:00,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [799685035] [2025-03-04 15:47:00,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:47:00,413 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 15:47:00,414 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:47:00,414 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 15:47:00,414 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 15:47:00,414 INFO L87 Difference]: Start difference. First operand 307202 states and 430082 transitions. cyclomatic complexity: 131072 Second operand has 3 states, 2 states have (on average 15.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:47:02,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:47:02,098 INFO L93 Difference]: Finished difference Result 606210 states and 835586 transitions. [2025-03-04 15:47:02,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606210 states and 835586 transitions. [2025-03-04 15:47:05,283 INFO L131 ngComponentsAnalysis]: Automaton has 16384 accepting balls. 606208 [2025-03-04 15:47:06,790 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606210 states to 606210 states and 835586 transitions. [2025-03-04 15:47:06,790 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606210 [2025-03-04 15:47:07,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606210 [2025-03-04 15:47:07,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606210 states and 835586 transitions. [2025-03-04 15:47:07,239 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:47:07,239 INFO L218 hiAutomatonCegarLoop]: Abstraction has 606210 states and 835586 transitions. [2025-03-04 15:47:07,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606210 states and 835586 transitions. [2025-03-04 15:47:12,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606210 to 606210. [2025-03-04 15:47:12,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 606210 states, 606210 states have (on average 1.3783771300374457) internal successors, (835586), 606209 states have internal predecessors, (835586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:47:14,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606210 states to 606210 states and 835586 transitions. [2025-03-04 15:47:14,733 INFO L240 hiAutomatonCegarLoop]: Abstraction has 606210 states and 835586 transitions. [2025-03-04 15:47:14,734 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 15:47:14,735 INFO L432 stractBuchiCegarLoop]: Abstraction has 606210 states and 835586 transitions. [2025-03-04 15:47:14,735 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-04 15:47:14,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606210 states and 835586 transitions. [2025-03-04 15:47:16,608 INFO L131 ngComponentsAnalysis]: Automaton has 16384 accepting balls. 606208 [2025-03-04 15:47:16,608 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:47:16,608 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:47:16,615 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 15:47:16,615 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:47:16,616 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-03-04 15:47:16,616 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-03-04 15:47:16,616 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:47:16,616 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 15 times [2025-03-04 15:47:16,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:47:16,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550046522] [2025-03-04 15:47:16,616 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:47:16,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:47:16,618 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:47:16,619 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:47:16,619 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 15:47:16,619 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:47:16,620 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:47:16,620 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:47:16,621 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:47:16,621 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:47:16,621 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:47:16,623 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:47:16,623 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:47:16,624 INFO L85 PathProgramCache]: Analyzing trace with hash -764320287, now seen corresponding path program 1 times [2025-03-04 15:47:16,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:47:16,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2077782070] [2025-03-04 15:47:16,624 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:47:16,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:47:16,626 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:47:16,627 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:47:16,627 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:47:16,627 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:47:16,627 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:47:16,628 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 15:47:16,628 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 15:47:16,628 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:47:16,629 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:47:16,633 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:47:16,633 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:47:16,634 INFO L85 PathProgramCache]: Analyzing trace with hash 271057632, now seen corresponding path program 1 times [2025-03-04 15:47:16,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:47:16,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1832465118] [2025-03-04 15:47:16,634 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:47:16,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:47:16,636 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-03-04 15:47:16,638 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-03-04 15:47:16,638 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:47:16,638 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:47:16,638 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:47:16,639 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-03-04 15:47:16,640 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-03-04 15:47:16,640 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:47:16,640 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:47:16,643 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:47:17,080 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:47:17,081 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:47:17,081 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:47:17,081 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:47:17,081 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:47:17,085 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:47:17,086 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:47:17,086 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:47:17,086 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:47:17,116 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 04.03 03:47:17 BoogieIcfgContainer [2025-03-04 15:47:17,116 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-04 15:47:17,116 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-04 15:47:17,116 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-04 15:47:17,117 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-04 15:47:17,117 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 03:46:42" (3/4) ... [2025-03-04 15:47:17,119 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-03-04 15:47:17,141 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-04 15:47:17,141 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-04 15:47:17,142 INFO L158 Benchmark]: Toolchain (without parser) took 35451.54ms. Allocated memory was 167.8MB in the beginning and 13.4GB in the end (delta: 13.2GB). Free memory was 130.2MB in the beginning and 8.2GB in the end (delta: -8.1GB). Peak memory consumption was 5.1GB. Max. memory is 16.1GB. [2025-03-04 15:47:17,142 INFO L158 Benchmark]: CDTParser took 0.12ms. Allocated memory is still 192.9MB. Free memory is still 119.2MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 15:47:17,142 INFO L158 Benchmark]: CACSL2BoogieTranslator took 145.61ms. Allocated memory is still 167.8MB. Free memory was 130.2MB in the beginning and 118.4MB in the end (delta: 11.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 15:47:17,142 INFO L158 Benchmark]: Boogie Procedure Inliner took 20.33ms. Allocated memory is still 167.8MB. Free memory was 118.4MB in the beginning and 116.9MB in the end (delta: 1.5MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 15:47:17,142 INFO L158 Benchmark]: Boogie Preprocessor took 20.40ms. Allocated memory is still 167.8MB. Free memory was 116.9MB in the beginning and 115.5MB in the end (delta: 1.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 15:47:17,143 INFO L158 Benchmark]: IcfgBuilder took 273.93ms. Allocated memory is still 167.8MB. Free memory was 115.5MB in the beginning and 99.5MB in the end (delta: 16.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-04 15:47:17,143 INFO L158 Benchmark]: BuchiAutomizer took 34962.64ms. Allocated memory was 167.8MB in the beginning and 13.4GB in the end (delta: 13.2GB). Free memory was 99.5MB in the beginning and 8.2GB in the end (delta: -8.1GB). Peak memory consumption was 5.1GB. Max. memory is 16.1GB. [2025-03-04 15:47:17,143 INFO L158 Benchmark]: Witness Printer took 24.87ms. Allocated memory is still 13.4GB. Free memory was 8.2GB in the beginning and 8.2GB in the end (delta: 4.4MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 15:47:17,144 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12ms. Allocated memory is still 192.9MB. Free memory is still 119.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 145.61ms. Allocated memory is still 167.8MB. Free memory was 130.2MB in the beginning and 118.4MB in the end (delta: 11.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 20.33ms. Allocated memory is still 167.8MB. Free memory was 118.4MB in the beginning and 116.9MB in the end (delta: 1.5MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 20.40ms. Allocated memory is still 167.8MB. Free memory was 116.9MB in the beginning and 115.5MB in the end (delta: 1.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * IcfgBuilder took 273.93ms. Allocated memory is still 167.8MB. Free memory was 115.5MB in the beginning and 99.5MB in the end (delta: 16.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 34962.64ms. Allocated memory was 167.8MB in the beginning and 13.4GB in the end (delta: 13.2GB). Free memory was 99.5MB in the beginning and 8.2GB in the end (delta: -8.1GB). Peak memory consumption was 5.1GB. Max. memory is 16.1GB. * Witness Printer took 24.87ms. Allocated memory is still 13.4GB. Free memory was 8.2GB in the beginning and 8.2GB in the end (delta: 4.4MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 14 terminating modules (14 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.14 modules have a trivial ranking function, the largest among these consists of 3 locations. The remainder module has 606210 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 34.9s and 15 iterations. TraceHistogramMax:1. Analysis of lassos took 1.2s. Construction of modules took 0.1s. Büchi inclusion checks took 29.4s. Highest rank in rank-based complementation 0. Minimization of det autom 14. Minimization of nondet autom 0. Automata minimization 15.5s AutomataMinimizationTime, 14 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations. Non-live state removal took 9.2s Buchi closure took 0.5s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 800 SdHoareTripleChecker+Valid, 0.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 800 mSDsluCounter, 2507 SdHoareTripleChecker+Invalid, 0.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 968 mSDsCounter, 28 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 72 IncrementalHoareTripleChecker+Invalid, 100 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 28 mSolverCounterUnsat, 1539 mSDtfsCounter, 72 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI14 SFLT0 conc0 concLT0 SILN0 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 53]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L8] int p1 = __VERIFIER_nondet_int(); [L9] int lk1; [L11] int p2 = __VERIFIER_nondet_int(); [L12] int lk2; [L14] int p3 = __VERIFIER_nondet_int(); [L15] int lk3; [L17] int p4 = __VERIFIER_nondet_int(); [L18] int lk4; [L20] int p5 = __VERIFIER_nondet_int(); [L21] int lk5; [L23] int p6 = __VERIFIER_nondet_int(); [L24] int lk6; [L26] int p7 = __VERIFIER_nondet_int(); [L27] int lk7; [L29] int p8 = __VERIFIER_nondet_int(); [L30] int lk8; [L32] int p9 = __VERIFIER_nondet_int(); [L33] int lk9; [L35] int p10 = __VERIFIER_nondet_int(); [L36] int lk10; [L38] int p11 = __VERIFIER_nondet_int(); [L39] int lk11; [L41] int p12 = __VERIFIER_nondet_int(); [L42] int lk12; [L44] int p13 = __VERIFIER_nondet_int(); [L45] int lk13; [L47] int p14 = __VERIFIER_nondet_int(); [L48] int lk14; [L51] int cond; Loop: [L53] COND TRUE 1 [L54] cond = __VERIFIER_nondet_int() [L55] COND FALSE !(cond == 0) [L58] lk1 = 0 [L60] lk2 = 0 [L62] lk3 = 0 [L64] lk4 = 0 [L66] lk5 = 0 [L68] lk6 = 0 [L70] lk7 = 0 [L72] lk8 = 0 [L74] lk9 = 0 [L76] lk10 = 0 [L78] lk11 = 0 [L80] lk12 = 0 [L82] lk13 = 0 [L84] lk14 = 0 [L88] COND FALSE !(p1 != 0) [L92] COND FALSE !(p2 != 0) [L96] COND FALSE !(p3 != 0) [L100] COND FALSE !(p4 != 0) [L104] COND FALSE !(p5 != 0) [L108] COND FALSE !(p6 != 0) [L112] COND FALSE !(p7 != 0) [L116] COND FALSE !(p8 != 0) [L120] COND FALSE !(p9 != 0) [L124] COND FALSE !(p10 != 0) [L128] COND FALSE !(p11 != 0) [L132] COND FALSE !(p12 != 0) [L136] COND FALSE !(p13 != 0) [L140] COND FALSE !(p14 != 0) [L146] COND FALSE !(p1 != 0) [L151] COND FALSE !(p2 != 0) [L156] COND FALSE !(p3 != 0) [L161] COND FALSE !(p4 != 0) [L166] COND FALSE !(p5 != 0) [L171] COND FALSE !(p6 != 0) [L176] COND FALSE !(p7 != 0) [L181] COND FALSE !(p8 != 0) [L186] COND FALSE !(p9 != 0) [L191] COND FALSE !(p10 != 0) [L196] COND FALSE !(p11 != 0) [L201] COND FALSE !(p12 != 0) [L206] COND FALSE !(p13 != 0) [L211] COND FALSE !(p14 != 0) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 53]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L8] int p1 = __VERIFIER_nondet_int(); [L9] int lk1; [L11] int p2 = __VERIFIER_nondet_int(); [L12] int lk2; [L14] int p3 = __VERIFIER_nondet_int(); [L15] int lk3; [L17] int p4 = __VERIFIER_nondet_int(); [L18] int lk4; [L20] int p5 = __VERIFIER_nondet_int(); [L21] int lk5; [L23] int p6 = __VERIFIER_nondet_int(); [L24] int lk6; [L26] int p7 = __VERIFIER_nondet_int(); [L27] int lk7; [L29] int p8 = __VERIFIER_nondet_int(); [L30] int lk8; [L32] int p9 = __VERIFIER_nondet_int(); [L33] int lk9; [L35] int p10 = __VERIFIER_nondet_int(); [L36] int lk10; [L38] int p11 = __VERIFIER_nondet_int(); [L39] int lk11; [L41] int p12 = __VERIFIER_nondet_int(); [L42] int lk12; [L44] int p13 = __VERIFIER_nondet_int(); [L45] int lk13; [L47] int p14 = __VERIFIER_nondet_int(); [L48] int lk14; [L51] int cond; Loop: [L53] COND TRUE 1 [L54] cond = __VERIFIER_nondet_int() [L55] COND FALSE !(cond == 0) [L58] lk1 = 0 [L60] lk2 = 0 [L62] lk3 = 0 [L64] lk4 = 0 [L66] lk5 = 0 [L68] lk6 = 0 [L70] lk7 = 0 [L72] lk8 = 0 [L74] lk9 = 0 [L76] lk10 = 0 [L78] lk11 = 0 [L80] lk12 = 0 [L82] lk13 = 0 [L84] lk14 = 0 [L88] COND FALSE !(p1 != 0) [L92] COND FALSE !(p2 != 0) [L96] COND FALSE !(p3 != 0) [L100] COND FALSE !(p4 != 0) [L104] COND FALSE !(p5 != 0) [L108] COND FALSE !(p6 != 0) [L112] COND FALSE !(p7 != 0) [L116] COND FALSE !(p8 != 0) [L120] COND FALSE !(p9 != 0) [L124] COND FALSE !(p10 != 0) [L128] COND FALSE !(p11 != 0) [L132] COND FALSE !(p12 != 0) [L136] COND FALSE !(p13 != 0) [L140] COND FALSE !(p14 != 0) [L146] COND FALSE !(p1 != 0) [L151] COND FALSE !(p2 != 0) [L156] COND FALSE !(p3 != 0) [L161] COND FALSE !(p4 != 0) [L166] COND FALSE !(p5 != 0) [L171] COND FALSE !(p6 != 0) [L176] COND FALSE !(p7 != 0) [L181] COND FALSE !(p8 != 0) [L186] COND FALSE !(p9 != 0) [L191] COND FALSE !(p10 != 0) [L196] COND FALSE !(p11 != 0) [L201] COND FALSE !(p12 != 0) [L206] COND FALSE !(p13 != 0) [L211] COND FALSE !(p14 != 0) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-03-04 15:47:17,157 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)