./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/toy2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/toy2.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a77d6f304c19846fdc8cd5bba9216d69953659ded966cffbf7faa285e2d864a4 --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 16:21:31,088 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 16:21:31,138 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-04 16:21:31,145 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 16:21:31,145 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 16:21:31,145 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 16:21:31,164 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 16:21:31,165 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 16:21:31,165 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 16:21:31,165 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 16:21:31,166 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 16:21:31,167 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 16:21:31,167 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 16:21:31,167 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 16:21:31,167 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 16:21:31,168 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 16:21:31,168 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 16:21:31,168 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 16:21:31,168 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 16:21:31,168 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 16:21:31,168 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 16:21:31,168 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 16:21:31,168 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-04 16:21:31,168 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 16:21:31,168 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-04 16:21:31,168 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 16:21:31,168 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 16:21:31,169 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 16:21:31,169 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 16:21:31,169 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 16:21:31,169 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-04 16:21:31,169 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 16:21:31,169 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 16:21:31,169 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 16:21:31,169 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 16:21:31,169 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 16:21:31,169 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 16:21:31,170 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 16:21:31,170 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 16:21:31,170 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 16:21:31,170 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a77d6f304c19846fdc8cd5bba9216d69953659ded966cffbf7faa285e2d864a4 [2025-03-04 16:21:31,456 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 16:21:31,462 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 16:21:31,464 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 16:21:31,465 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 16:21:31,465 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 16:21:31,466 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/toy2.cil.c [2025-03-04 16:21:32,652 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/59d637b84/2c8d20277fe2439da68ab77539d77996/FLAG4934455f6 [2025-03-04 16:21:32,883 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 16:21:32,885 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/toy2.cil.c [2025-03-04 16:21:32,897 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/59d637b84/2c8d20277fe2439da68ab77539d77996/FLAG4934455f6 [2025-03-04 16:21:32,914 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/59d637b84/2c8d20277fe2439da68ab77539d77996 [2025-03-04 16:21:32,917 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 16:21:32,918 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 16:21:32,920 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 16:21:32,920 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 16:21:32,923 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 16:21:32,924 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:21:32" (1/1) ... [2025-03-04 16:21:32,926 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2e76790c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:32, skipping insertion in model container [2025-03-04 16:21:32,926 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:21:32" (1/1) ... [2025-03-04 16:21:32,949 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 16:21:33,109 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:21:33,124 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 16:21:33,163 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:21:33,177 INFO L204 MainTranslator]: Completed translation [2025-03-04 16:21:33,178 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33 WrapperNode [2025-03-04 16:21:33,178 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 16:21:33,179 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 16:21:33,179 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 16:21:33,179 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 16:21:33,183 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33" (1/1) ... [2025-03-04 16:21:33,196 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33" (1/1) ... [2025-03-04 16:21:33,215 INFO L138 Inliner]: procedures = 20, calls = 16, calls flagged for inlining = 11, calls inlined = 11, statements flattened = 343 [2025-03-04 16:21:33,215 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 16:21:33,216 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 16:21:33,216 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 16:21:33,216 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 16:21:33,224 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33" (1/1) ... [2025-03-04 16:21:33,224 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33" (1/1) ... [2025-03-04 16:21:33,226 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33" (1/1) ... [2025-03-04 16:21:33,244 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-04 16:21:33,249 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33" (1/1) ... [2025-03-04 16:21:33,249 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33" (1/1) ... [2025-03-04 16:21:33,252 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33" (1/1) ... [2025-03-04 16:21:33,253 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33" (1/1) ... [2025-03-04 16:21:33,257 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33" (1/1) ... [2025-03-04 16:21:33,258 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33" (1/1) ... [2025-03-04 16:21:33,259 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 16:21:33,264 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 16:21:33,264 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 16:21:33,264 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 16:21:33,265 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33" (1/1) ... [2025-03-04 16:21:33,269 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:21:33,278 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:21:33,293 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:21:33,296 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 16:21:33,316 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-04 16:21:33,317 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-04 16:21:33,317 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 16:21:33,317 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 16:21:33,383 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 16:21:33,384 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 16:21:33,766 INFO L? ?]: Removed 20 outVars from TransFormulas that were not future-live. [2025-03-04 16:21:33,766 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 16:21:33,779 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 16:21:33,780 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-04 16:21:33,781 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:21:33 BoogieIcfgContainer [2025-03-04 16:21:33,781 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 16:21:33,782 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 16:21:33,782 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 16:21:33,786 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 16:21:33,787 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:21:33,787 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 04:21:32" (1/3) ... [2025-03-04 16:21:33,788 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@104e3895 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:21:33, skipping insertion in model container [2025-03-04 16:21:33,789 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:21:33,789 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:33" (2/3) ... [2025-03-04 16:21:33,789 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@104e3895 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:21:33, skipping insertion in model container [2025-03-04 16:21:33,789 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:21:33,789 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:21:33" (3/3) ... [2025-03-04 16:21:33,790 INFO L363 chiAutomizerObserver]: Analyzing ICFG toy2.cil.c [2025-03-04 16:21:33,839 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 16:21:33,840 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 16:21:33,840 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 16:21:33,840 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 16:21:33,840 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 16:21:33,841 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 16:21:33,841 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 16:21:33,841 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 16:21:33,847 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 135 states, 134 states have (on average 1.7537313432835822) internal successors, (235), 134 states have internal predecessors, (235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:33,865 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2025-03-04 16:21:33,866 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:33,866 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:33,874 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:33,875 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:33,875 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 16:21:33,877 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 135 states, 134 states have (on average 1.7537313432835822) internal successors, (235), 134 states have internal predecessors, (235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:33,881 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2025-03-04 16:21:33,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:33,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:33,885 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:33,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:33,894 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume !(1 == ~wl_i~0);~wl_st~0 := 2;" "assume !(1 == ~c1_i~0);~c1_st~0 := 2;" "assume !(1 == ~c2_i~0);~c2_st~0 := 2;" "assume !(1 == ~wb_i~0);~wb_st~0 := 2;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-03-04 16:21:33,894 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !true;" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:33,899 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:33,900 INFO L85 PathProgramCache]: Analyzing trace with hash 1320311430, now seen corresponding path program 1 times [2025-03-04 16:21:33,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:33,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58443582] [2025-03-04 16:21:33,908 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:33,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:33,969 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:33,990 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:33,991 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:33,991 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,121 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58443582] [2025-03-04 16:21:34,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58443582] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:34,123 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496539883] [2025-03-04 16:21:34,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,126 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:21:34,126 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:34,126 INFO L85 PathProgramCache]: Analyzing trace with hash -1426895027, now seen corresponding path program 1 times [2025-03-04 16:21:34,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:34,126 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1931381080] [2025-03-04 16:21:34,126 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:34,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:34,133 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes. [2025-03-04 16:21:34,135 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements. [2025-03-04 16:21:34,135 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:34,135 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,149 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,150 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1931381080] [2025-03-04 16:21:34,150 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1931381080] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,150 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:21:34,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915607540] [2025-03-04 16:21:34,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,151 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:34,152 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:34,168 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-04 16:21:34,169 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-04 16:21:34,170 INFO L87 Difference]: Start difference. First operand has 135 states, 134 states have (on average 1.7537313432835822) internal successors, (235), 134 states have internal predecessors, (235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 11.5) internal successors, (23), 2 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:34,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:34,181 INFO L93 Difference]: Finished difference Result 133 states and 226 transitions. [2025-03-04 16:21:34,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 133 states and 226 transitions. [2025-03-04 16:21:34,184 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-04 16:21:34,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 133 states to 128 states and 221 transitions. [2025-03-04 16:21:34,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2025-03-04 16:21:34,194 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2025-03-04 16:21:34,195 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 221 transitions. [2025-03-04 16:21:34,195 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:34,195 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 221 transitions. [2025-03-04 16:21:34,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 221 transitions. [2025-03-04 16:21:34,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2025-03-04 16:21:34,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.7265625) internal successors, (221), 127 states have internal predecessors, (221), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:34,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 221 transitions. [2025-03-04 16:21:34,223 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 221 transitions. [2025-03-04 16:21:34,223 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-04 16:21:34,225 INFO L432 stractBuchiCegarLoop]: Abstraction has 128 states and 221 transitions. [2025-03-04 16:21:34,227 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 16:21:34,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 221 transitions. [2025-03-04 16:21:34,229 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-04 16:21:34,229 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:34,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:34,233 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:34,233 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:34,233 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume !(1 == ~wl_i~0);~wl_st~0 := 2;" "assume !(1 == ~c1_i~0);~c1_st~0 := 2;" "assume !(1 == ~c2_i~0);~c2_st~0 := 2;" "assume !(1 == ~wb_i~0);~wb_st~0 := 2;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-03-04 16:21:34,234 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:34,234 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:34,234 INFO L85 PathProgramCache]: Analyzing trace with hash 1320311430, now seen corresponding path program 2 times [2025-03-04 16:21:34,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:34,234 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591659853] [2025-03-04 16:21:34,235 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:21:34,235 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:34,248 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:34,253 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:34,253 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:21:34,253 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,313 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [591659853] [2025-03-04 16:21:34,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [591659853] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,313 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,314 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:34,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [192044593] [2025-03-04 16:21:34,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,314 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:21:34,314 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:34,314 INFO L85 PathProgramCache]: Analyzing trace with hash 347199293, now seen corresponding path program 1 times [2025-03-04 16:21:34,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:34,314 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134466417] [2025-03-04 16:21:34,315 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:34,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:34,319 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:21:34,322 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:21:34,322 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:34,322 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,339 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,339 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1134466417] [2025-03-04 16:21:34,339 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1134466417] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,339 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,339 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:34,339 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1284046097] [2025-03-04 16:21:34,339 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,339 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:34,340 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:34,340 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:21:34,340 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:21:34,340 INFO L87 Difference]: Start difference. First operand 128 states and 221 transitions. cyclomatic complexity: 94 Second operand has 3 states, 3 states have (on average 8.0) internal successors, (24), 3 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:34,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:34,356 INFO L93 Difference]: Finished difference Result 128 states and 220 transitions. [2025-03-04 16:21:34,356 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 220 transitions. [2025-03-04 16:21:34,357 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-04 16:21:34,358 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 128 states and 220 transitions. [2025-03-04 16:21:34,358 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2025-03-04 16:21:34,359 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2025-03-04 16:21:34,359 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 220 transitions. [2025-03-04 16:21:34,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:34,360 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 220 transitions. [2025-03-04 16:21:34,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 220 transitions. [2025-03-04 16:21:34,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2025-03-04 16:21:34,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.71875) internal successors, (220), 127 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:34,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 220 transitions. [2025-03-04 16:21:34,365 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 220 transitions. [2025-03-04 16:21:34,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:21:34,366 INFO L432 stractBuchiCegarLoop]: Abstraction has 128 states and 220 transitions. [2025-03-04 16:21:34,366 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 16:21:34,366 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 220 transitions. [2025-03-04 16:21:34,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-04 16:21:34,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:34,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:34,368 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:34,368 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:34,368 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume !(1 == ~c1_i~0);~c1_st~0 := 2;" "assume !(1 == ~c2_i~0);~c2_st~0 := 2;" "assume !(1 == ~wb_i~0);~wb_st~0 := 2;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-03-04 16:21:34,368 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:34,369 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:34,369 INFO L85 PathProgramCache]: Analyzing trace with hash 1108960517, now seen corresponding path program 1 times [2025-03-04 16:21:34,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:34,369 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735554476] [2025-03-04 16:21:34,369 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:34,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:34,377 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:34,398 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:34,398 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:34,398 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,440 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1735554476] [2025-03-04 16:21:34,440 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1735554476] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,440 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,440 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:34,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [488748842] [2025-03-04 16:21:34,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,440 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:21:34,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:34,440 INFO L85 PathProgramCache]: Analyzing trace with hash -1715491550, now seen corresponding path program 1 times [2025-03-04 16:21:34,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:34,441 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361650188] [2025-03-04 16:21:34,441 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:34,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:34,450 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:21:34,452 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:21:34,452 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:34,452 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,475 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,475 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [361650188] [2025-03-04 16:21:34,475 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [361650188] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,475 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,475 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:34,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1499794235] [2025-03-04 16:21:34,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,476 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:34,476 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:34,476 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:21:34,476 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:21:34,476 INFO L87 Difference]: Start difference. First operand 128 states and 220 transitions. cyclomatic complexity: 93 Second operand has 3 states, 3 states have (on average 8.0) internal successors, (24), 3 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:34,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:34,486 INFO L93 Difference]: Finished difference Result 128 states and 219 transitions. [2025-03-04 16:21:34,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 219 transitions. [2025-03-04 16:21:34,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-04 16:21:34,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 128 states and 219 transitions. [2025-03-04 16:21:34,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2025-03-04 16:21:34,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2025-03-04 16:21:34,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 219 transitions. [2025-03-04 16:21:34,489 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:34,489 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 219 transitions. [2025-03-04 16:21:34,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 219 transitions. [2025-03-04 16:21:34,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2025-03-04 16:21:34,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.7109375) internal successors, (219), 127 states have internal predecessors, (219), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:34,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 219 transitions. [2025-03-04 16:21:34,493 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 219 transitions. [2025-03-04 16:21:34,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:21:34,494 INFO L432 stractBuchiCegarLoop]: Abstraction has 128 states and 219 transitions. [2025-03-04 16:21:34,494 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 16:21:34,494 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 219 transitions. [2025-03-04 16:21:34,495 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-04 16:21:34,495 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:34,495 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:34,495 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:34,495 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:34,495 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume !(1 == ~c2_i~0);~c2_st~0 := 2;" "assume !(1 == ~wb_i~0);~wb_st~0 := 2;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-03-04 16:21:34,496 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:34,496 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:34,496 INFO L85 PathProgramCache]: Analyzing trace with hash 1517784742, now seen corresponding path program 1 times [2025-03-04 16:21:34,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:34,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [988296115] [2025-03-04 16:21:34,497 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:34,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:34,502 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:34,504 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:34,504 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:34,504 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,529 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,529 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [988296115] [2025-03-04 16:21:34,529 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [988296115] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,529 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,529 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:34,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1839109674] [2025-03-04 16:21:34,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,529 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:21:34,530 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:34,530 INFO L85 PathProgramCache]: Analyzing trace with hash 347199293, now seen corresponding path program 2 times [2025-03-04 16:21:34,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:34,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105424423] [2025-03-04 16:21:34,530 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:21:34,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:34,534 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:21:34,536 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:21:34,536 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:21:34,536 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,558 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2105424423] [2025-03-04 16:21:34,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2105424423] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,558 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,558 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:34,558 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635185333] [2025-03-04 16:21:34,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,558 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:34,559 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:34,559 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:21:34,559 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:21:34,559 INFO L87 Difference]: Start difference. First operand 128 states and 219 transitions. cyclomatic complexity: 92 Second operand has 3 states, 3 states have (on average 8.0) internal successors, (24), 3 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:34,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:34,570 INFO L93 Difference]: Finished difference Result 128 states and 218 transitions. [2025-03-04 16:21:34,570 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 218 transitions. [2025-03-04 16:21:34,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-04 16:21:34,572 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 128 states and 218 transitions. [2025-03-04 16:21:34,572 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2025-03-04 16:21:34,573 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2025-03-04 16:21:34,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 218 transitions. [2025-03-04 16:21:34,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:34,573 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 218 transitions. [2025-03-04 16:21:34,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 218 transitions. [2025-03-04 16:21:34,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2025-03-04 16:21:34,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.703125) internal successors, (218), 127 states have internal predecessors, (218), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:34,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 218 transitions. [2025-03-04 16:21:34,577 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 218 transitions. [2025-03-04 16:21:34,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:21:34,578 INFO L432 stractBuchiCegarLoop]: Abstraction has 128 states and 218 transitions. [2025-03-04 16:21:34,578 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 16:21:34,578 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 218 transitions. [2025-03-04 16:21:34,579 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-04 16:21:34,579 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:34,579 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:34,582 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:34,582 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:34,582 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume !(1 == ~wb_i~0);~wb_st~0 := 2;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-03-04 16:21:34,582 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:34,583 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:34,583 INFO L85 PathProgramCache]: Analyzing trace with hash -1932710683, now seen corresponding path program 1 times [2025-03-04 16:21:34,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:34,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342406315] [2025-03-04 16:21:34,583 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:34,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:34,588 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:34,590 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:34,590 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:34,590 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,613 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,613 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1342406315] [2025-03-04 16:21:34,613 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1342406315] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,613 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,613 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:34,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840531770] [2025-03-04 16:21:34,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,614 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:21:34,614 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:34,614 INFO L85 PathProgramCache]: Analyzing trace with hash 347199293, now seen corresponding path program 3 times [2025-03-04 16:21:34,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:34,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381427620] [2025-03-04 16:21:34,616 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:21:34,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:34,623 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:21:34,628 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:21:34,630 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:21:34,631 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,651 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1381427620] [2025-03-04 16:21:34,651 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1381427620] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,651 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,651 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:34,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1267004906] [2025-03-04 16:21:34,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,651 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:34,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:34,651 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:21:34,651 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:21:34,652 INFO L87 Difference]: Start difference. First operand 128 states and 218 transitions. cyclomatic complexity: 91 Second operand has 3 states, 3 states have (on average 8.0) internal successors, (24), 3 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:34,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:34,664 INFO L93 Difference]: Finished difference Result 128 states and 217 transitions. [2025-03-04 16:21:34,666 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 217 transitions. [2025-03-04 16:21:34,667 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-04 16:21:34,667 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 128 states and 217 transitions. [2025-03-04 16:21:34,667 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2025-03-04 16:21:34,668 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2025-03-04 16:21:34,668 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 217 transitions. [2025-03-04 16:21:34,668 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:34,668 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 217 transitions. [2025-03-04 16:21:34,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 217 transitions. [2025-03-04 16:21:34,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2025-03-04 16:21:34,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.6953125) internal successors, (217), 127 states have internal predecessors, (217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:34,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 217 transitions. [2025-03-04 16:21:34,673 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 217 transitions. [2025-03-04 16:21:34,673 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:21:34,674 INFO L432 stractBuchiCegarLoop]: Abstraction has 128 states and 217 transitions. [2025-03-04 16:21:34,674 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 16:21:34,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 217 transitions. [2025-03-04 16:21:34,675 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-04 16:21:34,675 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:34,675 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:34,675 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:34,675 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:34,676 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-03-04 16:21:34,676 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:34,676 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:34,676 INFO L85 PathProgramCache]: Analyzing trace with hash -935638330, now seen corresponding path program 1 times [2025-03-04 16:21:34,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:34,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971707233] [2025-03-04 16:21:34,676 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:34,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:34,681 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:34,683 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:34,683 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:34,683 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,726 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,726 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971707233] [2025-03-04 16:21:34,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1971707233] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,726 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,726 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:21:34,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1482736402] [2025-03-04 16:21:34,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,727 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:21:34,727 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:34,727 INFO L85 PathProgramCache]: Analyzing trace with hash 347199293, now seen corresponding path program 4 times [2025-03-04 16:21:34,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:34,727 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [182090157] [2025-03-04 16:21:34,727 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:21:34,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:34,731 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 28 statements into 2 equivalence classes. [2025-03-04 16:21:34,733 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:21:34,733 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-03-04 16:21:34,733 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,746 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [182090157] [2025-03-04 16:21:34,746 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [182090157] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,746 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,746 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:34,746 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953977750] [2025-03-04 16:21:34,746 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,746 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:34,746 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:34,746 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:21:34,746 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:21:34,747 INFO L87 Difference]: Start difference. First operand 128 states and 217 transitions. cyclomatic complexity: 90 Second operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:34,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:34,845 INFO L93 Difference]: Finished difference Result 218 states and 363 transitions. [2025-03-04 16:21:34,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 218 states and 363 transitions. [2025-03-04 16:21:34,846 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 178 [2025-03-04 16:21:34,847 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 218 states to 218 states and 363 transitions. [2025-03-04 16:21:34,847 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 218 [2025-03-04 16:21:34,848 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 218 [2025-03-04 16:21:34,848 INFO L73 IsDeterministic]: Start isDeterministic. Operand 218 states and 363 transitions. [2025-03-04 16:21:34,848 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:34,848 INFO L218 hiAutomatonCegarLoop]: Abstraction has 218 states and 363 transitions. [2025-03-04 16:21:34,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states and 363 transitions. [2025-03-04 16:21:34,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 213. [2025-03-04 16:21:34,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 213 states, 213 states have (on average 1.6807511737089202) internal successors, (358), 212 states have internal predecessors, (358), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:34,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 358 transitions. [2025-03-04 16:21:34,860 INFO L240 hiAutomatonCegarLoop]: Abstraction has 213 states and 358 transitions. [2025-03-04 16:21:34,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:21:34,863 INFO L432 stractBuchiCegarLoop]: Abstraction has 213 states and 358 transitions. [2025-03-04 16:21:34,864 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-04 16:21:34,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 213 states and 358 transitions. [2025-03-04 16:21:34,865 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 178 [2025-03-04 16:21:34,865 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:34,865 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:34,866 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:34,866 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:34,866 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-03-04 16:21:34,866 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:34,868 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:34,868 INFO L85 PathProgramCache]: Analyzing trace with hash -1442120476, now seen corresponding path program 1 times [2025-03-04 16:21:34,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:34,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745351598] [2025-03-04 16:21:34,868 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:34,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:34,874 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:34,878 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:34,881 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:34,881 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,911 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,911 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745351598] [2025-03-04 16:21:34,911 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [745351598] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,911 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,911 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:21:34,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1390150781] [2025-03-04 16:21:34,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,911 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:21:34,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:34,911 INFO L85 PathProgramCache]: Analyzing trace with hash 1854751102, now seen corresponding path program 1 times [2025-03-04 16:21:34,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:34,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1176433555] [2025-03-04 16:21:34,912 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:34,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:34,916 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:21:34,917 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:21:34,917 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:34,917 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:34,938 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:34,938 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:34,938 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1176433555] [2025-03-04 16:21:34,938 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1176433555] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:34,938 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:34,938 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:34,938 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [979943869] [2025-03-04 16:21:34,938 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:34,938 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:34,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:34,938 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:21:34,938 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:21:34,939 INFO L87 Difference]: Start difference. First operand 213 states and 358 transitions. cyclomatic complexity: 147 Second operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:35,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:35,053 INFO L93 Difference]: Finished difference Result 544 states and 900 transitions. [2025-03-04 16:21:35,053 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 544 states and 900 transitions. [2025-03-04 16:21:35,057 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 493 [2025-03-04 16:21:35,059 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 544 states to 544 states and 900 transitions. [2025-03-04 16:21:35,059 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 544 [2025-03-04 16:21:35,059 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 544 [2025-03-04 16:21:35,059 INFO L73 IsDeterministic]: Start isDeterministic. Operand 544 states and 900 transitions. [2025-03-04 16:21:35,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:35,060 INFO L218 hiAutomatonCegarLoop]: Abstraction has 544 states and 900 transitions. [2025-03-04 16:21:35,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 544 states and 900 transitions. [2025-03-04 16:21:35,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 544 to 518. [2025-03-04 16:21:35,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 518 states, 518 states have (on average 1.664092664092664) internal successors, (862), 517 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:35,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 862 transitions. [2025-03-04 16:21:35,074 INFO L240 hiAutomatonCegarLoop]: Abstraction has 518 states and 862 transitions. [2025-03-04 16:21:35,074 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:21:35,076 INFO L432 stractBuchiCegarLoop]: Abstraction has 518 states and 862 transitions. [2025-03-04 16:21:35,076 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-04 16:21:35,076 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 862 transitions. [2025-03-04 16:21:35,078 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 486 [2025-03-04 16:21:35,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:35,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:35,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:35,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:35,080 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-03-04 16:21:35,080 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:35,081 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:35,081 INFO L85 PathProgramCache]: Analyzing trace with hash -123185569, now seen corresponding path program 1 times [2025-03-04 16:21:35,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:35,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733472588] [2025-03-04 16:21:35,081 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:35,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:35,085 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:35,089 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:35,089 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:35,089 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:35,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:35,127 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:35,127 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [733472588] [2025-03-04 16:21:35,127 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [733472588] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:35,127 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:35,127 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:21:35,127 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1712258551] [2025-03-04 16:21:35,127 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:35,127 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:21:35,127 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:35,128 INFO L85 PathProgramCache]: Analyzing trace with hash -207939741, now seen corresponding path program 1 times [2025-03-04 16:21:35,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:35,128 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817606132] [2025-03-04 16:21:35,128 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:35,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:35,135 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:21:35,138 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:21:35,138 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:35,138 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:35,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:35,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:35,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817606132] [2025-03-04 16:21:35,155 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [817606132] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:35,156 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:35,156 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:35,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [12262783] [2025-03-04 16:21:35,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:35,156 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:35,156 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:35,157 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:21:35,157 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:21:35,157 INFO L87 Difference]: Start difference. First operand 518 states and 862 transitions. cyclomatic complexity: 348 Second operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:35,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:35,220 INFO L93 Difference]: Finished difference Result 1009 states and 1646 transitions. [2025-03-04 16:21:35,224 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1009 states and 1646 transitions. [2025-03-04 16:21:35,229 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 959 [2025-03-04 16:21:35,233 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1009 states to 1009 states and 1646 transitions. [2025-03-04 16:21:35,233 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1009 [2025-03-04 16:21:35,234 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1009 [2025-03-04 16:21:35,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1009 states and 1646 transitions. [2025-03-04 16:21:35,235 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:35,235 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1009 states and 1646 transitions. [2025-03-04 16:21:35,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1009 states and 1646 transitions. [2025-03-04 16:21:35,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1009 to 1007. [2025-03-04 16:21:35,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.6325719960278053) internal successors, (1644), 1006 states have internal predecessors, (1644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:35,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1644 transitions. [2025-03-04 16:21:35,266 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1644 transitions. [2025-03-04 16:21:35,266 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:21:35,267 INFO L432 stractBuchiCegarLoop]: Abstraction has 1007 states and 1644 transitions. [2025-03-04 16:21:35,268 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-04 16:21:35,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1644 transitions. [2025-03-04 16:21:35,272 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 957 [2025-03-04 16:21:35,272 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:35,272 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:35,273 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:35,274 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:35,274 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-03-04 16:21:35,275 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume !(1 == ~e_e~0);" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:35,275 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:35,275 INFO L85 PathProgramCache]: Analyzing trace with hash 171111168, now seen corresponding path program 1 times [2025-03-04 16:21:35,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:35,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1634134977] [2025-03-04 16:21:35,275 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:35,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:35,280 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:35,281 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:35,282 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:35,282 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:35,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:35,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:35,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1634134977] [2025-03-04 16:21:35,311 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1634134977] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:35,311 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:35,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:21:35,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [579441632] [2025-03-04 16:21:35,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:35,312 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:21:35,312 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:35,313 INFO L85 PathProgramCache]: Analyzing trace with hash -179310590, now seen corresponding path program 1 times [2025-03-04 16:21:35,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:35,313 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911620608] [2025-03-04 16:21:35,313 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:35,313 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:35,317 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:21:35,319 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:21:35,320 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:35,320 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:35,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:35,331 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:35,331 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911620608] [2025-03-04 16:21:35,331 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [911620608] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:35,331 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:35,331 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:35,332 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1042037699] [2025-03-04 16:21:35,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:35,332 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:35,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:35,333 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:21:35,333 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:21:35,333 INFO L87 Difference]: Start difference. First operand 1007 states and 1644 transitions. cyclomatic complexity: 645 Second operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:35,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:35,402 INFO L93 Difference]: Finished difference Result 1195 states and 1921 transitions. [2025-03-04 16:21:35,402 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1195 states and 1921 transitions. [2025-03-04 16:21:35,408 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 1154 [2025-03-04 16:21:35,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1195 states to 1195 states and 1921 transitions. [2025-03-04 16:21:35,416 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1195 [2025-03-04 16:21:35,417 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1195 [2025-03-04 16:21:35,417 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1195 states and 1921 transitions. [2025-03-04 16:21:35,418 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:35,419 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1195 states and 1921 transitions. [2025-03-04 16:21:35,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1195 states and 1921 transitions. [2025-03-04 16:21:35,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1195 to 1185. [2025-03-04 16:21:35,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.6126582278481012) internal successors, (1911), 1184 states have internal predecessors, (1911), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:35,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1911 transitions. [2025-03-04 16:21:35,438 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1911 transitions. [2025-03-04 16:21:35,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:21:35,439 INFO L432 stractBuchiCegarLoop]: Abstraction has 1185 states and 1911 transitions. [2025-03-04 16:21:35,440 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-04 16:21:35,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1911 transitions. [2025-03-04 16:21:35,444 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 1154 [2025-03-04 16:21:35,445 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:35,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:35,445 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:35,445 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:35,446 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-03-04 16:21:35,446 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:35,446 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:35,446 INFO L85 PathProgramCache]: Analyzing trace with hash -122291839, now seen corresponding path program 1 times [2025-03-04 16:21:35,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:35,446 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142526083] [2025-03-04 16:21:35,446 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:35,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:35,450 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:35,452 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:35,453 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:35,453 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:35,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:35,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:35,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142526083] [2025-03-04 16:21:35,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142526083] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:35,474 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:35,474 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:21:35,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572021751] [2025-03-04 16:21:35,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:35,474 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:21:35,475 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:35,475 INFO L85 PathProgramCache]: Analyzing trace with hash 202635427, now seen corresponding path program 1 times [2025-03-04 16:21:35,475 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:35,475 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1062022740] [2025-03-04 16:21:35,475 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:35,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:35,478 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:21:35,479 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:21:35,479 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:35,479 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:35,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:35,488 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:35,488 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1062022740] [2025-03-04 16:21:35,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1062022740] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:35,488 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:35,488 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:35,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [764418789] [2025-03-04 16:21:35,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:35,488 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:35,489 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:35,489 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:21:35,489 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:21:35,489 INFO L87 Difference]: Start difference. First operand 1185 states and 1911 transitions. cyclomatic complexity: 735 Second operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:35,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:35,568 INFO L93 Difference]: Finished difference Result 1119 states and 1758 transitions. [2025-03-04 16:21:35,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1119 states and 1758 transitions. [2025-03-04 16:21:35,574 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 1081 [2025-03-04 16:21:35,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1119 states to 1119 states and 1758 transitions. [2025-03-04 16:21:35,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1119 [2025-03-04 16:21:35,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1119 [2025-03-04 16:21:35,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1119 states and 1758 transitions. [2025-03-04 16:21:35,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:35,582 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1119 states and 1758 transitions. [2025-03-04 16:21:35,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1119 states and 1758 transitions. [2025-03-04 16:21:35,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1119 to 1107. [2025-03-04 16:21:35,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1107 states, 1107 states have (on average 1.5772357723577235) internal successors, (1746), 1106 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:35,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1107 states to 1107 states and 1746 transitions. [2025-03-04 16:21:35,611 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1107 states and 1746 transitions. [2025-03-04 16:21:35,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:21:35,612 INFO L432 stractBuchiCegarLoop]: Abstraction has 1107 states and 1746 transitions. [2025-03-04 16:21:35,612 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-04 16:21:35,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1107 states and 1746 transitions. [2025-03-04 16:21:35,616 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 1079 [2025-03-04 16:21:35,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:35,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:35,617 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:35,617 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:35,617 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-03-04 16:21:35,617 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~e_f~0);" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:35,618 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:35,618 INFO L85 PathProgramCache]: Analyzing trace with hash -122262048, now seen corresponding path program 1 times [2025-03-04 16:21:35,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:35,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689253620] [2025-03-04 16:21:35,618 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:35,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:35,625 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:35,627 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:35,627 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:35,627 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:35,627 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:21:35,630 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:35,632 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:35,632 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:35,632 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:35,650 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:21:35,650 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:35,651 INFO L85 PathProgramCache]: Analyzing trace with hash 1556868645, now seen corresponding path program 1 times [2025-03-04 16:21:35,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:35,651 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1839612250] [2025-03-04 16:21:35,651 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:35,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:35,654 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:21:35,655 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:21:35,656 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:35,656 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:35,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:35,669 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:35,669 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1839612250] [2025-03-04 16:21:35,669 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1839612250] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:35,669 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:35,669 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:35,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164213666] [2025-03-04 16:21:35,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:35,669 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:35,670 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:35,670 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:21:35,670 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:21:35,671 INFO L87 Difference]: Start difference. First operand 1107 states and 1746 transitions. cyclomatic complexity: 646 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:35,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:35,703 INFO L93 Difference]: Finished difference Result 1626 states and 2540 transitions. [2025-03-04 16:21:35,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1626 states and 2540 transitions. [2025-03-04 16:21:35,713 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 1583 [2025-03-04 16:21:35,721 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1626 states to 1626 states and 2540 transitions. [2025-03-04 16:21:35,722 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1626 [2025-03-04 16:21:35,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1626 [2025-03-04 16:21:35,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1626 states and 2540 transitions. [2025-03-04 16:21:35,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:35,725 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1626 states and 2540 transitions. [2025-03-04 16:21:35,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1626 states and 2540 transitions. [2025-03-04 16:21:35,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1626 to 1622. [2025-03-04 16:21:35,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1622 states, 1622 states have (on average 1.563501849568434) internal successors, (2536), 1621 states have internal predecessors, (2536), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:35,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1622 states to 1622 states and 2536 transitions. [2025-03-04 16:21:35,748 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1622 states and 2536 transitions. [2025-03-04 16:21:35,748 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:21:35,749 INFO L432 stractBuchiCegarLoop]: Abstraction has 1622 states and 2536 transitions. [2025-03-04 16:21:35,749 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-04 16:21:35,749 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1622 states and 2536 transitions. [2025-03-04 16:21:35,755 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 1579 [2025-03-04 16:21:35,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:35,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:35,756 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:35,756 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:35,756 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume 1 == ~e_wl~0;~e_wl~0 := 2;" [2025-03-04 16:21:35,756 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~e_f~0);" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume !(1 == ~e_c~0);" "assume 1 == ~e_wl~0;~e_wl~0 := 2;" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:35,757 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:35,757 INFO L85 PathProgramCache]: Analyzing trace with hash -251344768, now seen corresponding path program 1 times [2025-03-04 16:21:35,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:35,758 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1928421416] [2025-03-04 16:21:35,758 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:35,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:35,765 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:35,768 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:35,768 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:35,769 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:35,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:35,803 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:35,803 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1928421416] [2025-03-04 16:21:35,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1928421416] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:35,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:35,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:21:35,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2035962910] [2025-03-04 16:21:35,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:35,804 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:21:35,804 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:35,804 INFO L85 PathProgramCache]: Analyzing trace with hash 1556868614, now seen corresponding path program 1 times [2025-03-04 16:21:35,804 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:35,804 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925952181] [2025-03-04 16:21:35,804 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:35,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:35,809 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:21:35,811 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:21:35,811 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:35,811 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:35,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:35,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:35,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [925952181] [2025-03-04 16:21:35,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [925952181] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:35,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:35,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:21:35,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1675024208] [2025-03-04 16:21:35,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:35,824 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:35,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:35,825 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:21:35,825 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:21:35,825 INFO L87 Difference]: Start difference. First operand 1622 states and 2536 transitions. cyclomatic complexity: 921 Second operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:35,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:35,899 INFO L93 Difference]: Finished difference Result 2609 states and 4065 transitions. [2025-03-04 16:21:35,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2609 states and 4065 transitions. [2025-03-04 16:21:35,910 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 2557 [2025-03-04 16:21:35,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2609 states to 2609 states and 4065 transitions. [2025-03-04 16:21:35,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2609 [2025-03-04 16:21:35,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2609 [2025-03-04 16:21:35,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2609 states and 4065 transitions. [2025-03-04 16:21:35,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:35,926 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2609 states and 4065 transitions. [2025-03-04 16:21:35,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2609 states and 4065 transitions. [2025-03-04 16:21:35,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2609 to 2577. [2025-03-04 16:21:35,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2577 states, 2577 states have (on average 1.561893674815677) internal successors, (4025), 2576 states have internal predecessors, (4025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:35,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2577 states to 2577 states and 4025 transitions. [2025-03-04 16:21:35,970 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2577 states and 4025 transitions. [2025-03-04 16:21:35,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:21:35,974 INFO L432 stractBuchiCegarLoop]: Abstraction has 2577 states and 4025 transitions. [2025-03-04 16:21:35,975 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-04 16:21:35,975 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2577 states and 4025 transitions. [2025-03-04 16:21:36,001 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 2549 [2025-03-04 16:21:36,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:36,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:36,004 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:36,004 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:36,004 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume 1 == ~e_wl~0;~e_wl~0 := 2;" [2025-03-04 16:21:36,004 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~e_f~0);" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:36,004 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:36,004 INFO L85 PathProgramCache]: Analyzing trace with hash -122262049, now seen corresponding path program 1 times [2025-03-04 16:21:36,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:36,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542445110] [2025-03-04 16:21:36,005 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:36,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:36,011 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:36,015 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:36,015 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,015 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:36,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:36,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:36,059 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542445110] [2025-03-04 16:21:36,059 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [542445110] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:36,059 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:36,059 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:36,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [6726930] [2025-03-04 16:21:36,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:36,060 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:21:36,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:36,060 INFO L85 PathProgramCache]: Analyzing trace with hash 1263465638, now seen corresponding path program 1 times [2025-03-04 16:21:36,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:36,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145353459] [2025-03-04 16:21:36,060 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:36,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:36,065 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:21:36,066 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:21:36,066 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,066 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:36,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:36,081 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:36,081 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1145353459] [2025-03-04 16:21:36,081 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1145353459] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:36,081 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:36,081 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:21:36,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [481128191] [2025-03-04 16:21:36,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:36,081 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:36,081 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:36,082 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:21:36,082 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:21:36,082 INFO L87 Difference]: Start difference. First operand 2577 states and 4025 transitions. cyclomatic complexity: 1461 Second operand has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:36,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:36,142 INFO L93 Difference]: Finished difference Result 2376 states and 3681 transitions. [2025-03-04 16:21:36,142 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2376 states and 3681 transitions. [2025-03-04 16:21:36,153 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 2336 [2025-03-04 16:21:36,161 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2376 states to 2376 states and 3681 transitions. [2025-03-04 16:21:36,161 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2376 [2025-03-04 16:21:36,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2376 [2025-03-04 16:21:36,163 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2376 states and 3681 transitions. [2025-03-04 16:21:36,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:36,166 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2376 states and 3681 transitions. [2025-03-04 16:21:36,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2376 states and 3681 transitions. [2025-03-04 16:21:36,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2376 to 2368. [2025-03-04 16:21:36,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2368 states, 2368 states have (on average 1.551097972972973) internal successors, (3673), 2367 states have internal predecessors, (3673), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:36,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2368 states to 2368 states and 3673 transitions. [2025-03-04 16:21:36,201 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2368 states and 3673 transitions. [2025-03-04 16:21:36,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:21:36,202 INFO L432 stractBuchiCegarLoop]: Abstraction has 2368 states and 3673 transitions. [2025-03-04 16:21:36,202 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-04 16:21:36,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2368 states and 3673 transitions. [2025-03-04 16:21:36,208 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 2336 [2025-03-04 16:21:36,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:36,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:36,209 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:36,209 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:36,209 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-03-04 16:21:36,209 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~e_f~0);" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-03-04 16:21:36,209 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:36,209 INFO L85 PathProgramCache]: Analyzing trace with hash -122262048, now seen corresponding path program 2 times [2025-03-04 16:21:36,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:36,210 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166833925] [2025-03-04 16:21:36,210 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:21:36,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:36,213 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:36,215 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:36,215 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:21:36,215 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,215 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:21:36,216 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-03-04 16:21:36,218 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 16:21:36,218 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,218 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,221 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:21:36,222 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:36,222 INFO L85 PathProgramCache]: Analyzing trace with hash 1263465638, now seen corresponding path program 2 times [2025-03-04 16:21:36,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:36,222 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120978652] [2025-03-04 16:21:36,222 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:21:36,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:36,224 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:21:36,225 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:21:36,225 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:21:36,225 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:36,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:36,235 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:36,235 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2120978652] [2025-03-04 16:21:36,235 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2120978652] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:36,235 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:36,235 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:21:36,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1267841998] [2025-03-04 16:21:36,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:36,235 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:21:36,235 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:36,235 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:21:36,235 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:21:36,235 INFO L87 Difference]: Start difference. First operand 2368 states and 3673 transitions. cyclomatic complexity: 1318 Second operand has 3 states, 2 states have (on average 14.0) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:36,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:36,262 INFO L93 Difference]: Finished difference Result 2650 states and 4034 transitions. [2025-03-04 16:21:36,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2650 states and 4034 transitions. [2025-03-04 16:21:36,271 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 2562 [2025-03-04 16:21:36,279 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2650 states to 2650 states and 4034 transitions. [2025-03-04 16:21:36,280 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2650 [2025-03-04 16:21:36,282 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2650 [2025-03-04 16:21:36,282 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2650 states and 4034 transitions. [2025-03-04 16:21:36,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:36,285 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2650 states and 4034 transitions. [2025-03-04 16:21:36,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2650 states and 4034 transitions. [2025-03-04 16:21:36,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2650 to 2323. [2025-03-04 16:21:36,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2323 states, 2323 states have (on average 1.5264743865690917) internal successors, (3546), 2322 states have internal predecessors, (3546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:36,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2323 states to 2323 states and 3546 transitions. [2025-03-04 16:21:36,321 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2323 states and 3546 transitions. [2025-03-04 16:21:36,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:21:36,322 INFO L432 stractBuchiCegarLoop]: Abstraction has 2323 states and 3546 transitions. [2025-03-04 16:21:36,322 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-04 16:21:36,322 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2323 states and 3546 transitions. [2025-03-04 16:21:36,328 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 2247 [2025-03-04 16:21:36,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:36,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:36,328 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:36,328 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:36,328 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-03-04 16:21:36,328 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume 0 == ~wl_st~0;" "assume 0 == ~wl_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1;" "assume !(0 != eval_~tmp~0#1);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" [2025-03-04 16:21:36,329 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:36,329 INFO L85 PathProgramCache]: Analyzing trace with hash -1529704737, now seen corresponding path program 1 times [2025-03-04 16:21:36,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:36,329 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [418337586] [2025-03-04 16:21:36,329 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:36,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:36,332 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-03-04 16:21:36,334 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 16:21:36,334 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,334 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,334 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:21:36,336 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-03-04 16:21:36,337 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 16:21:36,337 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,337 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,341 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:21:36,341 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:36,341 INFO L85 PathProgramCache]: Analyzing trace with hash 339625268, now seen corresponding path program 1 times [2025-03-04 16:21:36,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:36,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187380907] [2025-03-04 16:21:36,341 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:36,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:36,343 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:21:36,344 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:21:36,344 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,344 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,344 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:21:36,344 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 16:21:36,344 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 16:21:36,344 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,344 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,345 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:21:36,346 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:36,346 INFO L85 PathProgramCache]: Analyzing trace with hash 1341855250, now seen corresponding path program 1 times [2025-03-04 16:21:36,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:36,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658374046] [2025-03-04 16:21:36,346 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:36,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:36,351 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-03-04 16:21:36,366 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-03-04 16:21:36,366 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,366 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:36,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:36,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:36,385 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658374046] [2025-03-04 16:21:36,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1658374046] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:36,385 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:36,385 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:36,385 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1073072882] [2025-03-04 16:21:36,385 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:36,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:36,430 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:21:36,430 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:21:36,430 INFO L87 Difference]: Start difference. First operand 2323 states and 3546 transitions. cyclomatic complexity: 1238 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:36,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:36,472 INFO L93 Difference]: Finished difference Result 3568 states and 5413 transitions. [2025-03-04 16:21:36,472 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3568 states and 5413 transitions. [2025-03-04 16:21:36,488 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 3474 [2025-03-04 16:21:36,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3568 states to 3568 states and 5413 transitions. [2025-03-04 16:21:36,503 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3568 [2025-03-04 16:21:36,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3568 [2025-03-04 16:21:36,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3568 states and 5413 transitions. [2025-03-04 16:21:36,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:36,511 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3568 states and 5413 transitions. [2025-03-04 16:21:36,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3568 states and 5413 transitions. [2025-03-04 16:21:36,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3568 to 3568. [2025-03-04 16:21:36,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3568 states, 3568 states have (on average 1.5170964125560538) internal successors, (5413), 3567 states have internal predecessors, (5413), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:36,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3568 states to 3568 states and 5413 transitions. [2025-03-04 16:21:36,572 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3568 states and 5413 transitions. [2025-03-04 16:21:36,572 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:21:36,573 INFO L432 stractBuchiCegarLoop]: Abstraction has 3568 states and 5413 transitions. [2025-03-04 16:21:36,573 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-04 16:21:36,573 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3568 states and 5413 transitions. [2025-03-04 16:21:36,583 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 3474 [2025-03-04 16:21:36,583 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:36,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:36,583 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:36,583 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:36,584 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-03-04 16:21:36,584 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume 0 == ~wl_st~0;" "assume 0 == ~wl_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~c1_st~0;havoc eval_#t~nondet5#1;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" [2025-03-04 16:21:36,584 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:36,584 INFO L85 PathProgramCache]: Analyzing trace with hash -1529704737, now seen corresponding path program 2 times [2025-03-04 16:21:36,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:36,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [695464957] [2025-03-04 16:21:36,584 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:21:36,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:36,591 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 26 statements into 1 equivalence classes. [2025-03-04 16:21:36,593 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 16:21:36,594 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:21:36,594 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,594 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:21:36,597 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-03-04 16:21:36,599 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 16:21:36,599 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,599 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,603 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:21:36,604 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:36,604 INFO L85 PathProgramCache]: Analyzing trace with hash 1938204300, now seen corresponding path program 1 times [2025-03-04 16:21:36,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:36,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734357454] [2025-03-04 16:21:36,604 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:36,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:36,606 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-04 16:21:36,607 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-04 16:21:36,607 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,607 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,607 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:21:36,607 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-04 16:21:36,608 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-04 16:21:36,608 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,608 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,609 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:21:36,610 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:36,610 INFO L85 PathProgramCache]: Analyzing trace with hash -1352404626, now seen corresponding path program 1 times [2025-03-04 16:21:36,610 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:36,610 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1631968814] [2025-03-04 16:21:36,610 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:36,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:36,615 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 35 statements into 1 equivalence classes. [2025-03-04 16:21:36,618 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 35 of 35 statements. [2025-03-04 16:21:36,618 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,618 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:36,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:36,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:36,635 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1631968814] [2025-03-04 16:21:36,635 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1631968814] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:36,635 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:36,635 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:36,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1944620986] [2025-03-04 16:21:36,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:36,677 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:36,678 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:21:36,678 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:21:36,678 INFO L87 Difference]: Start difference. First operand 3568 states and 5413 transitions. cyclomatic complexity: 1860 Second operand has 3 states, 3 states have (on average 11.666666666666666) internal successors, (35), 3 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:36,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:36,712 INFO L93 Difference]: Finished difference Result 5616 states and 8441 transitions. [2025-03-04 16:21:36,712 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5616 states and 8441 transitions. [2025-03-04 16:21:36,729 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 5486 [2025-03-04 16:21:36,753 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5616 states to 5616 states and 8441 transitions. [2025-03-04 16:21:36,753 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5616 [2025-03-04 16:21:36,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5616 [2025-03-04 16:21:36,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5616 states and 8441 transitions. [2025-03-04 16:21:36,765 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:36,765 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5616 states and 8441 transitions. [2025-03-04 16:21:36,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5616 states and 8441 transitions. [2025-03-04 16:21:36,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5616 to 5616. [2025-03-04 16:21:36,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5616 states, 5616 states have (on average 1.5030270655270654) internal successors, (8441), 5615 states have internal predecessors, (8441), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:36,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5616 states to 5616 states and 8441 transitions. [2025-03-04 16:21:36,880 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5616 states and 8441 transitions. [2025-03-04 16:21:36,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:21:36,881 INFO L432 stractBuchiCegarLoop]: Abstraction has 5616 states and 8441 transitions. [2025-03-04 16:21:36,881 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-04 16:21:36,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5616 states and 8441 transitions. [2025-03-04 16:21:36,894 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 5486 [2025-03-04 16:21:36,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:36,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:36,894 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:36,894 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:36,894 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-03-04 16:21:36,894 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume 0 == ~wl_st~0;" "assume 0 == ~wl_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~c1_st~0;havoc eval_#t~nondet5#1;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume 0 == ~c2_st~0;havoc eval_#t~nondet6#1;eval_~tmp___1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp___1~0#1);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" [2025-03-04 16:21:36,895 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:36,895 INFO L85 PathProgramCache]: Analyzing trace with hash -1529704737, now seen corresponding path program 3 times [2025-03-04 16:21:36,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:36,895 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1941283362] [2025-03-04 16:21:36,895 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:21:36,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:36,898 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 26 statements into 1 equivalence classes. [2025-03-04 16:21:36,900 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 16:21:36,900 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:21:36,900 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,900 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:21:36,901 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-03-04 16:21:36,903 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 16:21:36,903 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,903 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,907 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:21:36,907 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:36,907 INFO L85 PathProgramCache]: Analyzing trace with hash -45216854, now seen corresponding path program 1 times [2025-03-04 16:21:36,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:36,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1684944187] [2025-03-04 16:21:36,907 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:36,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:36,909 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-04 16:21:36,909 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-04 16:21:36,909 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,909 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,909 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:21:36,913 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-04 16:21:36,913 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-04 16:21:36,913 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,913 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:36,914 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:21:36,914 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:36,915 INFO L85 PathProgramCache]: Analyzing trace with hash 1025121544, now seen corresponding path program 1 times [2025-03-04 16:21:36,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:36,915 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230092730] [2025-03-04 16:21:36,915 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:36,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:36,918 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-03-04 16:21:36,920 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-03-04 16:21:36,920 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:36,920 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:21:36,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:21:36,932 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:21:36,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [230092730] [2025-03-04 16:21:36,932 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [230092730] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:21:36,932 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:21:36,932 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:21:36,932 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [535826581] [2025-03-04 16:21:36,932 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:21:36,959 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:21:36,960 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:21:36,960 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:21:36,960 INFO L87 Difference]: Start difference. First operand 5616 states and 8441 transitions. cyclomatic complexity: 2840 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:37,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:21:37,003 INFO L93 Difference]: Finished difference Result 9558 states and 14306 transitions. [2025-03-04 16:21:37,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9558 states and 14306 transitions. [2025-03-04 16:21:37,043 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 9344 [2025-03-04 16:21:37,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9558 states to 9558 states and 14306 transitions. [2025-03-04 16:21:37,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9558 [2025-03-04 16:21:37,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9558 [2025-03-04 16:21:37,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9558 states and 14306 transitions. [2025-03-04 16:21:37,106 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:21:37,106 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9558 states and 14306 transitions. [2025-03-04 16:21:37,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9558 states and 14306 transitions. [2025-03-04 16:21:37,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9558 to 9558. [2025-03-04 16:21:37,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9558 states, 9558 states have (on average 1.496756643649299) internal successors, (14306), 9557 states have internal predecessors, (14306), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:21:37,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9558 states to 9558 states and 14306 transitions. [2025-03-04 16:21:37,293 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9558 states and 14306 transitions. [2025-03-04 16:21:37,294 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:21:37,294 INFO L432 stractBuchiCegarLoop]: Abstraction has 9558 states and 14306 transitions. [2025-03-04 16:21:37,294 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-04 16:21:37,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9558 states and 14306 transitions. [2025-03-04 16:21:37,328 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 9344 [2025-03-04 16:21:37,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:21:37,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:21:37,329 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:37,329 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:21:37,329 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-03-04 16:21:37,329 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume 0 == ~wl_st~0;" "assume 0 == ~wl_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~c1_st~0;havoc eval_#t~nondet5#1;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume 0 == ~c2_st~0;havoc eval_#t~nondet6#1;eval_~tmp___1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp___1~0#1);" "assume 0 == ~wb_st~0;havoc eval_#t~nondet7#1;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___2~0#1);" "assume !(0 == ~r_st~0);" [2025-03-04 16:21:37,330 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:37,330 INFO L85 PathProgramCache]: Analyzing trace with hash -1529704737, now seen corresponding path program 4 times [2025-03-04 16:21:37,330 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:37,330 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089991735] [2025-03-04 16:21:37,330 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:21:37,330 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:37,334 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 26 statements into 2 equivalence classes. [2025-03-04 16:21:37,337 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 16:21:37,337 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 16:21:37,338 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:37,338 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:21:37,339 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-03-04 16:21:37,341 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 16:21:37,342 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:37,342 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:37,345 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:21:37,345 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:37,345 INFO L85 PathProgramCache]: Analyzing trace with hash -1401722858, now seen corresponding path program 1 times [2025-03-04 16:21:37,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:37,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227912689] [2025-03-04 16:21:37,345 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:37,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:37,348 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-03-04 16:21:37,348 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-03-04 16:21:37,348 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:37,348 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:37,348 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:21:37,349 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-03-04 16:21:37,349 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-03-04 16:21:37,349 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:37,349 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:37,350 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:21:37,351 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:21:37,351 INFO L85 PathProgramCache]: Analyzing trace with hash 1713996408, now seen corresponding path program 1 times [2025-03-04 16:21:37,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:21:37,351 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070714640] [2025-03-04 16:21:37,351 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:21:37,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:21:37,355 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-03-04 16:21:37,357 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-03-04 16:21:37,358 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:37,358 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:37,358 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:21:37,359 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-03-04 16:21:37,361 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-03-04 16:21:37,361 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:37,361 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:37,364 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:21:38,317 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-03-04 16:21:38,321 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 16:21:38,321 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:38,321 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:38,321 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:21:38,329 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-03-04 16:21:38,333 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 16:21:38,333 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:21:38,333 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:21:38,415 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 04.03 04:21:38 BoogieIcfgContainer [2025-03-04 16:21:38,415 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-04 16:21:38,416 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-04 16:21:38,416 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-04 16:21:38,416 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-04 16:21:38,418 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:21:33" (3/4) ... [2025-03-04 16:21:38,420 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-03-04 16:21:38,479 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-04 16:21:38,479 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-04 16:21:38,480 INFO L158 Benchmark]: Toolchain (without parser) took 5561.66ms. Allocated memory was 167.8MB in the beginning and 436.2MB in the end (delta: 268.4MB). Free memory was 121.9MB in the beginning and 219.5MB in the end (delta: -97.6MB). Peak memory consumption was 169.3MB. Max. memory is 16.1GB. [2025-03-04 16:21:38,481 INFO L158 Benchmark]: CDTParser took 0.25ms. Allocated memory is still 201.3MB. Free memory is still 118.1MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:21:38,482 INFO L158 Benchmark]: CACSL2BoogieTranslator took 258.43ms. Allocated memory is still 167.8MB. Free memory was 121.5MB in the beginning and 107.0MB in the end (delta: 14.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-04 16:21:38,482 INFO L158 Benchmark]: Boogie Procedure Inliner took 36.69ms. Allocated memory is still 167.8MB. Free memory was 107.0MB in the beginning and 105.2MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:21:38,482 INFO L158 Benchmark]: Boogie Preprocessor took 47.21ms. Allocated memory is still 167.8MB. Free memory was 105.2MB in the beginning and 103.4MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:21:38,482 INFO L158 Benchmark]: IcfgBuilder took 517.53ms. Allocated memory is still 167.8MB. Free memory was 103.4MB in the beginning and 78.7MB in the end (delta: 24.7MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2025-03-04 16:21:38,482 INFO L158 Benchmark]: BuchiAutomizer took 4633.47ms. Allocated memory was 167.8MB in the beginning and 436.2MB in the end (delta: 268.4MB). Free memory was 78.7MB in the beginning and 226.6MB in the end (delta: -147.9MB). Peak memory consumption was 119.0MB. Max. memory is 16.1GB. [2025-03-04 16:21:38,482 INFO L158 Benchmark]: Witness Printer took 63.45ms. Allocated memory is still 436.2MB. Free memory was 226.6MB in the beginning and 219.5MB in the end (delta: 7.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 16:21:38,485 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25ms. Allocated memory is still 201.3MB. Free memory is still 118.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 258.43ms. Allocated memory is still 167.8MB. Free memory was 121.5MB in the beginning and 107.0MB in the end (delta: 14.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 36.69ms. Allocated memory is still 167.8MB. Free memory was 107.0MB in the beginning and 105.2MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 47.21ms. Allocated memory is still 167.8MB. Free memory was 105.2MB in the beginning and 103.4MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 517.53ms. Allocated memory is still 167.8MB. Free memory was 103.4MB in the beginning and 78.7MB in the end (delta: 24.7MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 4633.47ms. Allocated memory was 167.8MB in the beginning and 436.2MB in the end (delta: 268.4MB). Free memory was 78.7MB in the beginning and 226.6MB in the end (delta: -147.9MB). Peak memory consumption was 119.0MB. Max. memory is 16.1GB. * Witness Printer took 63.45ms. Allocated memory is still 436.2MB. Free memory was 226.6MB in the beginning and 219.5MB in the end (delta: 7.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (17 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.17 modules have a trivial ranking function, the largest among these consists of 4 locations. The remainder module has 9558 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.5s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 2.4s. Construction of modules took 0.4s. Büchi inclusion checks took 1.4s. Highest rank in rank-based complementation 0. Minimization of det autom 17. Minimization of nondet autom 0. Automata minimization 0.6s AutomataMinimizationTime, 17 MinimizatonAttempts, 426 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 4392 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 4392 mSDsluCounter, 6386 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2228 mSDsCounter, 135 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 415 IncrementalHoareTripleChecker+Invalid, 550 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 135 mSolverCounterUnsat, 4158 mSDtfsCounter, 415 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc3 concLT0 SILN0 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 294]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L28] int c ; [L29] int c_t ; [L30] int c_req_up ; [L31] int p_in ; [L32] int p_out ; [L33] int wl_st ; [L34] int c1_st ; [L35] int c2_st ; [L36] int wb_st ; [L37] int r_st ; [L38] int wl_i ; [L39] int c1_i ; [L40] int c2_i ; [L41] int wb_i ; [L42] int r_i ; [L43] int wl_pc ; [L44] int c1_pc ; [L45] int c2_pc ; [L46] int wb_pc ; [L47] int e_e ; [L48] int e_f ; [L49] int e_g ; [L50] int e_c ; [L51] int e_p_in ; [L52] int e_wl ; [L58] int d ; [L59] int data ; [L60] int processed ; [L61] static int t_b ; VAL [c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L689] int __retres1 ; [L693] e_wl = 2 [L694] e_c = e_wl [L695] e_g = e_c [L696] e_f = e_g [L697] e_e = e_f [L698] wl_pc = 0 [L699] c1_pc = 0 [L700] c2_pc = 0 [L701] wb_pc = 0 [L702] wb_i = 1 [L703] c2_i = wb_i [L704] c1_i = c2_i [L705] wl_i = c1_i [L706] r_i = 0 [L707] c_req_up = 0 [L708] d = 0 [L709] c = 0 [L710] CALL start_simulation() [L400] int kernel_st ; [L403] kernel_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L404] COND FALSE !((int )c_req_up == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L415] COND TRUE (int )wl_i == 1 [L416] wl_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L420] COND TRUE (int )c1_i == 1 [L421] c1_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L425] COND TRUE (int )c2_i == 1 [L426] c2_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L430] COND TRUE (int )wb_i == 1 [L431] wb_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L435] COND FALSE !((int )r_i == 1) [L438] r_st = 2 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L440] COND FALSE !((int )e_f == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L445] COND FALSE !((int )e_g == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L450] COND FALSE !((int )e_e == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L455] COND FALSE !((int )e_c == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L460] COND FALSE !((int )e_wl == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L465] COND FALSE !((int )wl_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L473] COND FALSE !((int )wl_pc == 2) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L483] COND FALSE !((int )c1_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L492] COND FALSE !((int )c2_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L501] COND FALSE !((int )wb_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L510] COND FALSE !((int )e_c == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L515] COND FALSE !((int )e_e == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L520] COND FALSE !((int )e_f == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L525] COND FALSE !((int )e_g == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L530] COND FALSE !((int )e_c == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L535] COND FALSE !((int )e_wl == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L541] COND TRUE 1 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L544] kernel_st = 1 [L545] CALL eval() [L286] int tmp ; [L287] int tmp___0 ; [L288] int tmp___1 ; [L289] int tmp___2 ; [L290] int tmp___3 ; VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] Loop: [L294] COND TRUE 1 [L296] COND TRUE (int )wl_st == 0 [L317] COND TRUE (int )wl_st == 0 [L319] tmp = __VERIFIER_nondet_int() [L321] COND FALSE !(\read(tmp)) [L332] COND TRUE (int )c1_st == 0 [L334] tmp___0 = __VERIFIER_nondet_int() [L336] COND FALSE !(\read(tmp___0)) [L347] COND TRUE (int )c2_st == 0 [L349] tmp___1 = __VERIFIER_nondet_int() [L351] COND FALSE !(\read(tmp___1)) [L362] COND TRUE (int )wb_st == 0 [L364] tmp___2 = __VERIFIER_nondet_int() [L366] COND FALSE !(\read(tmp___2)) [L377] COND FALSE !((int )r_st == 0) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 294]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L28] int c ; [L29] int c_t ; [L30] int c_req_up ; [L31] int p_in ; [L32] int p_out ; [L33] int wl_st ; [L34] int c1_st ; [L35] int c2_st ; [L36] int wb_st ; [L37] int r_st ; [L38] int wl_i ; [L39] int c1_i ; [L40] int c2_i ; [L41] int wb_i ; [L42] int r_i ; [L43] int wl_pc ; [L44] int c1_pc ; [L45] int c2_pc ; [L46] int wb_pc ; [L47] int e_e ; [L48] int e_f ; [L49] int e_g ; [L50] int e_c ; [L51] int e_p_in ; [L52] int e_wl ; [L58] int d ; [L59] int data ; [L60] int processed ; [L61] static int t_b ; VAL [c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L689] int __retres1 ; [L693] e_wl = 2 [L694] e_c = e_wl [L695] e_g = e_c [L696] e_f = e_g [L697] e_e = e_f [L698] wl_pc = 0 [L699] c1_pc = 0 [L700] c2_pc = 0 [L701] wb_pc = 0 [L702] wb_i = 1 [L703] c2_i = wb_i [L704] c1_i = c2_i [L705] wl_i = c1_i [L706] r_i = 0 [L707] c_req_up = 0 [L708] d = 0 [L709] c = 0 [L710] CALL start_simulation() [L400] int kernel_st ; [L403] kernel_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L404] COND FALSE !((int )c_req_up == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L415] COND TRUE (int )wl_i == 1 [L416] wl_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L420] COND TRUE (int )c1_i == 1 [L421] c1_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L425] COND TRUE (int )c2_i == 1 [L426] c2_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L430] COND TRUE (int )wb_i == 1 [L431] wb_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L435] COND FALSE !((int )r_i == 1) [L438] r_st = 2 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L440] COND FALSE !((int )e_f == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L445] COND FALSE !((int )e_g == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L450] COND FALSE !((int )e_e == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L455] COND FALSE !((int )e_c == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L460] COND FALSE !((int )e_wl == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L465] COND FALSE !((int )wl_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L473] COND FALSE !((int )wl_pc == 2) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L483] COND FALSE !((int )c1_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L492] COND FALSE !((int )c2_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L501] COND FALSE !((int )wb_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L510] COND FALSE !((int )e_c == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L515] COND FALSE !((int )e_e == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L520] COND FALSE !((int )e_f == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L525] COND FALSE !((int )e_g == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L530] COND FALSE !((int )e_c == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L535] COND FALSE !((int )e_wl == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L541] COND TRUE 1 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L544] kernel_st = 1 [L545] CALL eval() [L286] int tmp ; [L287] int tmp___0 ; [L288] int tmp___1 ; [L289] int tmp___2 ; [L290] int tmp___3 ; VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] Loop: [L294] COND TRUE 1 [L296] COND TRUE (int )wl_st == 0 [L317] COND TRUE (int )wl_st == 0 [L319] tmp = __VERIFIER_nondet_int() [L321] COND FALSE !(\read(tmp)) [L332] COND TRUE (int )c1_st == 0 [L334] tmp___0 = __VERIFIER_nondet_int() [L336] COND FALSE !(\read(tmp___0)) [L347] COND TRUE (int )c2_st == 0 [L349] tmp___1 = __VERIFIER_nondet_int() [L351] COND FALSE !(\read(tmp___1)) [L362] COND TRUE (int )wb_st == 0 [L364] tmp___2 = __VERIFIER_nondet_int() [L366] COND FALSE !(\read(tmp___2)) [L377] COND FALSE !((int )r_st == 0) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-03-04 16:21:38,502 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)