./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a30aa210ed4a7c8ee647a70aef136aef282e5eccb07388ecda6495e33bc30b6d --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-03 14:45:46,439 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-03 14:45:46,494 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2025-03-03 14:45:46,502 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-03 14:45:46,503 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-03 14:45:46,526 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-03 14:45:46,527 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-03 14:45:46,527 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-03 14:45:46,527 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-03 14:45:46,527 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-03 14:45:46,528 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2025-03-03 14:45:46,528 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2025-03-03 14:45:46,528 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-03 14:45:46,528 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-03 14:45:46,528 INFO L153 SettingsManager]: * Use SBE=true [2025-03-03 14:45:46,528 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-03 14:45:46,528 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2025-03-03 14:45:46,528 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-03 14:45:46,528 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-03 14:45:46,528 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-03 14:45:46,528 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-03 14:45:46,528 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2025-03-03 14:45:46,528 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2025-03-03 14:45:46,528 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-03 14:45:46,529 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2025-03-03 14:45:46,529 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * Compute procedure contracts=false [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2025-03-03 14:45:46,529 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2025-03-03 14:45:46,530 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2025-03-03 14:45:46,530 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2025-03-03 14:45:46,530 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a30aa210ed4a7c8ee647a70aef136aef282e5eccb07388ecda6495e33bc30b6d [2025-03-03 14:45:46,774 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-03 14:45:46,781 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-03 14:45:46,783 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-03 14:45:46,784 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-03 14:45:46,785 INFO L274 PluginConnector]: CDTParser initialized [2025-03-03 14:45:46,786 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c [2025-03-03 14:45:47,970 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7a2d6ec5d/81557c47174b48c1afc772f1f0d197b7/FLAG5d0ae9a0c [2025-03-03 14:45:48,296 INFO L384 CDTParser]: Found 1 translation units. [2025-03-03 14:45:48,298 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c [2025-03-03 14:45:48,311 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7a2d6ec5d/81557c47174b48c1afc772f1f0d197b7/FLAG5d0ae9a0c [2025-03-03 14:45:48,559 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7a2d6ec5d/81557c47174b48c1afc772f1f0d197b7 [2025-03-03 14:45:48,561 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-03 14:45:48,562 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-03 14:45:48,564 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-03 14:45:48,564 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-03 14:45:48,574 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-03 14:45:48,575 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,576 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@154be36a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48, skipping insertion in model container [2025-03-03 14:45:48,576 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,595 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-03 14:45:48,794 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c[14540,14553] [2025-03-03 14:45:48,800 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-03 14:45:48,809 INFO L200 MainTranslator]: Completed pre-run [2025-03-03 14:45:48,864 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c[14540,14553] [2025-03-03 14:45:48,865 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-03 14:45:48,879 INFO L204 MainTranslator]: Completed translation [2025-03-03 14:45:48,879 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48 WrapperNode [2025-03-03 14:45:48,879 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-03 14:45:48,880 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-03 14:45:48,880 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-03 14:45:48,880 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-03 14:45:48,884 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,891 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,917 INFO L138 Inliner]: procedures = 32, calls = 48, calls flagged for inlining = 12, calls inlined = 12, statements flattened = 502 [2025-03-03 14:45:48,917 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-03 14:45:48,918 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-03 14:45:48,918 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-03 14:45:48,918 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-03 14:45:48,924 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,924 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,927 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,938 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-03 14:45:48,939 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,939 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,947 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,949 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,950 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,952 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,959 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-03 14:45:48,960 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-03 14:45:48,960 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-03 14:45:48,960 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-03 14:45:48,961 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48" (1/1) ... [2025-03-03 14:45:48,966 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2025-03-03 14:45:48,975 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:45:48,987 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2025-03-03 14:45:48,993 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2025-03-03 14:45:49,009 INFO L130 BoogieDeclarations]: Found specification of procedure read_manual_selection_history [2025-03-03 14:45:49,009 INFO L138 BoogieDeclarations]: Found implementation of procedure read_manual_selection_history [2025-03-03 14:45:49,009 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-03 14:45:49,009 INFO L130 BoogieDeclarations]: Found specification of procedure read_side2_failed_history [2025-03-03 14:45:49,009 INFO L138 BoogieDeclarations]: Found implementation of procedure read_side2_failed_history [2025-03-03 14:45:49,009 INFO L130 BoogieDeclarations]: Found specification of procedure assert [2025-03-03 14:45:49,009 INFO L138 BoogieDeclarations]: Found implementation of procedure assert [2025-03-03 14:45:49,009 INFO L130 BoogieDeclarations]: Found specification of procedure flip_the_side [2025-03-03 14:45:49,009 INFO L138 BoogieDeclarations]: Found implementation of procedure flip_the_side [2025-03-03 14:45:49,009 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2025-03-03 14:45:49,009 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2025-03-03 14:45:49,009 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-03 14:45:49,010 INFO L130 BoogieDeclarations]: Found specification of procedure read_side1_failed_history [2025-03-03 14:45:49,010 INFO L138 BoogieDeclarations]: Found implementation of procedure read_side1_failed_history [2025-03-03 14:45:49,010 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-03 14:45:49,010 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-03 14:45:49,010 INFO L130 BoogieDeclarations]: Found specification of procedure read_active_side_history [2025-03-03 14:45:49,010 INFO L138 BoogieDeclarations]: Found implementation of procedure read_active_side_history [2025-03-03 14:45:49,111 INFO L256 CfgBuilder]: Building ICFG [2025-03-03 14:45:49,113 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-03 14:45:49,559 INFO L? ?]: Removed 113 outVars from TransFormulas that were not future-live. [2025-03-03 14:45:49,560 INFO L307 CfgBuilder]: Performing block encoding [2025-03-03 14:45:49,570 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-03 14:45:49,573 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-03 14:45:49,574 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 03.03 02:45:49 BoogieIcfgContainer [2025-03-03 14:45:49,574 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-03 14:45:49,575 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2025-03-03 14:45:49,576 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2025-03-03 14:45:49,579 INFO L274 PluginConnector]: TraceAbstraction initialized [2025-03-03 14:45:49,580 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.03 02:45:48" (1/3) ... [2025-03-03 14:45:49,580 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5839a2b8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.03 02:45:49, skipping insertion in model container [2025-03-03 14:45:49,580 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:48" (2/3) ... [2025-03-03 14:45:49,580 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5839a2b8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.03 02:45:49, skipping insertion in model container [2025-03-03 14:45:49,580 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 03.03 02:45:49" (3/3) ... [2025-03-03 14:45:49,581 INFO L128 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c [2025-03-03 14:45:49,592 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2025-03-03 14:45:49,593 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG pals_STARTPALS_ActiveStandby.4_1.ufo.BOUNDED-10.pals.c that has 8 procedures, 178 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2025-03-03 14:45:49,657 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2025-03-03 14:45:49,665 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@15082571, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2025-03-03 14:45:49,665 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2025-03-03 14:45:49,668 INFO L276 IsEmpty]: Start isEmpty. Operand has 178 states, 138 states have (on average 1.5434782608695652) internal successors, (213), 139 states have internal predecessors, (213), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-03 14:45:49,673 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2025-03-03 14:45:49,673 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:49,673 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:49,673 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:49,677 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:49,677 INFO L85 PathProgramCache]: Analyzing trace with hash 1289772300, now seen corresponding path program 1 times [2025-03-03 14:45:49,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:49,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448794330] [2025-03-03 14:45:49,683 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:49,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:49,743 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-03 14:45:49,787 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-03 14:45:49,788 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:49,788 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:49,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-03 14:45:49,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:49,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [448794330] [2025-03-03 14:45:49,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [448794330] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:49,896 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:49,897 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-03 14:45:49,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [214676382] [2025-03-03 14:45:49,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:49,905 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2025-03-03 14:45:49,906 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:49,920 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-03 14:45:49,921 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-03 14:45:49,923 INFO L87 Difference]: Start difference. First operand has 178 states, 138 states have (on average 1.5434782608695652) internal successors, (213), 139 states have internal predecessors, (213), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) Second operand has 2 states, 2 states have (on average 12.0) internal successors, (24), 2 states have internal predecessors, (24), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-03 14:45:49,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:49,954 INFO L93 Difference]: Finished difference Result 340 states and 550 transitions. [2025-03-03 14:45:49,955 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-03 14:45:49,956 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 12.0) internal successors, (24), 2 states have internal predecessors, (24), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 28 [2025-03-03 14:45:49,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:49,961 INFO L225 Difference]: With dead ends: 340 [2025-03-03 14:45:49,961 INFO L226 Difference]: Without dead ends: 175 [2025-03-03 14:45:49,964 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-03 14:45:49,966 INFO L435 NwaCegarLoop]: 273 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 273 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:49,967 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 273 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:49,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2025-03-03 14:45:49,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 175. [2025-03-03 14:45:49,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 175 states, 136 states have (on average 1.5294117647058822) internal successors, (208), 136 states have internal predecessors, (208), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-03 14:45:50,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 270 transitions. [2025-03-03 14:45:50,006 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 270 transitions. Word has length 28 [2025-03-03 14:45:50,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:50,007 INFO L471 AbstractCegarLoop]: Abstraction has 175 states and 270 transitions. [2025-03-03 14:45:50,007 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 12.0) internal successors, (24), 2 states have internal predecessors, (24), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-03 14:45:50,007 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 270 transitions. [2025-03-03 14:45:50,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2025-03-03 14:45:50,008 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:50,008 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:50,008 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2025-03-03 14:45:50,008 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:50,009 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:50,009 INFO L85 PathProgramCache]: Analyzing trace with hash -748283989, now seen corresponding path program 1 times [2025-03-03 14:45:50,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:50,009 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [363270563] [2025-03-03 14:45:50,009 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:50,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:50,022 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-03 14:45:50,037 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-03 14:45:50,038 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:50,038 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:50,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-03 14:45:50,223 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:50,223 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [363270563] [2025-03-03 14:45:50,223 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [363270563] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:50,223 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:50,223 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-03 14:45:50,223 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190529954] [2025-03-03 14:45:50,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:50,224 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2025-03-03 14:45:50,224 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:50,224 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-03 14:45:50,224 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-03 14:45:50,225 INFO L87 Difference]: Start difference. First operand 175 states and 270 transitions. Second operand has 6 states, 5 states have (on average 4.8) internal successors, (24), 6 states have internal predecessors, (24), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-03 14:45:50,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:50,320 INFO L93 Difference]: Finished difference Result 447 states and 697 transitions. [2025-03-03 14:45:50,321 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-03 14:45:50,321 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 4.8) internal successors, (24), 6 states have internal predecessors, (24), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 28 [2025-03-03 14:45:50,321 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:50,324 INFO L225 Difference]: With dead ends: 447 [2025-03-03 14:45:50,324 INFO L226 Difference]: Without dead ends: 286 [2025-03-03 14:45:50,327 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-03 14:45:50,328 INFO L435 NwaCegarLoop]: 264 mSDtfsCounter, 130 mSDsluCounter, 1033 mSDsCounter, 0 mSdLazyCounter, 37 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 156 SdHoareTripleChecker+Valid, 1297 SdHoareTripleChecker+Invalid, 49 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 37 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:50,328 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [156 Valid, 1297 Invalid, 49 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 37 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:45:50,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286 states. [2025-03-03 14:45:50,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286 to 175. [2025-03-03 14:45:50,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 175 states, 136 states have (on average 1.4411764705882353) internal successors, (196), 136 states have internal predecessors, (196), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-03 14:45:50,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 258 transitions. [2025-03-03 14:45:50,348 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 258 transitions. Word has length 28 [2025-03-03 14:45:50,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:50,349 INFO L471 AbstractCegarLoop]: Abstraction has 175 states and 258 transitions. [2025-03-03 14:45:50,349 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 4.8) internal successors, (24), 6 states have internal predecessors, (24), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-03 14:45:50,349 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 258 transitions. [2025-03-03 14:45:50,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2025-03-03 14:45:50,349 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:50,350 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:50,350 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2025-03-03 14:45:50,350 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:50,350 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:50,350 INFO L85 PathProgramCache]: Analyzing trace with hash 1326921225, now seen corresponding path program 1 times [2025-03-03 14:45:50,350 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:50,350 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112988466] [2025-03-03 14:45:50,351 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:50,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:50,381 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-03 14:45:50,411 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-03 14:45:50,412 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:50,413 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:50,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-03 14:45:50,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:50,581 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1112988466] [2025-03-03 14:45:50,581 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1112988466] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:50,581 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:50,581 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:50,581 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34209344] [2025-03-03 14:45:50,582 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:50,582 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:50,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:50,582 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:50,582 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:50,582 INFO L87 Difference]: Start difference. First operand 175 states and 258 transitions. Second operand has 4 states, 4 states have (on average 8.75) internal successors, (35), 3 states have internal predecessors, (35), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-03 14:45:50,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:50,641 INFO L93 Difference]: Finished difference Result 337 states and 506 transitions. [2025-03-03 14:45:50,641 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:50,642 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 8.75) internal successors, (35), 3 states have internal predecessors, (35), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 39 [2025-03-03 14:45:50,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:50,643 INFO L225 Difference]: With dead ends: 337 [2025-03-03 14:45:50,643 INFO L226 Difference]: Without dead ends: 179 [2025-03-03 14:45:50,644 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:50,644 INFO L435 NwaCegarLoop]: 252 mSDtfsCounter, 3 mSDsluCounter, 494 mSDsCounter, 0 mSdLazyCounter, 24 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 746 SdHoareTripleChecker+Invalid, 27 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 24 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:50,644 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 746 Invalid, 27 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 24 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:50,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2025-03-03 14:45:50,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2025-03-03 14:45:50,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 139 states have (on average 1.4316546762589928) internal successors, (199), 139 states have internal predecessors, (199), 31 states have call successors, (31), 8 states have call predecessors, (31), 8 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-03 14:45:50,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 261 transitions. [2025-03-03 14:45:50,653 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 261 transitions. Word has length 39 [2025-03-03 14:45:50,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:50,653 INFO L471 AbstractCegarLoop]: Abstraction has 179 states and 261 transitions. [2025-03-03 14:45:50,653 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 8.75) internal successors, (35), 3 states have internal predecessors, (35), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-03 14:45:50,653 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 261 transitions. [2025-03-03 14:45:50,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2025-03-03 14:45:50,654 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:50,654 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:50,654 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2025-03-03 14:45:50,654 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:50,655 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:50,655 INFO L85 PathProgramCache]: Analyzing trace with hash 1877633670, now seen corresponding path program 1 times [2025-03-03 14:45:50,655 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:50,655 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [397505656] [2025-03-03 14:45:50,655 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:50,656 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:50,672 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 55 statements into 1 equivalence classes. [2025-03-03 14:45:50,690 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 55 of 55 statements. [2025-03-03 14:45:50,691 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:50,691 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:50,753 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:50,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:50,754 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [397505656] [2025-03-03 14:45:50,754 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [397505656] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:50,754 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:50,754 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-03 14:45:50,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407930456] [2025-03-03 14:45:50,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:50,755 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-03-03 14:45:50,755 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:50,756 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-03 14:45:50,756 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-03 14:45:50,756 INFO L87 Difference]: Start difference. First operand 179 states and 261 transitions. Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:50,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:50,793 INFO L93 Difference]: Finished difference Result 491 states and 726 transitions. [2025-03-03 14:45:50,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-03 14:45:50,794 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 55 [2025-03-03 14:45:50,794 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:50,796 INFO L225 Difference]: With dead ends: 491 [2025-03-03 14:45:50,796 INFO L226 Difference]: Without dead ends: 329 [2025-03-03 14:45:50,797 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-03 14:45:50,797 INFO L435 NwaCegarLoop]: 268 mSDtfsCounter, 209 mSDsluCounter, 249 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 209 SdHoareTripleChecker+Valid, 517 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:50,797 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [209 Valid, 517 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:50,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 329 states. [2025-03-03 14:45:50,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 329 to 323. [2025-03-03 14:45:50,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 246 states have (on average 1.451219512195122) internal successors, (357), 247 states have internal predecessors, (357), 60 states have call successors, (60), 16 states have call predecessors, (60), 16 states have return successors, (60), 59 states have call predecessors, (60), 60 states have call successors, (60) [2025-03-03 14:45:50,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 477 transitions. [2025-03-03 14:45:50,830 INFO L78 Accepts]: Start accepts. Automaton has 323 states and 477 transitions. Word has length 55 [2025-03-03 14:45:50,831 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:50,831 INFO L471 AbstractCegarLoop]: Abstraction has 323 states and 477 transitions. [2025-03-03 14:45:50,831 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:50,831 INFO L276 IsEmpty]: Start isEmpty. Operand 323 states and 477 transitions. [2025-03-03 14:45:50,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2025-03-03 14:45:50,833 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:50,833 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:50,834 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2025-03-03 14:45:50,834 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:50,834 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:50,835 INFO L85 PathProgramCache]: Analyzing trace with hash -276221848, now seen corresponding path program 1 times [2025-03-03 14:45:50,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:50,835 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223691362] [2025-03-03 14:45:50,835 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:50,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:50,853 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-03-03 14:45:50,867 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-03-03 14:45:50,867 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:50,867 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:50,913 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:50,913 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:50,913 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1223691362] [2025-03-03 14:45:50,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1223691362] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:50,914 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:50,914 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-03 14:45:50,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2113965579] [2025-03-03 14:45:50,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:50,914 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-03-03 14:45:50,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:50,914 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-03 14:45:50,914 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-03 14:45:50,915 INFO L87 Difference]: Start difference. First operand 323 states and 477 transitions. Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:50,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:50,958 INFO L93 Difference]: Finished difference Result 908 states and 1352 transitions. [2025-03-03 14:45:50,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-03 14:45:50,959 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 56 [2025-03-03 14:45:50,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:50,965 INFO L225 Difference]: With dead ends: 908 [2025-03-03 14:45:50,965 INFO L226 Difference]: Without dead ends: 602 [2025-03-03 14:45:50,967 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-03 14:45:50,967 INFO L435 NwaCegarLoop]: 288 mSDtfsCounter, 211 mSDsluCounter, 251 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 211 SdHoareTripleChecker+Valid, 539 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:50,967 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [211 Valid, 539 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:50,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 602 states. [2025-03-03 14:45:51,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 602 to 596. [2025-03-03 14:45:51,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 596 states, 447 states have (on average 1.4608501118568233) internal successors, (653), 450 states have internal predecessors, (653), 117 states have call successors, (117), 31 states have call predecessors, (117), 31 states have return successors, (117), 114 states have call predecessors, (117), 117 states have call successors, (117) [2025-03-03 14:45:51,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 596 states to 596 states and 887 transitions. [2025-03-03 14:45:51,015 INFO L78 Accepts]: Start accepts. Automaton has 596 states and 887 transitions. Word has length 56 [2025-03-03 14:45:51,015 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:51,015 INFO L471 AbstractCegarLoop]: Abstraction has 596 states and 887 transitions. [2025-03-03 14:45:51,016 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:51,017 INFO L276 IsEmpty]: Start isEmpty. Operand 596 states and 887 transitions. [2025-03-03 14:45:51,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2025-03-03 14:45:51,022 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:51,022 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:51,022 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2025-03-03 14:45:51,022 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:51,022 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:51,023 INFO L85 PathProgramCache]: Analyzing trace with hash 1231329961, now seen corresponding path program 1 times [2025-03-03 14:45:51,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:51,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303903429] [2025-03-03 14:45:51,023 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:51,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:51,048 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-03-03 14:45:51,073 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-03-03 14:45:51,073 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:51,074 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:51,170 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:51,171 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:51,171 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303903429] [2025-03-03 14:45:51,171 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1303903429] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:51,171 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:51,171 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-03 14:45:51,171 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1583718908] [2025-03-03 14:45:51,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:51,171 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-03-03 14:45:51,172 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:51,172 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-03 14:45:51,173 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:51,173 INFO L87 Difference]: Start difference. First operand 596 states and 887 transitions. Second operand has 5 states, 5 states have (on average 9.0) internal successors, (45), 5 states have internal predecessors, (45), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:51,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:51,323 INFO L93 Difference]: Finished difference Result 1275 states and 1892 transitions. [2025-03-03 14:45:51,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-03 14:45:51,324 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 9.0) internal successors, (45), 5 states have internal predecessors, (45), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 56 [2025-03-03 14:45:51,324 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:51,331 INFO L225 Difference]: With dead ends: 1275 [2025-03-03 14:45:51,331 INFO L226 Difference]: Without dead ends: 696 [2025-03-03 14:45:51,333 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:51,333 INFO L435 NwaCegarLoop]: 226 mSDtfsCounter, 356 mSDsluCounter, 442 mSDsCounter, 0 mSdLazyCounter, 94 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 356 SdHoareTripleChecker+Valid, 668 SdHoareTripleChecker+Invalid, 108 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 94 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:51,333 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [356 Valid, 668 Invalid, 108 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 94 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:45:51,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 696 states. [2025-03-03 14:45:51,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 696 to 684. [2025-03-03 14:45:51,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 684 states, 522 states have (on average 1.446360153256705) internal successors, (755), 525 states have internal predecessors, (755), 124 states have call successors, (124), 37 states have call predecessors, (124), 37 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:51,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 684 states to 684 states and 1003 transitions. [2025-03-03 14:45:51,390 INFO L78 Accepts]: Start accepts. Automaton has 684 states and 1003 transitions. Word has length 56 [2025-03-03 14:45:51,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:51,390 INFO L471 AbstractCegarLoop]: Abstraction has 684 states and 1003 transitions. [2025-03-03 14:45:51,390 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 9.0) internal successors, (45), 5 states have internal predecessors, (45), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:51,391 INFO L276 IsEmpty]: Start isEmpty. Operand 684 states and 1003 transitions. [2025-03-03 14:45:51,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2025-03-03 14:45:51,393 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:51,393 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:51,393 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2025-03-03 14:45:51,393 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:51,394 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:51,394 INFO L85 PathProgramCache]: Analyzing trace with hash 2023849006, now seen corresponding path program 1 times [2025-03-03 14:45:51,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:51,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967057189] [2025-03-03 14:45:51,394 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:51,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:51,407 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 57 statements into 1 equivalence classes. [2025-03-03 14:45:51,425 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 57 of 57 statements. [2025-03-03 14:45:51,425 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:51,425 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:51,512 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:51,512 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:51,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967057189] [2025-03-03 14:45:51,512 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967057189] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:51,512 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:51,512 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-03 14:45:51,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067871223] [2025-03-03 14:45:51,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:51,512 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-03-03 14:45:51,512 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:51,513 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-03 14:45:51,513 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:51,513 INFO L87 Difference]: Start difference. First operand 684 states and 1003 transitions. Second operand has 5 states, 5 states have (on average 9.2) internal successors, (46), 5 states have internal predecessors, (46), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:51,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:51,653 INFO L93 Difference]: Finished difference Result 1275 states and 1884 transitions. [2025-03-03 14:45:51,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-03 14:45:51,654 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 9.2) internal successors, (46), 5 states have internal predecessors, (46), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 57 [2025-03-03 14:45:51,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:51,658 INFO L225 Difference]: With dead ends: 1275 [2025-03-03 14:45:51,658 INFO L226 Difference]: Without dead ends: 696 [2025-03-03 14:45:51,660 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:51,661 INFO L435 NwaCegarLoop]: 227 mSDtfsCounter, 353 mSDsluCounter, 444 mSDsCounter, 0 mSdLazyCounter, 91 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 353 SdHoareTripleChecker+Valid, 671 SdHoareTripleChecker+Invalid, 104 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 91 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:51,661 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [353 Valid, 671 Invalid, 104 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 91 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:45:51,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 696 states. [2025-03-03 14:45:51,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 696 to 684. [2025-03-03 14:45:51,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 684 states, 522 states have (on average 1.4386973180076628) internal successors, (751), 525 states have internal predecessors, (751), 124 states have call successors, (124), 37 states have call predecessors, (124), 37 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:51,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 684 states to 684 states and 999 transitions. [2025-03-03 14:45:51,723 INFO L78 Accepts]: Start accepts. Automaton has 684 states and 999 transitions. Word has length 57 [2025-03-03 14:45:51,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:51,724 INFO L471 AbstractCegarLoop]: Abstraction has 684 states and 999 transitions. [2025-03-03 14:45:51,724 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 9.2) internal successors, (46), 5 states have internal predecessors, (46), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:51,724 INFO L276 IsEmpty]: Start isEmpty. Operand 684 states and 999 transitions. [2025-03-03 14:45:51,725 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2025-03-03 14:45:51,725 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:51,725 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:51,725 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2025-03-03 14:45:51,725 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:51,726 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:51,726 INFO L85 PathProgramCache]: Analyzing trace with hash -827038876, now seen corresponding path program 1 times [2025-03-03 14:45:51,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:51,726 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1602684096] [2025-03-03 14:45:51,726 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:51,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:51,738 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 58 statements into 1 equivalence classes. [2025-03-03 14:45:51,750 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 58 of 58 statements. [2025-03-03 14:45:51,750 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:51,750 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:51,885 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:51,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:51,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1602684096] [2025-03-03 14:45:51,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1602684096] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:51,886 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:51,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:51,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1031623183] [2025-03-03 14:45:51,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:51,886 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:51,886 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:51,887 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:51,887 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:51,887 INFO L87 Difference]: Start difference. First operand 684 states and 999 transitions. Second operand has 4 states, 4 states have (on average 11.75) internal successors, (47), 3 states have internal predecessors, (47), 2 states have call successors, (5), 3 states have call predecessors, (5), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2025-03-03 14:45:51,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:51,937 INFO L93 Difference]: Finished difference Result 1283 states and 1896 transitions. [2025-03-03 14:45:51,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:51,938 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 11.75) internal successors, (47), 3 states have internal predecessors, (47), 2 states have call successors, (5), 3 states have call predecessors, (5), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 58 [2025-03-03 14:45:51,938 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:51,942 INFO L225 Difference]: With dead ends: 1283 [2025-03-03 14:45:51,942 INFO L226 Difference]: Without dead ends: 704 [2025-03-03 14:45:51,944 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:51,944 INFO L435 NwaCegarLoop]: 254 mSDtfsCounter, 4 mSDsluCounter, 504 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 758 SdHoareTripleChecker+Invalid, 16 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:51,944 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 758 Invalid, 16 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:51,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 704 states. [2025-03-03 14:45:51,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 704 to 704. [2025-03-03 14:45:51,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 704 states, 538 states have (on average 1.4256505576208178) internal successors, (767), 541 states have internal predecessors, (767), 124 states have call successors, (124), 41 states have call predecessors, (124), 41 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:51,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 704 states to 704 states and 1015 transitions. [2025-03-03 14:45:51,993 INFO L78 Accepts]: Start accepts. Automaton has 704 states and 1015 transitions. Word has length 58 [2025-03-03 14:45:51,993 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:51,993 INFO L471 AbstractCegarLoop]: Abstraction has 704 states and 1015 transitions. [2025-03-03 14:45:51,993 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 11.75) internal successors, (47), 3 states have internal predecessors, (47), 2 states have call successors, (5), 3 states have call predecessors, (5), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2025-03-03 14:45:51,993 INFO L276 IsEmpty]: Start isEmpty. Operand 704 states and 1015 transitions. [2025-03-03 14:45:51,994 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2025-03-03 14:45:51,994 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:51,994 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:51,994 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2025-03-03 14:45:51,995 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:51,995 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:51,995 INFO L85 PathProgramCache]: Analyzing trace with hash 283408038, now seen corresponding path program 1 times [2025-03-03 14:45:51,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:51,995 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071962904] [2025-03-03 14:45:51,995 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:51,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:52,006 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 66 statements into 1 equivalence classes. [2025-03-03 14:45:52,017 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 66 of 66 statements. [2025-03-03 14:45:52,017 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:52,018 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:52,145 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:52,146 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:52,146 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1071962904] [2025-03-03 14:45:52,146 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1071962904] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:52,146 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:52,146 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:52,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229855615] [2025-03-03 14:45:52,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:52,146 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:52,146 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:52,147 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:52,147 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:52,147 INFO L87 Difference]: Start difference. First operand 704 states and 1015 transitions. Second operand has 4 states, 4 states have (on average 13.25) internal successors, (53), 3 states have internal predecessors, (53), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (4), 1 states have call predecessors, (4), 1 states have call successors, (4) [2025-03-03 14:45:52,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:52,228 INFO L93 Difference]: Finished difference Result 1323 states and 1940 transitions. [2025-03-03 14:45:52,229 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:52,229 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 13.25) internal successors, (53), 3 states have internal predecessors, (53), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (4), 1 states have call predecessors, (4), 1 states have call successors, (4) Word has length 66 [2025-03-03 14:45:52,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:52,233 INFO L225 Difference]: With dead ends: 1323 [2025-03-03 14:45:52,233 INFO L226 Difference]: Without dead ends: 724 [2025-03-03 14:45:52,234 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:52,235 INFO L435 NwaCegarLoop]: 251 mSDtfsCounter, 4 mSDsluCounter, 493 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 744 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:52,235 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 744 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:52,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 724 states. [2025-03-03 14:45:52,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 724 to 724. [2025-03-03 14:45:52,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 724 states, 554 states have (on average 1.4133574007220218) internal successors, (783), 557 states have internal predecessors, (783), 124 states have call successors, (124), 45 states have call predecessors, (124), 45 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:52,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 724 states to 724 states and 1031 transitions. [2025-03-03 14:45:52,275 INFO L78 Accepts]: Start accepts. Automaton has 724 states and 1031 transitions. Word has length 66 [2025-03-03 14:45:52,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:52,275 INFO L471 AbstractCegarLoop]: Abstraction has 724 states and 1031 transitions. [2025-03-03 14:45:52,275 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 13.25) internal successors, (53), 3 states have internal predecessors, (53), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (4), 1 states have call predecessors, (4), 1 states have call successors, (4) [2025-03-03 14:45:52,275 INFO L276 IsEmpty]: Start isEmpty. Operand 724 states and 1031 transitions. [2025-03-03 14:45:52,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2025-03-03 14:45:52,276 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:52,276 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:52,277 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2025-03-03 14:45:52,277 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:52,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:52,277 INFO L85 PathProgramCache]: Analyzing trace with hash -175449556, now seen corresponding path program 1 times [2025-03-03 14:45:52,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:52,277 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326773840] [2025-03-03 14:45:52,277 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:52,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:52,288 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes. [2025-03-03 14:45:52,299 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements. [2025-03-03 14:45:52,300 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:52,300 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:52,390 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:52,390 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:52,390 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1326773840] [2025-03-03 14:45:52,390 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1326773840] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:52,390 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:52,390 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:52,391 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1198537881] [2025-03-03 14:45:52,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:52,391 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:52,391 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:52,391 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:52,391 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:52,391 INFO L87 Difference]: Start difference. First operand 724 states and 1031 transitions. Second operand has 4 states, 4 states have (on average 14.75) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-03 14:45:52,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:52,476 INFO L93 Difference]: Finished difference Result 1359 states and 1956 transitions. [2025-03-03 14:45:52,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:52,476 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.75) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 74 [2025-03-03 14:45:52,477 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:52,480 INFO L225 Difference]: With dead ends: 1359 [2025-03-03 14:45:52,481 INFO L226 Difference]: Without dead ends: 740 [2025-03-03 14:45:52,482 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:52,483 INFO L435 NwaCegarLoop]: 256 mSDtfsCounter, 3 mSDsluCounter, 498 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 754 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:52,483 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 754 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:52,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 740 states. [2025-03-03 14:45:52,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 740 to 740. [2025-03-03 14:45:52,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 740 states, 566 states have (on average 1.4045936395759717) internal successors, (795), 569 states have internal predecessors, (795), 124 states have call successors, (124), 49 states have call predecessors, (124), 49 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:52,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 740 states to 740 states and 1043 transitions. [2025-03-03 14:45:52,522 INFO L78 Accepts]: Start accepts. Automaton has 740 states and 1043 transitions. Word has length 74 [2025-03-03 14:45:52,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:52,523 INFO L471 AbstractCegarLoop]: Abstraction has 740 states and 1043 transitions. [2025-03-03 14:45:52,523 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.75) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-03 14:45:52,523 INFO L276 IsEmpty]: Start isEmpty. Operand 740 states and 1043 transitions. [2025-03-03 14:45:52,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2025-03-03 14:45:52,524 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:52,524 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:52,524 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2025-03-03 14:45:52,525 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:52,525 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:52,525 INFO L85 PathProgramCache]: Analyzing trace with hash -807377819, now seen corresponding path program 1 times [2025-03-03 14:45:52,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:52,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145640920] [2025-03-03 14:45:52,525 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:52,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:52,536 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes. [2025-03-03 14:45:52,546 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements. [2025-03-03 14:45:52,546 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:52,546 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:52,664 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:52,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:52,664 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2145640920] [2025-03-03 14:45:52,665 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2145640920] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:52,665 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:52,665 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:52,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780102592] [2025-03-03 14:45:52,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:52,665 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:52,665 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:52,665 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:52,665 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:52,666 INFO L87 Difference]: Start difference. First operand 740 states and 1043 transitions. Second operand has 4 states, 4 states have (on average 14.75) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-03 14:45:52,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:52,737 INFO L93 Difference]: Finished difference Result 1395 states and 1996 transitions. [2025-03-03 14:45:52,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:52,738 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.75) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 74 [2025-03-03 14:45:52,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:52,742 INFO L225 Difference]: With dead ends: 1395 [2025-03-03 14:45:52,743 INFO L226 Difference]: Without dead ends: 760 [2025-03-03 14:45:52,746 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:52,747 INFO L435 NwaCegarLoop]: 251 mSDtfsCounter, 4 mSDsluCounter, 493 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 744 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:52,747 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 744 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:52,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 760 states. [2025-03-03 14:45:52,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 760 to 760. [2025-03-03 14:45:52,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 760 states, 582 states have (on average 1.3934707903780068) internal successors, (811), 585 states have internal predecessors, (811), 124 states have call successors, (124), 53 states have call predecessors, (124), 53 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:52,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 760 states to 760 states and 1059 transitions. [2025-03-03 14:45:52,798 INFO L78 Accepts]: Start accepts. Automaton has 760 states and 1059 transitions. Word has length 74 [2025-03-03 14:45:52,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:52,798 INFO L471 AbstractCegarLoop]: Abstraction has 760 states and 1059 transitions. [2025-03-03 14:45:52,798 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.75) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-03 14:45:52,798 INFO L276 IsEmpty]: Start isEmpty. Operand 760 states and 1059 transitions. [2025-03-03 14:45:52,801 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2025-03-03 14:45:52,801 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:52,801 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:52,804 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2025-03-03 14:45:52,804 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:52,805 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:52,805 INFO L85 PathProgramCache]: Analyzing trace with hash -262487165, now seen corresponding path program 1 times [2025-03-03 14:45:52,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:52,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706947144] [2025-03-03 14:45:52,805 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:52,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:52,819 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 82 statements into 1 equivalence classes. [2025-03-03 14:45:52,844 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 82 of 82 statements. [2025-03-03 14:45:52,845 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:52,845 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:53,003 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-03 14:45:53,003 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:53,003 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706947144] [2025-03-03 14:45:53,003 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [706947144] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:53,004 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:53,004 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:53,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [307544479] [2025-03-03 14:45:53,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:53,004 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:53,004 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:53,005 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:53,005 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:53,005 INFO L87 Difference]: Start difference. First operand 760 states and 1059 transitions. Second operand has 4 states, 4 states have (on average 15.25) internal successors, (61), 3 states have internal predecessors, (61), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 1 states have call predecessors, (6), 1 states have call successors, (6) [2025-03-03 14:45:53,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:53,065 INFO L93 Difference]: Finished difference Result 1439 states and 2024 transitions. [2025-03-03 14:45:53,065 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:53,066 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 15.25) internal successors, (61), 3 states have internal predecessors, (61), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 1 states have call predecessors, (6), 1 states have call successors, (6) Word has length 82 [2025-03-03 14:45:53,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:53,070 INFO L225 Difference]: With dead ends: 1439 [2025-03-03 14:45:53,070 INFO L226 Difference]: Without dead ends: 784 [2025-03-03 14:45:53,071 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:53,072 INFO L435 NwaCegarLoop]: 255 mSDtfsCounter, 5 mSDsluCounter, 501 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5 SdHoareTripleChecker+Valid, 756 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:53,072 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [5 Valid, 756 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 20 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:53,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 784 states. [2025-03-03 14:45:53,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 784 to 784. [2025-03-03 14:45:53,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 784 states, 602 states have (on average 1.3803986710963456) internal successors, (831), 605 states have internal predecessors, (831), 124 states have call successors, (124), 57 states have call predecessors, (124), 57 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:53,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 784 states to 784 states and 1079 transitions. [2025-03-03 14:45:53,118 INFO L78 Accepts]: Start accepts. Automaton has 784 states and 1079 transitions. Word has length 82 [2025-03-03 14:45:53,118 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:53,118 INFO L471 AbstractCegarLoop]: Abstraction has 784 states and 1079 transitions. [2025-03-03 14:45:53,118 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 15.25) internal successors, (61), 3 states have internal predecessors, (61), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 1 states have call predecessors, (6), 1 states have call successors, (6) [2025-03-03 14:45:53,119 INFO L276 IsEmpty]: Start isEmpty. Operand 784 states and 1079 transitions. [2025-03-03 14:45:53,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2025-03-03 14:45:53,120 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:53,120 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:53,120 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2025-03-03 14:45:53,120 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:53,121 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:53,121 INFO L85 PathProgramCache]: Analyzing trace with hash -105403367, now seen corresponding path program 1 times [2025-03-03 14:45:53,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:53,121 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [952867568] [2025-03-03 14:45:53,121 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:53,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:53,132 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 85 statements into 1 equivalence classes. [2025-03-03 14:45:53,181 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 85 of 85 statements. [2025-03-03 14:45:53,181 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:53,181 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:53,558 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2025-03-03 14:45:53,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:53,558 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [952867568] [2025-03-03 14:45:53,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [952867568] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:53,558 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:53,558 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-03 14:45:53,558 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481920679] [2025-03-03 14:45:53,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:53,559 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-03 14:45:53,559 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:53,559 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-03 14:45:53,559 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:53,559 INFO L87 Difference]: Start difference. First operand 784 states and 1079 transitions. Second operand has 7 states, 7 states have (on average 9.142857142857142) internal successors, (64), 6 states have internal predecessors, (64), 3 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 4 states have call predecessors, (7), 3 states have call successors, (7) [2025-03-03 14:45:53,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:53,805 INFO L93 Difference]: Finished difference Result 2035 states and 2789 transitions. [2025-03-03 14:45:53,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-03 14:45:53,806 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 9.142857142857142) internal successors, (64), 6 states have internal predecessors, (64), 3 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 4 states have call predecessors, (7), 3 states have call successors, (7) Word has length 85 [2025-03-03 14:45:53,806 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:53,814 INFO L225 Difference]: With dead ends: 2035 [2025-03-03 14:45:53,814 INFO L226 Difference]: Without dead ends: 1356 [2025-03-03 14:45:53,816 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:45:53,816 INFO L435 NwaCegarLoop]: 255 mSDtfsCounter, 210 mSDsluCounter, 1170 mSDsCounter, 0 mSdLazyCounter, 98 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 214 SdHoareTripleChecker+Valid, 1425 SdHoareTripleChecker+Invalid, 105 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 98 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:53,817 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [214 Valid, 1425 Invalid, 105 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 98 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:45:53,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1356 states. [2025-03-03 14:45:53,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1356 to 1068. [2025-03-03 14:45:53,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1068 states, 813 states have (on average 1.3690036900369005) internal successors, (1113), 818 states have internal predecessors, (1113), 172 states have call successors, (172), 82 states have call predecessors, (172), 82 states have return successors, (172), 167 states have call predecessors, (172), 172 states have call successors, (172) [2025-03-03 14:45:53,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1068 states to 1068 states and 1457 transitions. [2025-03-03 14:45:53,885 INFO L78 Accepts]: Start accepts. Automaton has 1068 states and 1457 transitions. Word has length 85 [2025-03-03 14:45:53,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:53,886 INFO L471 AbstractCegarLoop]: Abstraction has 1068 states and 1457 transitions. [2025-03-03 14:45:53,886 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 9.142857142857142) internal successors, (64), 6 states have internal predecessors, (64), 3 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 4 states have call predecessors, (7), 3 states have call successors, (7) [2025-03-03 14:45:53,886 INFO L276 IsEmpty]: Start isEmpty. Operand 1068 states and 1457 transitions. [2025-03-03 14:45:53,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2025-03-03 14:45:53,887 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:53,887 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:53,887 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2025-03-03 14:45:53,888 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:53,888 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:53,888 INFO L85 PathProgramCache]: Analyzing trace with hash -838728871, now seen corresponding path program 1 times [2025-03-03 14:45:53,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:53,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53831486] [2025-03-03 14:45:53,888 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:53,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:53,899 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-03 14:45:53,914 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-03 14:45:53,914 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:53,914 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:54,028 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2025-03-03 14:45:54,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:54,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53831486] [2025-03-03 14:45:54,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53831486] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:54,028 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:54,028 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:54,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [224437147] [2025-03-03 14:45:54,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:54,029 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:54,029 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:54,029 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:54,029 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:54,029 INFO L87 Difference]: Start difference. First operand 1068 states and 1457 transitions. Second operand has 4 states, 4 states have (on average 17.0) internal successors, (68), 3 states have internal predecessors, (68), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-03 14:45:54,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:54,106 INFO L93 Difference]: Finished difference Result 1987 states and 2732 transitions. [2025-03-03 14:45:54,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:54,106 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 17.0) internal successors, (68), 3 states have internal predecessors, (68), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) Word has length 89 [2025-03-03 14:45:54,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:54,111 INFO L225 Difference]: With dead ends: 1987 [2025-03-03 14:45:54,112 INFO L226 Difference]: Without dead ends: 1092 [2025-03-03 14:45:54,113 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:54,114 INFO L435 NwaCegarLoop]: 256 mSDtfsCounter, 3 mSDsluCounter, 498 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 754 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:54,114 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 754 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:54,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1092 states. [2025-03-03 14:45:54,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1092 to 1092. [2025-03-03 14:45:54,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1092 states, 831 states have (on average 1.3610108303249098) internal successors, (1131), 836 states have internal predecessors, (1131), 172 states have call successors, (172), 88 states have call predecessors, (172), 88 states have return successors, (172), 167 states have call predecessors, (172), 172 states have call successors, (172) [2025-03-03 14:45:54,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1092 states to 1092 states and 1475 transitions. [2025-03-03 14:45:54,170 INFO L78 Accepts]: Start accepts. Automaton has 1092 states and 1475 transitions. Word has length 89 [2025-03-03 14:45:54,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:54,170 INFO L471 AbstractCegarLoop]: Abstraction has 1092 states and 1475 transitions. [2025-03-03 14:45:54,170 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 17.0) internal successors, (68), 3 states have internal predecessors, (68), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-03 14:45:54,171 INFO L276 IsEmpty]: Start isEmpty. Operand 1092 states and 1475 transitions. [2025-03-03 14:45:54,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2025-03-03 14:45:54,171 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:54,172 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:54,172 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2025-03-03 14:45:54,172 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:54,172 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:54,172 INFO L85 PathProgramCache]: Analyzing trace with hash 508507787, now seen corresponding path program 1 times [2025-03-03 14:45:54,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:54,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368948197] [2025-03-03 14:45:54,173 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:54,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:54,183 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 88 statements into 1 equivalence classes. [2025-03-03 14:45:54,194 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 88 of 88 statements. [2025-03-03 14:45:54,194 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:54,195 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:54,450 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2025-03-03 14:45:54,450 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:54,450 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [368948197] [2025-03-03 14:45:54,450 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [368948197] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:45:54,450 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1622182151] [2025-03-03 14:45:54,450 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:54,450 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:45:54,450 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:45:54,452 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:45:54,454 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2025-03-03 14:45:54,534 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 88 statements into 1 equivalence classes. [2025-03-03 14:45:54,585 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 88 of 88 statements. [2025-03-03 14:45:54,585 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:54,585 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:54,588 INFO L256 TraceCheckSpWp]: Trace formula consists of 475 conjuncts, 13 conjuncts are in the unsatisfiable core [2025-03-03 14:45:54,592 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:45:54,684 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2025-03-03 14:45:54,684 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-03-03 14:45:54,684 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1622182151] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:54,684 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-03-03 14:45:54,684 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [10] total 15 [2025-03-03 14:45:54,686 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741194072] [2025-03-03 14:45:54,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:54,686 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2025-03-03 14:45:54,686 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:54,686 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-03 14:45:54,687 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=180, Unknown=0, NotChecked=0, Total=210 [2025-03-03 14:45:54,687 INFO L87 Difference]: Start difference. First operand 1092 states and 1475 transitions. Second operand has 8 states, 7 states have (on average 9.142857142857142) internal successors, (64), 7 states have internal predecessors, (64), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-03 14:45:54,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:54,869 INFO L93 Difference]: Finished difference Result 2345 states and 3285 transitions. [2025-03-03 14:45:54,869 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-03 14:45:54,869 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 9.142857142857142) internal successors, (64), 7 states have internal predecessors, (64), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) Word has length 88 [2025-03-03 14:45:54,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:54,880 INFO L225 Difference]: With dead ends: 2345 [2025-03-03 14:45:54,881 INFO L226 Difference]: Without dead ends: 1514 [2025-03-03 14:45:54,884 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 101 GetRequests, 85 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=261, Unknown=0, NotChecked=0, Total=306 [2025-03-03 14:45:54,884 INFO L435 NwaCegarLoop]: 432 mSDtfsCounter, 136 mSDsluCounter, 2395 mSDsCounter, 0 mSdLazyCounter, 124 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 162 SdHoareTripleChecker+Valid, 2827 SdHoareTripleChecker+Invalid, 126 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 124 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:54,884 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [162 Valid, 2827 Invalid, 126 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 124 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:45:54,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1514 states. [2025-03-03 14:45:54,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1514 to 1100. [2025-03-03 14:45:54,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1100 states, 835 states have (on average 1.3520958083832335) internal successors, (1129), 842 states have internal predecessors, (1129), 174 states have call successors, (174), 90 states have call predecessors, (174), 90 states have return successors, (174), 167 states have call predecessors, (174), 174 states have call successors, (174) [2025-03-03 14:45:54,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1100 states to 1100 states and 1477 transitions. [2025-03-03 14:45:54,957 INFO L78 Accepts]: Start accepts. Automaton has 1100 states and 1477 transitions. Word has length 88 [2025-03-03 14:45:54,957 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:54,957 INFO L471 AbstractCegarLoop]: Abstraction has 1100 states and 1477 transitions. [2025-03-03 14:45:54,958 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 9.142857142857142) internal successors, (64), 7 states have internal predecessors, (64), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-03 14:45:54,958 INFO L276 IsEmpty]: Start isEmpty. Operand 1100 states and 1477 transitions. [2025-03-03 14:45:54,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2025-03-03 14:45:54,959 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:54,959 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:54,968 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2025-03-03 14:45:55,159 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable14 [2025-03-03 14:45:55,159 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:55,160 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:55,160 INFO L85 PathProgramCache]: Analyzing trace with hash -2073176967, now seen corresponding path program 1 times [2025-03-03 14:45:55,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:55,160 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694400579] [2025-03-03 14:45:55,160 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:55,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:55,186 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 91 statements into 1 equivalence classes. [2025-03-03 14:45:55,197 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 91 of 91 statements. [2025-03-03 14:45:55,197 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:55,197 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:55,291 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2025-03-03 14:45:55,291 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:55,291 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694400579] [2025-03-03 14:45:55,291 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [694400579] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:55,291 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:55,291 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-03 14:45:55,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1991469054] [2025-03-03 14:45:55,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:55,291 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-03 14:45:55,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:55,292 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-03 14:45:55,292 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:55,292 INFO L87 Difference]: Start difference. First operand 1100 states and 1477 transitions. Second operand has 7 states, 7 states have (on average 9.571428571428571) internal successors, (67), 6 states have internal predecessors, (67), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) [2025-03-03 14:45:55,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:55,458 INFO L93 Difference]: Finished difference Result 1984 states and 2666 transitions. [2025-03-03 14:45:55,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-03 14:45:55,458 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 9.571428571428571) internal successors, (67), 6 states have internal predecessors, (67), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) Word has length 91 [2025-03-03 14:45:55,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:55,464 INFO L225 Difference]: With dead ends: 1984 [2025-03-03 14:45:55,464 INFO L226 Difference]: Without dead ends: 1139 [2025-03-03 14:45:55,466 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:45:55,466 INFO L435 NwaCegarLoop]: 256 mSDtfsCounter, 250 mSDsluCounter, 1211 mSDsCounter, 0 mSdLazyCounter, 75 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 251 SdHoareTripleChecker+Valid, 1467 SdHoareTripleChecker+Invalid, 90 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 75 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:55,466 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [251 Valid, 1467 Invalid, 90 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 75 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:45:55,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1139 states. [2025-03-03 14:45:55,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1139 to 1105. [2025-03-03 14:45:55,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1105 states, 851 states have (on average 1.3443008225616921) internal successors, (1144), 863 states have internal predecessors, (1144), 162 states have call successors, (162), 91 states have call predecessors, (162), 91 states have return successors, (162), 150 states have call predecessors, (162), 162 states have call successors, (162) [2025-03-03 14:45:55,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1105 states to 1105 states and 1468 transitions. [2025-03-03 14:45:55,523 INFO L78 Accepts]: Start accepts. Automaton has 1105 states and 1468 transitions. Word has length 91 [2025-03-03 14:45:55,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:55,523 INFO L471 AbstractCegarLoop]: Abstraction has 1105 states and 1468 transitions. [2025-03-03 14:45:55,523 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 9.571428571428571) internal successors, (67), 6 states have internal predecessors, (67), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) [2025-03-03 14:45:55,523 INFO L276 IsEmpty]: Start isEmpty. Operand 1105 states and 1468 transitions. [2025-03-03 14:45:55,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2025-03-03 14:45:55,524 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:55,524 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:55,524 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2025-03-03 14:45:55,524 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:55,525 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:55,525 INFO L85 PathProgramCache]: Analyzing trace with hash -1749427774, now seen corresponding path program 1 times [2025-03-03 14:45:55,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:55,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2087388456] [2025-03-03 14:45:55,525 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:55,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:55,535 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 93 statements into 1 equivalence classes. [2025-03-03 14:45:55,567 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 93 of 93 statements. [2025-03-03 14:45:55,567 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:55,567 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:55,911 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2025-03-03 14:45:55,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:55,912 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2087388456] [2025-03-03 14:45:55,912 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2087388456] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:55,912 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:55,912 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-03 14:45:55,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1068212255] [2025-03-03 14:45:55,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:55,912 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-03 14:45:55,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:55,913 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-03 14:45:55,913 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:55,913 INFO L87 Difference]: Start difference. First operand 1105 states and 1468 transitions. Second operand has 7 states, 7 states have (on average 9.428571428571429) internal successors, (66), 6 states have internal predecessors, (66), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-03 14:45:56,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:56,111 INFO L93 Difference]: Finished difference Result 1973 states and 2629 transitions. [2025-03-03 14:45:56,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-03 14:45:56,111 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 9.428571428571429) internal successors, (66), 6 states have internal predecessors, (66), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) Word has length 93 [2025-03-03 14:45:56,112 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:56,119 INFO L225 Difference]: With dead ends: 1973 [2025-03-03 14:45:56,120 INFO L226 Difference]: Without dead ends: 1103 [2025-03-03 14:45:56,122 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:45:56,123 INFO L435 NwaCegarLoop]: 285 mSDtfsCounter, 151 mSDsluCounter, 1298 mSDsCounter, 0 mSdLazyCounter, 78 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 153 SdHoareTripleChecker+Valid, 1583 SdHoareTripleChecker+Invalid, 80 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 78 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:56,123 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [153 Valid, 1583 Invalid, 80 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 78 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:45:56,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1103 states. [2025-03-03 14:45:56,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1103 to 995. [2025-03-03 14:45:56,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 995 states, 768 states have (on average 1.3463541666666667) internal successors, (1034), 778 states have internal predecessors, (1034), 145 states have call successors, (145), 81 states have call predecessors, (145), 81 states have return successors, (145), 135 states have call predecessors, (145), 145 states have call successors, (145) [2025-03-03 14:45:56,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 995 states to 995 states and 1324 transitions. [2025-03-03 14:45:56,194 INFO L78 Accepts]: Start accepts. Automaton has 995 states and 1324 transitions. Word has length 93 [2025-03-03 14:45:56,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:56,195 INFO L471 AbstractCegarLoop]: Abstraction has 995 states and 1324 transitions. [2025-03-03 14:45:56,195 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 9.428571428571429) internal successors, (66), 6 states have internal predecessors, (66), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-03 14:45:56,195 INFO L276 IsEmpty]: Start isEmpty. Operand 995 states and 1324 transitions. [2025-03-03 14:45:56,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2025-03-03 14:45:56,197 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:56,197 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:56,197 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2025-03-03 14:45:56,197 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:56,197 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:56,198 INFO L85 PathProgramCache]: Analyzing trace with hash -1745026751, now seen corresponding path program 1 times [2025-03-03 14:45:56,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:56,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785362810] [2025-03-03 14:45:56,198 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:56,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:56,208 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 94 statements into 1 equivalence classes. [2025-03-03 14:45:56,229 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 94 of 94 statements. [2025-03-03 14:45:56,229 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:56,229 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:56,612 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2025-03-03 14:45:56,613 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:56,614 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [785362810] [2025-03-03 14:45:56,614 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [785362810] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:56,614 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:56,614 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-03 14:45:56,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [507304907] [2025-03-03 14:45:56,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:56,614 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-03 14:45:56,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:56,615 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-03 14:45:56,615 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:56,615 INFO L87 Difference]: Start difference. First operand 995 states and 1324 transitions. Second operand has 7 states, 7 states have (on average 10.142857142857142) internal successors, (71), 6 states have internal predecessors, (71), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-03 14:45:56,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:56,999 INFO L93 Difference]: Finished difference Result 1905 states and 2517 transitions. [2025-03-03 14:45:57,000 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-03 14:45:57,000 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 10.142857142857142) internal successors, (71), 6 states have internal predecessors, (71), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) Word has length 94 [2025-03-03 14:45:57,000 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:57,005 INFO L225 Difference]: With dead ends: 1905 [2025-03-03 14:45:57,005 INFO L226 Difference]: Without dead ends: 1065 [2025-03-03 14:45:57,006 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:45:57,006 INFO L435 NwaCegarLoop]: 279 mSDtfsCounter, 512 mSDsluCounter, 952 mSDsCounter, 0 mSdLazyCounter, 177 mSolverCounterSat, 51 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 518 SdHoareTripleChecker+Valid, 1231 SdHoareTripleChecker+Invalid, 228 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 51 IncrementalHoareTripleChecker+Valid, 177 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:57,006 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [518 Valid, 1231 Invalid, 228 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [51 Valid, 177 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-03-03 14:45:57,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1065 states. [2025-03-03 14:45:57,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1065 to 1011. [2025-03-03 14:45:57,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1011 states, 776 states have (on average 1.3234536082474226) internal successors, (1027), 787 states have internal predecessors, (1027), 148 states have call successors, (148), 86 states have call predecessors, (148), 86 states have return successors, (148), 137 states have call predecessors, (148), 148 states have call successors, (148) [2025-03-03 14:45:57,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1011 states to 1011 states and 1323 transitions. [2025-03-03 14:45:57,064 INFO L78 Accepts]: Start accepts. Automaton has 1011 states and 1323 transitions. Word has length 94 [2025-03-03 14:45:57,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:57,065 INFO L471 AbstractCegarLoop]: Abstraction has 1011 states and 1323 transitions. [2025-03-03 14:45:57,065 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 10.142857142857142) internal successors, (71), 6 states have internal predecessors, (71), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-03 14:45:57,065 INFO L276 IsEmpty]: Start isEmpty. Operand 1011 states and 1323 transitions. [2025-03-03 14:45:57,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2025-03-03 14:45:57,066 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:57,066 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:57,066 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2025-03-03 14:45:57,066 INFO L396 AbstractCegarLoop]: === Iteration 19 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:57,066 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:57,066 INFO L85 PathProgramCache]: Analyzing trace with hash 924137639, now seen corresponding path program 1 times [2025-03-03 14:45:57,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:57,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873836642] [2025-03-03 14:45:57,066 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:57,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:57,079 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 95 statements into 1 equivalence classes. [2025-03-03 14:45:57,088 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 95 of 95 statements. [2025-03-03 14:45:57,088 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:57,088 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:57,134 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-03 14:45:57,134 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:57,134 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873836642] [2025-03-03 14:45:57,134 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1873836642] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:57,134 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:57,134 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:57,134 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [197586480] [2025-03-03 14:45:57,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:57,135 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:57,135 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:57,135 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:57,135 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:57,135 INFO L87 Difference]: Start difference. First operand 1011 states and 1323 transitions. Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 4 states have internal predecessors, (71), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:45:57,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:57,289 INFO L93 Difference]: Finished difference Result 2670 states and 3515 transitions. [2025-03-03 14:45:57,289 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-03 14:45:57,290 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 17.75) internal successors, (71), 4 states have internal predecessors, (71), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 95 [2025-03-03 14:45:57,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:57,297 INFO L225 Difference]: With dead ends: 2670 [2025-03-03 14:45:57,297 INFO L226 Difference]: Without dead ends: 1865 [2025-03-03 14:45:57,299 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:57,299 INFO L435 NwaCegarLoop]: 462 mSDtfsCounter, 200 mSDsluCounter, 690 mSDsCounter, 0 mSdLazyCounter, 35 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 200 SdHoareTripleChecker+Valid, 1152 SdHoareTripleChecker+Invalid, 42 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 35 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:57,299 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [200 Valid, 1152 Invalid, 42 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 35 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:57,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1865 states. [2025-03-03 14:45:57,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1865 to 1748. [2025-03-03 14:45:57,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1748 states, 1323 states have (on average 1.3167044595616024) internal successors, (1742), 1342 states have internal predecessors, (1742), 272 states have call successors, (272), 152 states have call predecessors, (272), 152 states have return successors, (272), 253 states have call predecessors, (272), 272 states have call successors, (272) [2025-03-03 14:45:57,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1748 states to 1748 states and 2286 transitions. [2025-03-03 14:45:57,397 INFO L78 Accepts]: Start accepts. Automaton has 1748 states and 2286 transitions. Word has length 95 [2025-03-03 14:45:57,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:57,397 INFO L471 AbstractCegarLoop]: Abstraction has 1748 states and 2286 transitions. [2025-03-03 14:45:57,397 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 17.75) internal successors, (71), 4 states have internal predecessors, (71), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:45:57,398 INFO L276 IsEmpty]: Start isEmpty. Operand 1748 states and 2286 transitions. [2025-03-03 14:45:57,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2025-03-03 14:45:57,398 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:57,398 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:57,399 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2025-03-03 14:45:57,399 INFO L396 AbstractCegarLoop]: === Iteration 20 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:57,399 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:57,399 INFO L85 PathProgramCache]: Analyzing trace with hash 151226506, now seen corresponding path program 1 times [2025-03-03 14:45:57,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:57,399 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1268461434] [2025-03-03 14:45:57,399 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:57,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:57,408 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 97 statements into 1 equivalence classes. [2025-03-03 14:45:57,415 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 97 of 97 statements. [2025-03-03 14:45:57,416 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:57,416 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:57,461 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-03 14:45:57,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:57,462 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1268461434] [2025-03-03 14:45:57,462 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1268461434] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:57,462 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:57,462 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:57,462 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594879934] [2025-03-03 14:45:57,462 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:57,462 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:57,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:57,463 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:57,463 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:57,463 INFO L87 Difference]: Start difference. First operand 1748 states and 2286 transitions. Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 4 states have internal predecessors, (73), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:45:57,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:57,656 INFO L93 Difference]: Finished difference Result 4060 states and 5334 transitions. [2025-03-03 14:45:57,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-03 14:45:57,657 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 18.25) internal successors, (73), 4 states have internal predecessors, (73), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 97 [2025-03-03 14:45:57,657 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:57,668 INFO L225 Difference]: With dead ends: 4060 [2025-03-03 14:45:57,668 INFO L226 Difference]: Without dead ends: 2601 [2025-03-03 14:45:57,672 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:57,672 INFO L435 NwaCegarLoop]: 480 mSDtfsCounter, 201 mSDsluCounter, 706 mSDsCounter, 0 mSdLazyCounter, 40 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 201 SdHoareTripleChecker+Valid, 1186 SdHoareTripleChecker+Invalid, 46 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 40 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:57,672 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [201 Valid, 1186 Invalid, 46 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 40 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:57,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2601 states. [2025-03-03 14:45:57,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2601 to 2482. [2025-03-03 14:45:57,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2482 states, 1867 states have (on average 1.3111944295661488) internal successors, (2448), 1894 states have internal predecessors, (2448), 396 states have call successors, (396), 218 states have call predecessors, (396), 218 states have return successors, (396), 369 states have call predecessors, (396), 396 states have call successors, (396) [2025-03-03 14:45:57,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2482 states to 2482 states and 3240 transitions. [2025-03-03 14:45:57,819 INFO L78 Accepts]: Start accepts. Automaton has 2482 states and 3240 transitions. Word has length 97 [2025-03-03 14:45:57,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:57,819 INFO L471 AbstractCegarLoop]: Abstraction has 2482 states and 3240 transitions. [2025-03-03 14:45:57,820 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 18.25) internal successors, (73), 4 states have internal predecessors, (73), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:45:57,820 INFO L276 IsEmpty]: Start isEmpty. Operand 2482 states and 3240 transitions. [2025-03-03 14:45:57,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2025-03-03 14:45:57,821 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:57,821 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:57,821 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2025-03-03 14:45:57,822 INFO L396 AbstractCegarLoop]: === Iteration 21 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:57,822 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:57,822 INFO L85 PathProgramCache]: Analyzing trace with hash 1978024268, now seen corresponding path program 1 times [2025-03-03 14:45:57,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:57,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120196415] [2025-03-03 14:45:57,822 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:57,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:57,837 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 97 statements into 1 equivalence classes. [2025-03-03 14:45:57,880 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 97 of 97 statements. [2025-03-03 14:45:57,880 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:57,880 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:58,169 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2025-03-03 14:45:58,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:58,169 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2120196415] [2025-03-03 14:45:58,169 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2120196415] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:58,169 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:58,169 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-03 14:45:58,169 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2003426426] [2025-03-03 14:45:58,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:58,169 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-03 14:45:58,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:58,170 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-03 14:45:58,170 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:58,170 INFO L87 Difference]: Start difference. First operand 2482 states and 3240 transitions. Second operand has 7 states, 7 states have (on average 10.571428571428571) internal successors, (74), 6 states have internal predecessors, (74), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 3 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:45:58,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:58,718 INFO L93 Difference]: Finished difference Result 4841 states and 6317 transitions. [2025-03-03 14:45:58,719 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-03 14:45:58,719 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 10.571428571428571) internal successors, (74), 6 states have internal predecessors, (74), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 3 states have call predecessors, (8), 2 states have call successors, (8) Word has length 97 [2025-03-03 14:45:58,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:58,731 INFO L225 Difference]: With dead ends: 4841 [2025-03-03 14:45:58,731 INFO L226 Difference]: Without dead ends: 2739 [2025-03-03 14:45:58,736 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:45:58,737 INFO L435 NwaCegarLoop]: 319 mSDtfsCounter, 415 mSDsluCounter, 1142 mSDsCounter, 0 mSdLazyCounter, 181 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 421 SdHoareTripleChecker+Valid, 1461 SdHoareTripleChecker+Invalid, 183 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 181 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:58,737 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [421 Valid, 1461 Invalid, 183 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 181 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-03-03 14:45:58,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2739 states. [2025-03-03 14:45:58,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2739 to 2493. [2025-03-03 14:45:58,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2493 states, 1867 states have (on average 1.3090519550080342) internal successors, (2444), 1895 states have internal predecessors, (2444), 403 states have call successors, (403), 222 states have call predecessors, (403), 222 states have return successors, (403), 375 states have call predecessors, (403), 403 states have call successors, (403) [2025-03-03 14:45:58,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2493 states to 2493 states and 3250 transitions. [2025-03-03 14:45:58,919 INFO L78 Accepts]: Start accepts. Automaton has 2493 states and 3250 transitions. Word has length 97 [2025-03-03 14:45:58,920 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:58,920 INFO L471 AbstractCegarLoop]: Abstraction has 2493 states and 3250 transitions. [2025-03-03 14:45:58,920 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 10.571428571428571) internal successors, (74), 6 states have internal predecessors, (74), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 3 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:45:58,920 INFO L276 IsEmpty]: Start isEmpty. Operand 2493 states and 3250 transitions. [2025-03-03 14:45:58,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2025-03-03 14:45:58,922 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:58,922 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:58,922 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2025-03-03 14:45:58,922 INFO L396 AbstractCegarLoop]: === Iteration 22 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:58,923 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:58,923 INFO L85 PathProgramCache]: Analyzing trace with hash 1395709453, now seen corresponding path program 1 times [2025-03-03 14:45:58,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:58,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771099356] [2025-03-03 14:45:58,923 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:58,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:58,936 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 99 statements into 1 equivalence classes. [2025-03-03 14:45:58,944 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 99 of 99 statements. [2025-03-03 14:45:58,944 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:58,944 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:58,991 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-03 14:45:58,992 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:58,992 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771099356] [2025-03-03 14:45:58,992 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1771099356] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:58,993 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:58,993 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:58,993 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1570142482] [2025-03-03 14:45:58,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:58,993 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:58,993 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:58,994 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:58,994 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:58,994 INFO L87 Difference]: Start difference. First operand 2493 states and 3250 transitions. Second operand has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:45:59,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:59,276 INFO L93 Difference]: Finished difference Result 6394 states and 8373 transitions. [2025-03-03 14:45:59,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-03 14:45:59,280 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 99 [2025-03-03 14:45:59,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:59,300 INFO L225 Difference]: With dead ends: 6394 [2025-03-03 14:45:59,300 INFO L226 Difference]: Without dead ends: 4330 [2025-03-03 14:45:59,306 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:59,307 INFO L435 NwaCegarLoop]: 469 mSDtfsCounter, 205 mSDsluCounter, 703 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 205 SdHoareTripleChecker+Valid, 1172 SdHoareTripleChecker+Invalid, 35 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:59,308 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [205 Valid, 1172 Invalid, 35 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:59,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4330 states. [2025-03-03 14:45:59,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4330 to 3993. [2025-03-03 14:45:59,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3993 states, 2956 states have (on average 1.297361299052774) internal successors, (3835), 3000 states have internal predecessors, (3835), 672 states have call successors, (672), 364 states have call predecessors, (672), 364 states have return successors, (672), 628 states have call predecessors, (672), 672 states have call successors, (672) [2025-03-03 14:45:59,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3993 states to 3993 states and 5179 transitions. [2025-03-03 14:45:59,613 INFO L78 Accepts]: Start accepts. Automaton has 3993 states and 5179 transitions. Word has length 99 [2025-03-03 14:45:59,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:59,613 INFO L471 AbstractCegarLoop]: Abstraction has 3993 states and 5179 transitions. [2025-03-03 14:45:59,614 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:45:59,614 INFO L276 IsEmpty]: Start isEmpty. Operand 3993 states and 5179 transitions. [2025-03-03 14:45:59,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2025-03-03 14:45:59,616 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:59,616 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:59,616 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2025-03-03 14:45:59,616 INFO L396 AbstractCegarLoop]: === Iteration 23 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:59,617 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:59,617 INFO L85 PathProgramCache]: Analyzing trace with hash -10155904, now seen corresponding path program 1 times [2025-03-03 14:45:59,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:59,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833089462] [2025-03-03 14:45:59,617 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:59,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:59,629 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 100 statements into 1 equivalence classes. [2025-03-03 14:45:59,633 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 100 of 100 statements. [2025-03-03 14:45:59,634 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:59,634 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:59,663 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-03 14:45:59,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:59,664 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833089462] [2025-03-03 14:45:59,664 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [833089462] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:59,664 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:59,664 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-03 14:45:59,664 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1822204719] [2025-03-03 14:45:59,664 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:59,665 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-03-03 14:45:59,665 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:59,665 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-03 14:45:59,665 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-03 14:45:59,665 INFO L87 Difference]: Start difference. First operand 3993 states and 5179 transitions. Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:45:59,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:59,973 INFO L93 Difference]: Finished difference Result 7677 states and 10001 transitions. [2025-03-03 14:45:59,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-03 14:45:59,973 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 100 [2025-03-03 14:45:59,974 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:59,997 INFO L225 Difference]: With dead ends: 7677 [2025-03-03 14:45:59,997 INFO L226 Difference]: Without dead ends: 4026 [2025-03-03 14:46:00,010 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-03 14:46:00,010 INFO L435 NwaCegarLoop]: 259 mSDtfsCounter, 6 mSDsluCounter, 224 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 483 SdHoareTripleChecker+Invalid, 40 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:00,011 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 483 Invalid, 40 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:46:00,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4026 states. [2025-03-03 14:46:00,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4026 to 3999. [2025-03-03 14:46:00,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3999 states, 2962 states have (on average 1.2967589466576637) internal successors, (3841), 3006 states have internal predecessors, (3841), 672 states have call successors, (672), 364 states have call predecessors, (672), 364 states have return successors, (672), 628 states have call predecessors, (672), 672 states have call successors, (672) [2025-03-03 14:46:00,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3999 states to 3999 states and 5185 transitions. [2025-03-03 14:46:00,396 INFO L78 Accepts]: Start accepts. Automaton has 3999 states and 5185 transitions. Word has length 100 [2025-03-03 14:46:00,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:00,397 INFO L471 AbstractCegarLoop]: Abstraction has 3999 states and 5185 transitions. [2025-03-03 14:46:00,398 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:00,398 INFO L276 IsEmpty]: Start isEmpty. Operand 3999 states and 5185 transitions. [2025-03-03 14:46:00,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2025-03-03 14:46:00,400 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:00,400 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:00,400 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2025-03-03 14:46:00,400 INFO L396 AbstractCegarLoop]: === Iteration 24 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:00,400 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:00,400 INFO L85 PathProgramCache]: Analyzing trace with hash -1740310676, now seen corresponding path program 1 times [2025-03-03 14:46:00,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:00,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638015674] [2025-03-03 14:46:00,401 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:00,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:00,411 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 101 statements into 1 equivalence classes. [2025-03-03 14:46:00,421 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 101 of 101 statements. [2025-03-03 14:46:00,421 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:00,421 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:00,493 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-03 14:46:00,493 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:00,493 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1638015674] [2025-03-03 14:46:00,493 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1638015674] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:46:00,493 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:46:00,493 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:46:00,494 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1657345658] [2025-03-03 14:46:00,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:46:00,494 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:46:00,494 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:00,494 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:46:00,494 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:46:00,495 INFO L87 Difference]: Start difference. First operand 3999 states and 5185 transitions. Second operand has 4 states, 4 states have (on average 19.25) internal successors, (77), 4 states have internal predecessors, (77), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:00,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:00,730 INFO L93 Difference]: Finished difference Result 7642 states and 9928 transitions. [2025-03-03 14:46:00,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:46:00,731 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 19.25) internal successors, (77), 4 states have internal predecessors, (77), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 101 [2025-03-03 14:46:00,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:00,756 INFO L225 Difference]: With dead ends: 7642 [2025-03-03 14:46:00,756 INFO L226 Difference]: Without dead ends: 3715 [2025-03-03 14:46:00,765 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:46:00,766 INFO L435 NwaCegarLoop]: 261 mSDtfsCounter, 79 mSDsluCounter, 472 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 79 SdHoareTripleChecker+Valid, 733 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:00,766 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [79 Valid, 733 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:46:00,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3715 states. [2025-03-03 14:46:00,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3715 to 3652. [2025-03-03 14:46:00,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3652 states, 2698 states have (on average 1.305040770941438) internal successors, (3521), 2732 states have internal predecessors, (3521), 620 states have call successors, (620), 333 states have call predecessors, (620), 333 states have return successors, (620), 586 states have call predecessors, (620), 620 states have call successors, (620) [2025-03-03 14:46:00,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3652 states to 3652 states and 4761 transitions. [2025-03-03 14:46:00,973 INFO L78 Accepts]: Start accepts. Automaton has 3652 states and 4761 transitions. Word has length 101 [2025-03-03 14:46:00,973 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:00,973 INFO L471 AbstractCegarLoop]: Abstraction has 3652 states and 4761 transitions. [2025-03-03 14:46:00,973 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 19.25) internal successors, (77), 4 states have internal predecessors, (77), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:00,974 INFO L276 IsEmpty]: Start isEmpty. Operand 3652 states and 4761 transitions. [2025-03-03 14:46:00,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2025-03-03 14:46:00,975 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:00,975 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:00,976 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2025-03-03 14:46:00,976 INFO L396 AbstractCegarLoop]: === Iteration 25 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:00,976 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:00,976 INFO L85 PathProgramCache]: Analyzing trace with hash -695191203, now seen corresponding path program 1 times [2025-03-03 14:46:00,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:00,976 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1233453069] [2025-03-03 14:46:00,977 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:00,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:00,987 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 102 statements into 1 equivalence classes. [2025-03-03 14:46:00,998 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 102 of 102 statements. [2025-03-03 14:46:00,998 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:00,998 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:01,113 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-03 14:46:01,113 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:01,113 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1233453069] [2025-03-03 14:46:01,113 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1233453069] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:46:01,113 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:46:01,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:46:01,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080102807] [2025-03-03 14:46:01,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:46:01,114 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:46:01,114 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:01,114 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:46:01,115 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:46:01,115 INFO L87 Difference]: Start difference. First operand 3652 states and 4761 transitions. Second operand has 4 states, 4 states have (on average 19.5) internal successors, (78), 4 states have internal predecessors, (78), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:01,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:01,298 INFO L93 Difference]: Finished difference Result 7113 states and 9291 transitions. [2025-03-03 14:46:01,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:46:01,299 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 19.5) internal successors, (78), 4 states have internal predecessors, (78), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 102 [2025-03-03 14:46:01,299 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:01,315 INFO L225 Difference]: With dead ends: 7113 [2025-03-03 14:46:01,315 INFO L226 Difference]: Without dead ends: 3576 [2025-03-03 14:46:01,324 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:46:01,324 INFO L435 NwaCegarLoop]: 266 mSDtfsCounter, 60 mSDsluCounter, 477 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 60 SdHoareTripleChecker+Valid, 743 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:01,325 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [60 Valid, 743 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:46:01,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3576 states. [2025-03-03 14:46:01,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3576 to 2749. [2025-03-03 14:46:01,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2749 states, 2029 states have (on average 1.2971907343518976) internal successors, (2632), 2048 states have internal predecessors, (2632), 469 states have call successors, (469), 250 states have call predecessors, (469), 250 states have return successors, (469), 450 states have call predecessors, (469), 469 states have call successors, (469) [2025-03-03 14:46:01,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2749 states to 2749 states and 3570 transitions. [2025-03-03 14:46:01,529 INFO L78 Accepts]: Start accepts. Automaton has 2749 states and 3570 transitions. Word has length 102 [2025-03-03 14:46:01,529 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:01,529 INFO L471 AbstractCegarLoop]: Abstraction has 2749 states and 3570 transitions. [2025-03-03 14:46:01,529 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 19.5) internal successors, (78), 4 states have internal predecessors, (78), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:01,529 INFO L276 IsEmpty]: Start isEmpty. Operand 2749 states and 3570 transitions. [2025-03-03 14:46:01,534 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2025-03-03 14:46:01,534 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:01,534 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:01,535 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24 [2025-03-03 14:46:01,535 INFO L396 AbstractCegarLoop]: === Iteration 26 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:01,535 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:01,535 INFO L85 PathProgramCache]: Analyzing trace with hash -1273702806, now seen corresponding path program 1 times [2025-03-03 14:46:01,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:01,536 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995325836] [2025-03-03 14:46:01,536 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:01,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:01,554 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-03 14:46:01,583 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-03 14:46:01,584 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:01,584 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:02,055 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 26 proven. 4 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2025-03-03 14:46:02,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:02,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1995325836] [2025-03-03 14:46:02,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1995325836] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:02,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [709323167] [2025-03-03 14:46:02,056 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:02,056 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:02,056 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:02,059 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:02,060 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2025-03-03 14:46:02,167 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-03 14:46:02,246 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-03 14:46:02,246 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:02,246 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:02,250 INFO L256 TraceCheckSpWp]: Trace formula consists of 731 conjuncts, 18 conjuncts are in the unsatisfiable core [2025-03-03 14:46:02,255 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:02,292 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 44 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2025-03-03 14:46:02,292 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-03-03 14:46:02,292 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [709323167] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:46:02,292 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-03-03 14:46:02,292 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [8] total 11 [2025-03-03 14:46:02,292 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [522742590] [2025-03-03 14:46:02,292 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:46:02,293 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-03-03 14:46:02,293 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:02,293 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-03 14:46:02,293 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:46:02,293 INFO L87 Difference]: Start difference. First operand 2749 states and 3570 transitions. Second operand has 5 states, 4 states have (on average 24.25) internal successors, (97), 5 states have internal predecessors, (97), 3 states have call successors, (14), 2 states have call predecessors, (14), 3 states have return successors, (13), 2 states have call predecessors, (13), 3 states have call successors, (13) [2025-03-03 14:46:02,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:02,539 INFO L93 Difference]: Finished difference Result 5176 states and 6759 transitions. [2025-03-03 14:46:02,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-03 14:46:02,539 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 24.25) internal successors, (97), 5 states have internal predecessors, (97), 3 states have call successors, (14), 2 states have call predecessors, (14), 3 states have return successors, (13), 2 states have call predecessors, (13), 3 states have call successors, (13) Word has length 152 [2025-03-03 14:46:02,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:02,551 INFO L225 Difference]: With dead ends: 5176 [2025-03-03 14:46:02,551 INFO L226 Difference]: Without dead ends: 2582 [2025-03-03 14:46:02,558 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 152 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:46:02,558 INFO L435 NwaCegarLoop]: 255 mSDtfsCounter, 0 mSDsluCounter, 753 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1008 SdHoareTripleChecker+Invalid, 20 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:02,559 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1008 Invalid, 20 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 20 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:46:02,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2582 states. [2025-03-03 14:46:02,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2582 to 2566. [2025-03-03 14:46:02,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2566 states, 1891 states have (on average 1.2934955050237968) internal successors, (2446), 1908 states have internal predecessors, (2446), 440 states have call successors, (440), 234 states have call predecessors, (440), 234 states have return successors, (440), 423 states have call predecessors, (440), 440 states have call successors, (440) [2025-03-03 14:46:02,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2566 states to 2566 states and 3326 transitions. [2025-03-03 14:46:02,821 INFO L78 Accepts]: Start accepts. Automaton has 2566 states and 3326 transitions. Word has length 152 [2025-03-03 14:46:02,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:02,822 INFO L471 AbstractCegarLoop]: Abstraction has 2566 states and 3326 transitions. [2025-03-03 14:46:02,822 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 24.25) internal successors, (97), 5 states have internal predecessors, (97), 3 states have call successors, (14), 2 states have call predecessors, (14), 3 states have return successors, (13), 2 states have call predecessors, (13), 3 states have call successors, (13) [2025-03-03 14:46:02,822 INFO L276 IsEmpty]: Start isEmpty. Operand 2566 states and 3326 transitions. [2025-03-03 14:46:02,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2025-03-03 14:46:02,826 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:02,826 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:02,834 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2025-03-03 14:46:03,028 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable25 [2025-03-03 14:46:03,028 INFO L396 AbstractCegarLoop]: === Iteration 27 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:03,029 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:03,029 INFO L85 PathProgramCache]: Analyzing trace with hash -75496420, now seen corresponding path program 1 times [2025-03-03 14:46:03,029 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:03,029 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870829552] [2025-03-03 14:46:03,029 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:03,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:03,046 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 154 statements into 1 equivalence classes. [2025-03-03 14:46:03,090 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 154 of 154 statements. [2025-03-03 14:46:03,090 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:03,090 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:03,650 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 12 proven. 17 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-03 14:46:03,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:03,650 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870829552] [2025-03-03 14:46:03,650 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1870829552] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:03,651 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1778289693] [2025-03-03 14:46:03,651 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:03,651 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:03,651 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:03,653 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:03,669 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2025-03-03 14:46:03,772 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 154 statements into 1 equivalence classes. [2025-03-03 14:46:03,846 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 154 of 154 statements. [2025-03-03 14:46:03,846 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:03,846 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:03,850 INFO L256 TraceCheckSpWp]: Trace formula consists of 765 conjuncts, 27 conjuncts are in the unsatisfiable core [2025-03-03 14:46:03,854 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:04,133 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 32 proven. 44 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-03 14:46:04,135 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-03 14:46:04,412 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 12 proven. 17 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-03 14:46:04,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1778289693] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-03 14:46:04,412 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-03 14:46:04,412 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 11, 8] total 23 [2025-03-03 14:46:04,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1924792981] [2025-03-03 14:46:04,413 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-03 14:46:04,413 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2025-03-03 14:46:04,414 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:04,415 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2025-03-03 14:46:04,415 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=422, Unknown=0, NotChecked=0, Total=506 [2025-03-03 14:46:04,415 INFO L87 Difference]: Start difference. First operand 2566 states and 3326 transitions. Second operand has 23 states, 23 states have (on average 10.173913043478262) internal successors, (234), 20 states have internal predecessors, (234), 8 states have call successors, (40), 4 states have call predecessors, (40), 8 states have return successors, (39), 11 states have call predecessors, (39), 8 states have call successors, (39) [2025-03-03 14:46:05,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:05,848 INFO L93 Difference]: Finished difference Result 7246 states and 9427 transitions. [2025-03-03 14:46:05,849 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2025-03-03 14:46:05,849 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 10.173913043478262) internal successors, (234), 20 states have internal predecessors, (234), 8 states have call successors, (40), 4 states have call predecessors, (40), 8 states have return successors, (39), 11 states have call predecessors, (39), 8 states have call successors, (39) Word has length 154 [2025-03-03 14:46:05,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:05,868 INFO L225 Difference]: With dead ends: 7246 [2025-03-03 14:46:05,868 INFO L226 Difference]: Without dead ends: 4916 [2025-03-03 14:46:05,876 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 340 GetRequests, 298 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 378 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=360, Invalid=1532, Unknown=0, NotChecked=0, Total=1892 [2025-03-03 14:46:05,877 INFO L435 NwaCegarLoop]: 408 mSDtfsCounter, 1808 mSDsluCounter, 2973 mSDsCounter, 0 mSdLazyCounter, 756 mSolverCounterSat, 694 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1813 SdHoareTripleChecker+Valid, 3381 SdHoareTripleChecker+Invalid, 1450 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 694 IncrementalHoareTripleChecker+Valid, 756 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:05,877 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1813 Valid, 3381 Invalid, 1450 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [694 Valid, 756 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2025-03-03 14:46:05,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4916 states. [2025-03-03 14:46:06,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4916 to 4394. [2025-03-03 14:46:06,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4394 states, 3238 states have (on average 1.2970969734403952) internal successors, (4200), 3266 states have internal predecessors, (4200), 751 states have call successors, (751), 404 states have call predecessors, (751), 404 states have return successors, (751), 723 states have call predecessors, (751), 751 states have call successors, (751) [2025-03-03 14:46:06,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4394 states to 4394 states and 5702 transitions. [2025-03-03 14:46:06,191 INFO L78 Accepts]: Start accepts. Automaton has 4394 states and 5702 transitions. Word has length 154 [2025-03-03 14:46:06,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:06,191 INFO L471 AbstractCegarLoop]: Abstraction has 4394 states and 5702 transitions. [2025-03-03 14:46:06,192 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 10.173913043478262) internal successors, (234), 20 states have internal predecessors, (234), 8 states have call successors, (40), 4 states have call predecessors, (40), 8 states have return successors, (39), 11 states have call predecessors, (39), 8 states have call successors, (39) [2025-03-03 14:46:06,192 INFO L276 IsEmpty]: Start isEmpty. Operand 4394 states and 5702 transitions. [2025-03-03 14:46:06,198 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2025-03-03 14:46:06,198 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:06,199 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:06,206 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2025-03-03 14:46:06,403 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable26,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:06,403 INFO L396 AbstractCegarLoop]: === Iteration 28 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:06,404 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:06,404 INFO L85 PathProgramCache]: Analyzing trace with hash -2034971932, now seen corresponding path program 1 times [2025-03-03 14:46:06,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:06,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483813546] [2025-03-03 14:46:06,404 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:06,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:06,419 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 155 statements into 1 equivalence classes. [2025-03-03 14:46:06,451 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 155 of 155 statements. [2025-03-03 14:46:06,451 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:06,451 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:06,959 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 22 proven. 5 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-03 14:46:06,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:06,959 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483813546] [2025-03-03 14:46:06,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1483813546] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:06,959 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1899276879] [2025-03-03 14:46:06,959 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:06,959 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:06,959 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:06,961 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:06,963 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2025-03-03 14:46:07,069 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 155 statements into 1 equivalence classes. [2025-03-03 14:46:07,138 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 155 of 155 statements. [2025-03-03 14:46:07,138 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:07,138 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:07,147 INFO L256 TraceCheckSpWp]: Trace formula consists of 766 conjuncts, 41 conjuncts are in the unsatisfiable core [2025-03-03 14:46:07,152 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:07,721 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 50 proven. 28 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2025-03-03 14:46:07,721 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-03 14:46:08,454 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 15 proven. 12 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-03 14:46:08,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1899276879] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-03 14:46:08,455 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-03 14:46:08,455 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 13, 11] total 29 [2025-03-03 14:46:08,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089264164] [2025-03-03 14:46:08,455 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-03 14:46:08,455 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 29 states [2025-03-03 14:46:08,455 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:08,456 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2025-03-03 14:46:08,456 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=128, Invalid=684, Unknown=0, NotChecked=0, Total=812 [2025-03-03 14:46:08,456 INFO L87 Difference]: Start difference. First operand 4394 states and 5702 transitions. Second operand has 29 states, 29 states have (on average 8.724137931034482) internal successors, (253), 29 states have internal predecessors, (253), 11 states have call successors, (38), 6 states have call predecessors, (38), 7 states have return successors, (37), 11 states have call predecessors, (37), 11 states have call successors, (37) [2025-03-03 14:46:13,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:13,731 INFO L93 Difference]: Finished difference Result 10344 states and 13438 transitions. [2025-03-03 14:46:13,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2025-03-03 14:46:13,732 INFO L78 Accepts]: Start accepts. Automaton has has 29 states, 29 states have (on average 8.724137931034482) internal successors, (253), 29 states have internal predecessors, (253), 11 states have call successors, (38), 6 states have call predecessors, (38), 7 states have return successors, (37), 11 states have call predecessors, (37), 11 states have call successors, (37) Word has length 155 [2025-03-03 14:46:13,732 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:13,757 INFO L225 Difference]: With dead ends: 10344 [2025-03-03 14:46:13,757 INFO L226 Difference]: Without dead ends: 6197 [2025-03-03 14:46:13,767 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 404 GetRequests, 311 SyntacticMatches, 0 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2645 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=1664, Invalid=7266, Unknown=0, NotChecked=0, Total=8930 [2025-03-03 14:46:13,768 INFO L435 NwaCegarLoop]: 342 mSDtfsCounter, 2792 mSDsluCounter, 3800 mSDsCounter, 0 mSdLazyCounter, 2127 mSolverCounterSat, 946 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2792 SdHoareTripleChecker+Valid, 4142 SdHoareTripleChecker+Invalid, 3073 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 946 IncrementalHoareTripleChecker+Valid, 2127 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.5s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:13,768 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2792 Valid, 4142 Invalid, 3073 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [946 Valid, 2127 Invalid, 0 Unknown, 0 Unchecked, 1.5s Time] [2025-03-03 14:46:13,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6197 states. [2025-03-03 14:46:14,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6197 to 5915. [2025-03-03 14:46:14,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5915 states, 4368 states have (on average 1.291437728937729) internal successors, (5641), 4406 states have internal predecessors, (5641), 995 states have call successors, (995), 551 states have call predecessors, (995), 551 states have return successors, (995), 957 states have call predecessors, (995), 995 states have call successors, (995) [2025-03-03 14:46:14,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5915 states to 5915 states and 7631 transitions. [2025-03-03 14:46:14,340 INFO L78 Accepts]: Start accepts. Automaton has 5915 states and 7631 transitions. Word has length 155 [2025-03-03 14:46:14,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:14,340 INFO L471 AbstractCegarLoop]: Abstraction has 5915 states and 7631 transitions. [2025-03-03 14:46:14,340 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 29 states, 29 states have (on average 8.724137931034482) internal successors, (253), 29 states have internal predecessors, (253), 11 states have call successors, (38), 6 states have call predecessors, (38), 7 states have return successors, (37), 11 states have call predecessors, (37), 11 states have call successors, (37) [2025-03-03 14:46:14,340 INFO L276 IsEmpty]: Start isEmpty. Operand 5915 states and 7631 transitions. [2025-03-03 14:46:14,348 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 158 [2025-03-03 14:46:14,348 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:14,348 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:14,364 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2025-03-03 14:46:14,551 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable27 [2025-03-03 14:46:14,552 INFO L396 AbstractCegarLoop]: === Iteration 29 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:14,552 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:14,552 INFO L85 PathProgramCache]: Analyzing trace with hash -1121278789, now seen corresponding path program 1 times [2025-03-03 14:46:14,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:14,552 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1122950534] [2025-03-03 14:46:14,552 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:14,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:14,565 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 157 statements into 1 equivalence classes. [2025-03-03 14:46:14,579 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 157 of 157 statements. [2025-03-03 14:46:14,579 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:14,579 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:14,700 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2025-03-03 14:46:14,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:14,701 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1122950534] [2025-03-03 14:46:14,701 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1122950534] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:46:14,701 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:46:14,701 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-03 14:46:14,701 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [194963102] [2025-03-03 14:46:14,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:46:14,701 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-03 14:46:14,701 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:14,702 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-03 14:46:14,702 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:46:14,702 INFO L87 Difference]: Start difference. First operand 5915 states and 7631 transitions. Second operand has 7 states, 7 states have (on average 13.0) internal successors, (91), 6 states have internal predecessors, (91), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 3 states have call predecessors, (13), 2 states have call successors, (13) [2025-03-03 14:46:15,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:15,866 INFO L93 Difference]: Finished difference Result 16915 states and 21905 transitions. [2025-03-03 14:46:15,866 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-03 14:46:15,866 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 13.0) internal successors, (91), 6 states have internal predecessors, (91), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 3 states have call predecessors, (13), 2 states have call successors, (13) Word has length 157 [2025-03-03 14:46:15,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:15,907 INFO L225 Difference]: With dead ends: 16915 [2025-03-03 14:46:15,907 INFO L226 Difference]: Without dead ends: 11511 [2025-03-03 14:46:15,920 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:46:15,920 INFO L435 NwaCegarLoop]: 478 mSDtfsCounter, 220 mSDsluCounter, 2059 mSDsCounter, 0 mSdLazyCounter, 137 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 225 SdHoareTripleChecker+Valid, 2537 SdHoareTripleChecker+Invalid, 137 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 137 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:15,920 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [225 Valid, 2537 Invalid, 137 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 137 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:46:15,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11511 states. [2025-03-03 14:46:16,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11511 to 8399. [2025-03-03 14:46:16,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8399 states, 6156 states have (on average 1.2910981156595192) internal successors, (7948), 6212 states have internal predecessors, (7948), 1459 states have call successors, (1459), 783 states have call predecessors, (1459), 783 states have return successors, (1459), 1403 states have call predecessors, (1459), 1459 states have call successors, (1459) [2025-03-03 14:46:16,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8399 states to 8399 states and 10866 transitions. [2025-03-03 14:46:16,782 INFO L78 Accepts]: Start accepts. Automaton has 8399 states and 10866 transitions. Word has length 157 [2025-03-03 14:46:16,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:16,784 INFO L471 AbstractCegarLoop]: Abstraction has 8399 states and 10866 transitions. [2025-03-03 14:46:16,784 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 13.0) internal successors, (91), 6 states have internal predecessors, (91), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 3 states have call predecessors, (13), 2 states have call successors, (13) [2025-03-03 14:46:16,784 INFO L276 IsEmpty]: Start isEmpty. Operand 8399 states and 10866 transitions. [2025-03-03 14:46:16,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 158 [2025-03-03 14:46:16,796 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:16,796 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:16,796 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable28 [2025-03-03 14:46:16,796 INFO L396 AbstractCegarLoop]: === Iteration 30 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:16,797 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:16,797 INFO L85 PathProgramCache]: Analyzing trace with hash -995622477, now seen corresponding path program 1 times [2025-03-03 14:46:16,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:16,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131030786] [2025-03-03 14:46:16,797 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:16,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:16,811 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 157 statements into 1 equivalence classes. [2025-03-03 14:46:16,841 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 157 of 157 statements. [2025-03-03 14:46:16,841 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:16,841 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:17,254 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 27 proven. 4 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2025-03-03 14:46:17,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:17,254 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131030786] [2025-03-03 14:46:17,255 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [131030786] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:17,255 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1253149927] [2025-03-03 14:46:17,255 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:17,255 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:17,255 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:17,257 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:17,258 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2025-03-03 14:46:17,359 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 157 statements into 1 equivalence classes. [2025-03-03 14:46:17,427 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 157 of 157 statements. [2025-03-03 14:46:17,427 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:17,427 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:17,431 INFO L256 TraceCheckSpWp]: Trace formula consists of 783 conjuncts, 11 conjuncts are in the unsatisfiable core [2025-03-03 14:46:17,434 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:17,517 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 47 proven. 4 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2025-03-03 14:46:17,517 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-03 14:46:17,589 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 24 proven. 2 refuted. 0 times theorem prover too weak. 59 trivial. 0 not checked. [2025-03-03 14:46:17,589 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1253149927] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-03 14:46:17,590 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-03 14:46:17,590 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 14 [2025-03-03 14:46:17,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572367792] [2025-03-03 14:46:17,590 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-03 14:46:17,590 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2025-03-03 14:46:17,590 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:17,591 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2025-03-03 14:46:17,591 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=153, Unknown=0, NotChecked=0, Total=182 [2025-03-03 14:46:17,591 INFO L87 Difference]: Start difference. First operand 8399 states and 10866 transitions. Second operand has 14 states, 13 states have (on average 13.692307692307692) internal successors, (178), 11 states have internal predecessors, (178), 5 states have call successors, (32), 4 states have call predecessors, (32), 7 states have return successors, (32), 7 states have call predecessors, (32), 5 states have call successors, (32) [2025-03-03 14:46:19,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:19,445 INFO L93 Difference]: Finished difference Result 22380 states and 28831 transitions. [2025-03-03 14:46:19,446 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2025-03-03 14:46:19,446 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 13 states have (on average 13.692307692307692) internal successors, (178), 11 states have internal predecessors, (178), 5 states have call successors, (32), 4 states have call predecessors, (32), 7 states have return successors, (32), 7 states have call predecessors, (32), 5 states have call successors, (32) Word has length 157 [2025-03-03 14:46:19,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:19,501 INFO L225 Difference]: With dead ends: 22380 [2025-03-03 14:46:19,501 INFO L226 Difference]: Without dead ends: 14179 [2025-03-03 14:46:19,519 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 313 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 102 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=92, Invalid=610, Unknown=0, NotChecked=0, Total=702 [2025-03-03 14:46:19,521 INFO L435 NwaCegarLoop]: 265 mSDtfsCounter, 211 mSDsluCounter, 2311 mSDsCounter, 0 mSdLazyCounter, 378 mSolverCounterSat, 27 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 215 SdHoareTripleChecker+Valid, 2576 SdHoareTripleChecker+Invalid, 405 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 27 IncrementalHoareTripleChecker+Valid, 378 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:19,521 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [215 Valid, 2576 Invalid, 405 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [27 Valid, 378 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-03-03 14:46:19,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14179 states. [2025-03-03 14:46:20,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14179 to 9469. [2025-03-03 14:46:20,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9469 states, 6927 states have (on average 1.2900245416486213) internal successors, (8936), 6994 states have internal predecessors, (8936), 1644 states have call successors, (1644), 897 states have call predecessors, (1644), 897 states have return successors, (1644), 1577 states have call predecessors, (1644), 1644 states have call successors, (1644) [2025-03-03 14:46:20,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9469 states to 9469 states and 12224 transitions. [2025-03-03 14:46:20,573 INFO L78 Accepts]: Start accepts. Automaton has 9469 states and 12224 transitions. Word has length 157 [2025-03-03 14:46:20,574 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:20,574 INFO L471 AbstractCegarLoop]: Abstraction has 9469 states and 12224 transitions. [2025-03-03 14:46:20,574 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 13 states have (on average 13.692307692307692) internal successors, (178), 11 states have internal predecessors, (178), 5 states have call successors, (32), 4 states have call predecessors, (32), 7 states have return successors, (32), 7 states have call predecessors, (32), 5 states have call successors, (32) [2025-03-03 14:46:20,574 INFO L276 IsEmpty]: Start isEmpty. Operand 9469 states and 12224 transitions. [2025-03-03 14:46:20,583 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2025-03-03 14:46:20,583 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:20,583 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:20,591 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2025-03-03 14:46:20,783 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:20,784 INFO L396 AbstractCegarLoop]: === Iteration 31 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:20,784 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:20,785 INFO L85 PathProgramCache]: Analyzing trace with hash -769381661, now seen corresponding path program 1 times [2025-03-03 14:46:20,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:20,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325539724] [2025-03-03 14:46:20,785 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:20,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:20,799 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 173 statements into 1 equivalence classes. [2025-03-03 14:46:20,835 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 173 of 173 statements. [2025-03-03 14:46:20,837 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:20,837 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:21,268 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 27 proven. 8 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2025-03-03 14:46:21,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:21,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325539724] [2025-03-03 14:46:21,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1325539724] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:21,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [503824086] [2025-03-03 14:46:21,269 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:21,269 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:21,269 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:21,271 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:21,272 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2025-03-03 14:46:21,374 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 173 statements into 1 equivalence classes. [2025-03-03 14:46:21,444 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 173 of 173 statements. [2025-03-03 14:46:21,444 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:21,444 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:21,448 INFO L256 TraceCheckSpWp]: Trace formula consists of 820 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-03-03 14:46:21,451 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:21,739 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 69 proven. 17 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2025-03-03 14:46:21,740 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-03 14:46:23,053 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 20 proven. 9 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2025-03-03 14:46:23,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [503824086] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-03 14:46:23,053 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-03 14:46:23,053 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 11, 10] total 26 [2025-03-03 14:46:23,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1849289341] [2025-03-03 14:46:23,054 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-03 14:46:23,054 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2025-03-03 14:46:23,054 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:23,055 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2025-03-03 14:46:23,055 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=573, Unknown=0, NotChecked=0, Total=650 [2025-03-03 14:46:23,055 INFO L87 Difference]: Start difference. First operand 9469 states and 12224 transitions. Second operand has 26 states, 25 states have (on average 10.52) internal successors, (263), 24 states have internal predecessors, (263), 8 states have call successors, (42), 5 states have call predecessors, (42), 7 states have return successors, (41), 9 states have call predecessors, (41), 8 states have call successors, (41) [2025-03-03 14:46:26,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:26,950 INFO L93 Difference]: Finished difference Result 25984 states and 33601 transitions. [2025-03-03 14:46:26,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2025-03-03 14:46:26,951 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 25 states have (on average 10.52) internal successors, (263), 24 states have internal predecessors, (263), 8 states have call successors, (42), 5 states have call predecessors, (42), 7 states have return successors, (41), 9 states have call predecessors, (41), 8 states have call successors, (41) Word has length 173 [2025-03-03 14:46:26,951 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:27,005 INFO L225 Difference]: With dead ends: 25984 [2025-03-03 14:46:27,005 INFO L226 Difference]: Without dead ends: 16723 [2025-03-03 14:46:27,020 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 394 GetRequests, 342 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 609 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=383, Invalid=2479, Unknown=0, NotChecked=0, Total=2862 [2025-03-03 14:46:27,021 INFO L435 NwaCegarLoop]: 688 mSDtfsCounter, 865 mSDsluCounter, 8178 mSDsCounter, 0 mSdLazyCounter, 3853 mSolverCounterSat, 231 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 869 SdHoareTripleChecker+Valid, 8866 SdHoareTripleChecker+Invalid, 4084 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 231 IncrementalHoareTripleChecker+Valid, 3853 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.5s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:27,021 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [869 Valid, 8866 Invalid, 4084 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [231 Valid, 3853 Invalid, 0 Unknown, 0 Unchecked, 1.5s Time] [2025-03-03 14:46:27,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16723 states. [2025-03-03 14:46:28,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16723 to 13479. [2025-03-03 14:46:28,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13479 states, 9819 states have (on average 1.2925959873714228) internal successors, (12692), 9922 states have internal predecessors, (12692), 2376 states have call successors, (2376), 1283 states have call predecessors, (2376), 1283 states have return successors, (2376), 2273 states have call predecessors, (2376), 2376 states have call successors, (2376) [2025-03-03 14:46:28,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13479 states to 13479 states and 17444 transitions. [2025-03-03 14:46:28,740 INFO L78 Accepts]: Start accepts. Automaton has 13479 states and 17444 transitions. Word has length 173 [2025-03-03 14:46:28,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:28,741 INFO L471 AbstractCegarLoop]: Abstraction has 13479 states and 17444 transitions. [2025-03-03 14:46:28,741 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 25 states have (on average 10.52) internal successors, (263), 24 states have internal predecessors, (263), 8 states have call successors, (42), 5 states have call predecessors, (42), 7 states have return successors, (41), 9 states have call predecessors, (41), 8 states have call successors, (41) [2025-03-03 14:46:28,741 INFO L276 IsEmpty]: Start isEmpty. Operand 13479 states and 17444 transitions. [2025-03-03 14:46:28,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2025-03-03 14:46:28,751 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:28,751 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:28,760 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2025-03-03 14:46:28,951 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:28,952 INFO L396 AbstractCegarLoop]: === Iteration 32 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:28,953 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:28,953 INFO L85 PathProgramCache]: Analyzing trace with hash 295344362, now seen corresponding path program 1 times [2025-03-03 14:46:28,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:28,953 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817028560] [2025-03-03 14:46:28,953 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:28,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:28,967 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 181 statements into 1 equivalence classes. [2025-03-03 14:46:28,990 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 181 of 181 statements. [2025-03-03 14:46:28,990 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:28,990 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:29,552 INFO L134 CoverageAnalysis]: Checked inductivity of 124 backedges. 23 proven. 9 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2025-03-03 14:46:29,552 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:29,552 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817028560] [2025-03-03 14:46:29,552 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [817028560] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:29,552 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [40253313] [2025-03-03 14:46:29,552 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:29,552 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:29,553 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:29,555 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:29,556 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2025-03-03 14:46:29,676 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 181 statements into 1 equivalence classes. [2025-03-03 14:46:29,750 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 181 of 181 statements. [2025-03-03 14:46:29,751 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:29,751 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:29,754 INFO L256 TraceCheckSpWp]: Trace formula consists of 822 conjuncts, 48 conjuncts are in the unsatisfiable core [2025-03-03 14:46:29,758 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:30,279 INFO L134 CoverageAnalysis]: Checked inductivity of 124 backedges. 76 proven. 17 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2025-03-03 14:46:30,280 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-03 14:46:31,080 INFO L134 CoverageAnalysis]: Checked inductivity of 124 backedges. 16 proven. 16 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2025-03-03 14:46:31,081 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [40253313] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-03 14:46:31,081 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-03 14:46:31,081 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 11, 12] total 28 [2025-03-03 14:46:31,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [132007722] [2025-03-03 14:46:31,081 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-03 14:46:31,081 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 28 states [2025-03-03 14:46:31,081 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:31,083 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2025-03-03 14:46:31,083 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=106, Invalid=650, Unknown=0, NotChecked=0, Total=756 [2025-03-03 14:46:31,083 INFO L87 Difference]: Start difference. First operand 13479 states and 17444 transitions. Second operand has 28 states, 28 states have (on average 9.75) internal successors, (273), 28 states have internal predecessors, (273), 10 states have call successors, (47), 5 states have call predecessors, (47), 6 states have return successors, (46), 10 states have call predecessors, (46), 10 states have call successors, (46) [2025-03-03 14:46:35,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:35,015 INFO L93 Difference]: Finished difference Result 27846 states and 36112 transitions. [2025-03-03 14:46:35,015 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2025-03-03 14:46:35,015 INFO L78 Accepts]: Start accepts. Automaton has has 28 states, 28 states have (on average 9.75) internal successors, (273), 28 states have internal predecessors, (273), 10 states have call successors, (47), 5 states have call predecessors, (47), 6 states have return successors, (46), 10 states have call predecessors, (46), 10 states have call successors, (46) Word has length 181 [2025-03-03 14:46:35,016 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:35,066 INFO L225 Difference]: With dead ends: 27846 [2025-03-03 14:46:35,066 INFO L226 Difference]: Without dead ends: 14760 [2025-03-03 14:46:35,085 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 412 GetRequests, 356 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 829 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=488, Invalid=2818, Unknown=0, NotChecked=0, Total=3306 [2025-03-03 14:46:35,086 INFO L435 NwaCegarLoop]: 406 mSDtfsCounter, 1380 mSDsluCounter, 4220 mSDsCounter, 0 mSdLazyCounter, 2077 mSolverCounterSat, 470 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1380 SdHoareTripleChecker+Valid, 4626 SdHoareTripleChecker+Invalid, 2547 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 470 IncrementalHoareTripleChecker+Valid, 2077 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:35,086 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1380 Valid, 4626 Invalid, 2547 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [470 Valid, 2077 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2025-03-03 14:46:35,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14760 states. [2025-03-03 14:46:37,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14760 to 14377. [2025-03-03 14:46:37,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14377 states, 10472 states have (on average 1.2916348357524827) internal successors, (13526), 10583 states have internal predecessors, (13526), 2536 states have call successors, (2536), 1368 states have call predecessors, (2536), 1368 states have return successors, (2536), 2425 states have call predecessors, (2536), 2536 states have call successors, (2536) [2025-03-03 14:46:37,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14377 states to 14377 states and 18598 transitions. [2025-03-03 14:46:37,190 INFO L78 Accepts]: Start accepts. Automaton has 14377 states and 18598 transitions. Word has length 181 [2025-03-03 14:46:37,190 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:37,190 INFO L471 AbstractCegarLoop]: Abstraction has 14377 states and 18598 transitions. [2025-03-03 14:46:37,191 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 28 states, 28 states have (on average 9.75) internal successors, (273), 28 states have internal predecessors, (273), 10 states have call successors, (47), 5 states have call predecessors, (47), 6 states have return successors, (46), 10 states have call predecessors, (46), 10 states have call successors, (46) [2025-03-03 14:46:37,191 INFO L276 IsEmpty]: Start isEmpty. Operand 14377 states and 18598 transitions. [2025-03-03 14:46:37,200 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2025-03-03 14:46:37,200 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:37,200 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:37,211 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2025-03-03 14:46:37,400 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:37,401 INFO L396 AbstractCegarLoop]: === Iteration 33 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:37,401 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:37,401 INFO L85 PathProgramCache]: Analyzing trace with hash 1119555439, now seen corresponding path program 1 times [2025-03-03 14:46:37,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:37,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [907459053] [2025-03-03 14:46:37,401 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:37,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:37,421 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 181 statements into 1 equivalence classes. [2025-03-03 14:46:37,451 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 181 of 181 statements. [2025-03-03 14:46:37,451 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:37,451 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:37,914 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 23 proven. 6 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2025-03-03 14:46:37,914 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:37,914 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [907459053] [2025-03-03 14:46:37,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [907459053] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:37,914 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1794422878] [2025-03-03 14:46:37,914 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:37,914 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:37,914 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:37,916 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:37,917 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2025-03-03 14:46:38,021 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 181 statements into 1 equivalence classes. [2025-03-03 14:46:38,086 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 181 of 181 statements. [2025-03-03 14:46:38,086 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:38,086 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:38,088 INFO L256 TraceCheckSpWp]: Trace formula consists of 838 conjuncts, 30 conjuncts are in the unsatisfiable core [2025-03-03 14:46:38,092 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:38,436 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 80 proven. 10 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2025-03-03 14:46:38,436 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-03 14:46:38,820 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 23 proven. 6 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2025-03-03 14:46:38,820 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1794422878] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-03 14:46:38,820 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-03 14:46:38,820 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 12, 9] total 23 [2025-03-03 14:46:38,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203435210] [2025-03-03 14:46:38,820 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-03 14:46:38,821 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2025-03-03 14:46:38,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:38,822 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2025-03-03 14:46:38,822 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=401, Unknown=0, NotChecked=0, Total=506 [2025-03-03 14:46:38,822 INFO L87 Difference]: Start difference. First operand 14377 states and 18598 transitions. Second operand has 23 states, 23 states have (on average 10.869565217391305) internal successors, (250), 23 states have internal predecessors, (250), 9 states have call successors, (37), 5 states have call predecessors, (37), 6 states have return successors, (36), 9 states have call predecessors, (36), 9 states have call successors, (36) [2025-03-03 14:46:41,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:41,993 INFO L93 Difference]: Finished difference Result 34747 states and 45063 transitions. [2025-03-03 14:46:41,993 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2025-03-03 14:46:41,994 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 10.869565217391305) internal successors, (250), 23 states have internal predecessors, (250), 9 states have call successors, (37), 5 states have call predecessors, (37), 6 states have return successors, (36), 9 states have call predecessors, (36), 9 states have call successors, (36) Word has length 181 [2025-03-03 14:46:41,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:42,062 INFO L225 Difference]: With dead ends: 34747 [2025-03-03 14:46:42,063 INFO L226 Difference]: Without dead ends: 20815 [2025-03-03 14:46:42,092 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 395 GetRequests, 353 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 474 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=368, Invalid=1524, Unknown=0, NotChecked=0, Total=1892 [2025-03-03 14:46:42,092 INFO L435 NwaCegarLoop]: 347 mSDtfsCounter, 1727 mSDsluCounter, 2034 mSDsCounter, 0 mSdLazyCounter, 1371 mSolverCounterSat, 496 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1727 SdHoareTripleChecker+Valid, 2381 SdHoareTripleChecker+Invalid, 1867 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 496 IncrementalHoareTripleChecker+Valid, 1371 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:42,092 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1727 Valid, 2381 Invalid, 1867 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [496 Valid, 1371 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2025-03-03 14:46:42,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20815 states. [2025-03-03 14:46:44,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20815 to 19411. [2025-03-03 14:46:44,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19411 states, 14116 states have (on average 1.2947010484556531) internal successors, (18276), 14270 states have internal predecessors, (18276), 3440 states have call successors, (3440), 1854 states have call predecessors, (3440), 1854 states have return successors, (3440), 3286 states have call predecessors, (3440), 3440 states have call successors, (3440) [2025-03-03 14:46:44,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19411 states to 19411 states and 25156 transitions. [2025-03-03 14:46:44,578 INFO L78 Accepts]: Start accepts. Automaton has 19411 states and 25156 transitions. Word has length 181 [2025-03-03 14:46:44,578 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:44,578 INFO L471 AbstractCegarLoop]: Abstraction has 19411 states and 25156 transitions. [2025-03-03 14:46:44,579 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 10.869565217391305) internal successors, (250), 23 states have internal predecessors, (250), 9 states have call successors, (37), 5 states have call predecessors, (37), 6 states have return successors, (36), 9 states have call predecessors, (36), 9 states have call successors, (36) [2025-03-03 14:46:44,579 INFO L276 IsEmpty]: Start isEmpty. Operand 19411 states and 25156 transitions. [2025-03-03 14:46:44,587 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2025-03-03 14:46:44,587 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:44,587 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:44,595 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2025-03-03 14:46:44,787 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable32 [2025-03-03 14:46:44,787 INFO L396 AbstractCegarLoop]: === Iteration 34 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:44,788 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:44,788 INFO L85 PathProgramCache]: Analyzing trace with hash 792262701, now seen corresponding path program 1 times [2025-03-03 14:46:44,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:44,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959515063] [2025-03-03 14:46:44,788 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:44,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:44,798 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 181 statements into 1 equivalence classes. [2025-03-03 14:46:44,895 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 181 of 181 statements. [2025-03-03 14:46:44,897 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:44,897 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:45,708 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 25 proven. 6 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2025-03-03 14:46:45,709 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:45,709 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1959515063] [2025-03-03 14:46:45,709 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1959515063] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:45,709 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1406287374] [2025-03-03 14:46:45,709 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:45,709 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:45,709 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:45,711 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:45,712 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2025-03-03 14:46:45,825 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 181 statements into 1 equivalence classes. [2025-03-03 14:46:45,899 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 181 of 181 statements. [2025-03-03 14:46:45,899 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:45,899 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:45,902 INFO L256 TraceCheckSpWp]: Trace formula consists of 837 conjuncts, 40 conjuncts are in the unsatisfiable core [2025-03-03 14:46:45,905 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:46,279 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 78 proven. 14 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2025-03-03 14:46:46,279 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-03 14:46:46,927 INFO L134 CoverageAnalysis]: Checked inductivity of 123 backedges. 25 proven. 6 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2025-03-03 14:46:46,927 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1406287374] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-03 14:46:46,927 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-03 14:46:46,927 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 13, 9] total 25 [2025-03-03 14:46:46,928 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852803950] [2025-03-03 14:46:46,928 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-03 14:46:46,928 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 25 states [2025-03-03 14:46:46,928 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:46,929 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2025-03-03 14:46:46,929 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=499, Unknown=0, NotChecked=0, Total=600 [2025-03-03 14:46:46,929 INFO L87 Difference]: Start difference. First operand 19411 states and 25156 transitions. Second operand has 25 states, 25 states have (on average 9.8) internal successors, (245), 25 states have internal predecessors, (245), 8 states have call successors, (36), 5 states have call predecessors, (36), 6 states have return successors, (35), 8 states have call predecessors, (35), 8 states have call successors, (35) [2025-03-03 14:46:50,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:50,436 INFO L93 Difference]: Finished difference Result 34456 states and 44709 transitions. [2025-03-03 14:46:50,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2025-03-03 14:46:50,437 INFO L78 Accepts]: Start accepts. Automaton has has 25 states, 25 states have (on average 9.8) internal successors, (245), 25 states have internal predecessors, (245), 8 states have call successors, (36), 5 states have call predecessors, (36), 6 states have return successors, (35), 8 states have call predecessors, (35), 8 states have call successors, (35) Word has length 181 [2025-03-03 14:46:50,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:50,506 INFO L225 Difference]: With dead ends: 34456 [2025-03-03 14:46:50,506 INFO L226 Difference]: Without dead ends: 19459 [2025-03-03 14:46:50,534 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 390 GetRequests, 352 SyntacticMatches, 1 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 299 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=285, Invalid=1197, Unknown=0, NotChecked=0, Total=1482 [2025-03-03 14:46:50,534 INFO L435 NwaCegarLoop]: 439 mSDtfsCounter, 1340 mSDsluCounter, 2436 mSDsCounter, 0 mSdLazyCounter, 1389 mSolverCounterSat, 452 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1340 SdHoareTripleChecker+Valid, 2875 SdHoareTripleChecker+Invalid, 1841 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 452 IncrementalHoareTripleChecker+Valid, 1389 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:50,534 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1340 Valid, 2875 Invalid, 1841 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [452 Valid, 1389 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2025-03-03 14:46:50,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19459 states. [2025-03-03 14:46:53,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19459 to 19393. [2025-03-03 14:46:53,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19393 states, 14098 states have (on average 1.294367995460349) internal successors, (18248), 14252 states have internal predecessors, (18248), 3440 states have call successors, (3440), 1854 states have call predecessors, (3440), 1854 states have return successors, (3440), 3286 states have call predecessors, (3440), 3440 states have call successors, (3440) [2025-03-03 14:46:53,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19393 states to 19393 states and 25128 transitions. [2025-03-03 14:46:53,213 INFO L78 Accepts]: Start accepts. Automaton has 19393 states and 25128 transitions. Word has length 181 [2025-03-03 14:46:53,213 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:53,213 INFO L471 AbstractCegarLoop]: Abstraction has 19393 states and 25128 transitions. [2025-03-03 14:46:53,213 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 25 states, 25 states have (on average 9.8) internal successors, (245), 25 states have internal predecessors, (245), 8 states have call successors, (36), 5 states have call predecessors, (36), 6 states have return successors, (35), 8 states have call predecessors, (35), 8 states have call successors, (35) [2025-03-03 14:46:53,213 INFO L276 IsEmpty]: Start isEmpty. Operand 19393 states and 25128 transitions. [2025-03-03 14:46:53,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2025-03-03 14:46:53,221 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:53,221 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:53,229 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2025-03-03 14:46:53,422 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable33,10 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:53,422 INFO L396 AbstractCegarLoop]: === Iteration 35 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:53,422 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:53,422 INFO L85 PathProgramCache]: Analyzing trace with hash 932782177, now seen corresponding path program 1 times [2025-03-03 14:46:53,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:53,423 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733678712] [2025-03-03 14:46:53,423 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:53,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:53,434 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-03-03 14:46:53,490 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-03-03 14:46:53,491 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:53,491 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-03 14:46:53,491 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-03 14:46:53,499 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-03-03 14:46:53,590 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-03-03 14:46:53,590 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:53,590 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-03 14:46:53,651 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-03 14:46:53,651 INFO L340 BasicCegarLoop]: Counterexample is feasible [2025-03-03 14:46:53,652 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location assertErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2025-03-03 14:46:53,653 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable34 [2025-03-03 14:46:53,655 INFO L422 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:53,800 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2025-03-03 14:46:53,802 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.03 02:46:53 BoogieIcfgContainer [2025-03-03 14:46:53,803 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2025-03-03 14:46:53,804 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-03 14:46:53,804 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-03 14:46:53,804 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-03 14:46:53,805 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 03.03 02:45:49" (3/4) ... [2025-03-03 14:46:53,805 INFO L140 WitnessPrinter]: Generating witness for reachability counterexample [2025-03-03 14:46:53,933 INFO L127 tionWitnessGenerator]: Generated YAML witness of length 144. [2025-03-03 14:46:54,006 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-03 14:46:54,007 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.yml [2025-03-03 14:46:54,007 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-03 14:46:54,007 INFO L158 Benchmark]: Toolchain (without parser) took 65445.64ms. Allocated memory was 142.6MB in the beginning and 4.3GB in the end (delta: 4.1GB). Free memory was 111.4MB in the beginning and 2.9GB in the end (delta: -2.8GB). Peak memory consumption was 1.3GB. Max. memory is 16.1GB. [2025-03-03 14:46:54,008 INFO L158 Benchmark]: CDTParser took 0.25ms. Allocated memory is still 201.3MB. Free memory is still 123.9MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-03 14:46:54,008 INFO L158 Benchmark]: CACSL2BoogieTranslator took 315.74ms. Allocated memory is still 142.6MB. Free memory was 110.9MB in the beginning and 93.2MB in the end (delta: 17.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-03 14:46:54,008 INFO L158 Benchmark]: Boogie Procedure Inliner took 37.25ms. Allocated memory is still 142.6MB. Free memory was 93.2MB in the beginning and 89.7MB in the end (delta: 3.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-03 14:46:54,010 INFO L158 Benchmark]: Boogie Preprocessor took 41.30ms. Allocated memory is still 142.6MB. Free memory was 89.7MB in the beginning and 86.3MB in the end (delta: 3.5MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-03 14:46:54,010 INFO L158 Benchmark]: IcfgBuilder took 614.16ms. Allocated memory is still 142.6MB. Free memory was 86.3MB in the beginning and 44.9MB in the end (delta: 41.4MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2025-03-03 14:46:54,010 INFO L158 Benchmark]: TraceAbstraction took 64227.84ms. Allocated memory was 142.6MB in the beginning and 4.3GB in the end (delta: 4.1GB). Free memory was 44.4MB in the beginning and 3.0GB in the end (delta: -2.9GB). Peak memory consumption was 1.2GB. Max. memory is 16.1GB. [2025-03-03 14:46:54,010 INFO L158 Benchmark]: Witness Printer took 203.19ms. Allocated memory is still 4.3GB. Free memory was 3.0GB in the beginning and 2.9GB in the end (delta: 41.9MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2025-03-03 14:46:54,011 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25ms. Allocated memory is still 201.3MB. Free memory is still 123.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 315.74ms. Allocated memory is still 142.6MB. Free memory was 110.9MB in the beginning and 93.2MB in the end (delta: 17.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 37.25ms. Allocated memory is still 142.6MB. Free memory was 93.2MB in the beginning and 89.7MB in the end (delta: 3.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 41.30ms. Allocated memory is still 142.6MB. Free memory was 89.7MB in the beginning and 86.3MB in the end (delta: 3.5MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 614.16ms. Allocated memory is still 142.6MB. Free memory was 86.3MB in the beginning and 44.9MB in the end (delta: 41.4MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * TraceAbstraction took 64227.84ms. Allocated memory was 142.6MB in the beginning and 4.3GB in the end (delta: 4.1GB). Free memory was 44.4MB in the beginning and 3.0GB in the end (delta: -2.9GB). Peak memory consumption was 1.2GB. Max. memory is 16.1GB. * Witness Printer took 203.19ms. Allocated memory is still 4.3GB. Free memory was 3.0GB in the beginning and 2.9GB in the end (delta: 41.9MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 611]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L24] msg_t nomsg = (msg_t )-1; [L25] port_t cs1 ; [L26] int8_t cs1_old ; [L27] int8_t cs1_new ; [L28] port_t cs2 ; [L29] int8_t cs2_old ; [L30] int8_t cs2_new ; [L31] port_t s1s2 ; [L32] int8_t s1s2_old ; [L33] int8_t s1s2_new ; [L34] port_t s1s1 ; [L35] int8_t s1s1_old ; [L36] int8_t s1s1_new ; [L37] port_t s2s1 ; [L38] int8_t s2s1_old ; [L39] int8_t s2s1_new ; [L40] port_t s2s2 ; [L41] int8_t s2s2_old ; [L42] int8_t s2s2_new ; [L43] port_t s1p ; [L44] int8_t s1p_old ; [L45] int8_t s1p_new ; [L46] port_t s2p ; [L47] int8_t s2p_old ; [L48] int8_t s2p_new ; [L51] _Bool side1Failed ; [L52] _Bool side2Failed ; [L53] msg_t side1_written ; [L54] msg_t side2_written ; [L60] static _Bool side1Failed_History_0 ; [L61] static _Bool side1Failed_History_1 ; [L62] static _Bool side1Failed_History_2 ; [L63] static _Bool side2Failed_History_0 ; [L64] static _Bool side2Failed_History_1 ; [L65] static _Bool side2Failed_History_2 ; [L66] static int8_t active_side_History_0 ; [L67] static int8_t active_side_History_1 ; [L68] static int8_t active_side_History_2 ; [L69] static msg_t manual_selection_History_0 ; [L70] static msg_t manual_selection_History_1 ; [L71] static msg_t manual_selection_History_2 ; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L534] int c1 ; [L535] int i2 ; [L538] c1 = 0 [L539] side1Failed = __VERIFIER_nondet_bool() [L540] side2Failed = __VERIFIER_nondet_bool() [L541] side1_written = __VERIFIER_nondet_char() [L542] side2_written = __VERIFIER_nondet_char() [L543] side1Failed_History_0 = __VERIFIER_nondet_bool() [L544] side1Failed_History_1 = __VERIFIER_nondet_bool() [L545] side1Failed_History_2 = __VERIFIER_nondet_bool() [L546] side2Failed_History_0 = __VERIFIER_nondet_bool() [L547] side2Failed_History_1 = __VERIFIER_nondet_bool() [L548] side2Failed_History_2 = __VERIFIER_nondet_bool() [L549] active_side_History_0 = __VERIFIER_nondet_char() [L550] active_side_History_1 = __VERIFIER_nondet_char() [L551] active_side_History_2 = __VERIFIER_nondet_char() [L552] manual_selection_History_0 = __VERIFIER_nondet_char() [L553] manual_selection_History_1 = __VERIFIER_nondet_char() [L554] manual_selection_History_2 = __VERIFIER_nondet_char() [L555] CALL, EXPR init() [L197] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L200] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L203] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L206] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L209] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L212] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L215] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L218] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L221] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L224] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L227] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L230] COND FALSE !((int )manual_selection_History_2 != 0) [L233] return (1); VAL [\result=1, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L555] RET, EXPR init() [L555] i2 = init() [L556] CALL assume_abort_if_not(i2) VAL [\old(cond)=1, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L58] COND FALSE !(!cond) VAL [\old(cond)=1, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L556] RET assume_abort_if_not(i2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, i2=1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L557] cs1_old = nomsg [L558] cs1_new = nomsg [L559] cs2_old = nomsg [L560] cs2_new = nomsg [L561] s1s2_old = nomsg [L562] s1s2_new = nomsg [L563] s1s1_old = nomsg [L564] s1s1_new = nomsg [L565] s2s1_old = nomsg [L566] s2s1_new = nomsg [L567] s2s2_old = nomsg [L568] s2s2_new = nomsg [L569] s1p_old = nomsg [L570] s1p_new = nomsg [L571] s2p_old = nomsg [L572] s2p_new = nomsg [L573] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, i2=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L574] COND TRUE i2 < 10 [L576] CALL Console_task_each_pals_period() [L251] msg_t manual_selection ; [L252] char tmp ; [L255] tmp = __VERIFIER_nondet_char() [L256] manual_selection = tmp [L257] CALL write_manual_selection_history(manual_selection) [L167] manual_selection_History_2 = manual_selection_History_1 [L168] manual_selection_History_1 = manual_selection_History_0 [L169] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L257] RET write_manual_selection_history(manual_selection) [L258] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L259] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L260] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L576] RET Console_task_each_pals_period() [L577] CALL Side1_activestandby_task_each_pals_period() [L266] int8_t side1 ; [L267] int8_t side2 ; [L268] msg_t manual_selection ; [L269] int8_t next_state ; [L272] side1 = nomsg [L273] side2 = nomsg [L274] manual_selection = (msg_t )0 [L275] side1Failed = __VERIFIER_nondet_bool() [L276] CALL write_side1_failed_history(side1Failed) [L77] side1Failed_History_2 = side1Failed_History_1 [L78] side1Failed_History_1 = side1Failed_History_0 [L79] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L276] RET write_side1_failed_history(side1Failed) [L277] COND TRUE \read(side1Failed) [L278] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L279] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L280] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L281] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L577] RET Side1_activestandby_task_each_pals_period() [L578] CALL Side2_activestandby_task_each_pals_period() [L323] int8_t side1 ; [L324] int8_t side2 ; [L325] msg_t manual_selection ; [L326] int8_t next_state ; [L329] side1 = nomsg [L330] side2 = nomsg [L331] manual_selection = (msg_t )0 [L332] side2Failed = __VERIFIER_nondet_bool() [L333] CALL write_side2_failed_history(side2Failed) [L107] side2Failed_History_2 = side2Failed_History_1 [L108] side2Failed_History_1 = side2Failed_History_0 [L109] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L333] RET write_side2_failed_history(side2Failed) [L334] COND FALSE !(\read(side2Failed)) [L341] side1 = s1s2_old [L342] s1s2_old = nomsg [L343] side2 = s2s2_old [L344] s2s2_old = nomsg [L345] manual_selection = cs2_old [L346] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L347] COND TRUE (int )side1 == (int )side2 [L348] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, next_state=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L371] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L372] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L373] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L374] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L578] RET Side2_activestandby_task_each_pals_period() [L579] CALL Pendulum_prism_task_each_pals_period() [L380] int8_t active_side ; [L381] int8_t tmp ; [L382] int8_t side1 ; [L383] int8_t side2 ; VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [\old(index)=0, \result=-2, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] RET, EXPR read_active_side_history((unsigned char)0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] tmp = read_active_side_history((unsigned char)0) [L387] active_side = tmp [L388] side1 = nomsg [L389] side2 = nomsg [L390] side1 = s1p_old [L391] s1p_old = nomsg [L392] side2 = s2p_old [L393] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L394] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L397] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L400] COND FALSE !((int )side1 == 0) [L407] active_side = (int8_t )0 VAL [active_side=0, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L409] CALL write_active_side_history(active_side) [L137] active_side_History_2 = active_side_History_1 [L138] active_side_History_1 = active_side_History_0 [L139] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L409] RET write_active_side_history(active_side) [L579] RET Pendulum_prism_task_each_pals_period() [L580] cs1_old = cs1_new [L581] cs1_new = nomsg [L582] cs2_old = cs2_new [L583] cs2_new = nomsg [L584] s1s2_old = s1s2_new [L585] s1s2_new = nomsg [L586] s1s1_old = s1s1_new [L587] s1s1_new = nomsg [L588] s2s1_old = s2s1_new [L589] s2s1_new = nomsg [L590] s2s2_old = s2s2_new [L591] s2s2_new = nomsg [L592] s1p_old = s1p_new [L593] s1p_new = nomsg [L594] s2p_old = s2p_new [L595] s2p_new = nomsg [L596] CALL, EXPR check() [L415] int tmp ; [L416] msg_t tmp___0 ; [L417] _Bool tmp___1 ; [L418] _Bool tmp___2 ; [L419] _Bool tmp___3 ; [L420] _Bool tmp___4 ; [L421] int8_t tmp___5 ; [L422] _Bool tmp___6 ; [L423] _Bool tmp___7 ; [L424] _Bool tmp___8 ; [L425] int8_t tmp___9 ; [L426] _Bool tmp___10 ; [L427] _Bool tmp___11 ; [L428] _Bool tmp___12 ; [L429] msg_t tmp___13 ; [L430] _Bool tmp___14 ; [L431] _Bool tmp___15 ; [L432] _Bool tmp___16 ; [L433] _Bool tmp___17 ; [L434] int8_t tmp___18 ; [L435] int8_t tmp___19 ; [L436] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L439] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L442] COND TRUE ! side2Failed [L443] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L447] CALL assume_abort_if_not((_Bool )tmp) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L58] COND FALSE !(!cond) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L447] RET assume_abort_if_not((_Bool )tmp) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L448] CALL, EXPR read_manual_selection_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L178] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L181] COND TRUE (int )index == 1 [L182] return (manual_selection_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L448] RET, EXPR read_manual_selection_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L448] tmp___0 = read_manual_selection_history((unsigned char)1) [L449] COND TRUE ! tmp___0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L450] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L450] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L450] tmp___1 = read_side1_failed_history((unsigned char)1) [L451] COND TRUE ! tmp___1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L452] CALL, EXPR read_side1_failed_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND TRUE (int )index == 0 [L89] return (side1Failed_History_0); VAL [\old(index)=0, \result=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L452] RET, EXPR read_side1_failed_history((unsigned char)0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L452] tmp___2 = read_side1_failed_history((unsigned char)0) [L453] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L478] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L478] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L478] tmp___7 = read_side1_failed_history((unsigned char)1) [L479] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L494] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L494] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L494] tmp___11 = read_side1_failed_history((unsigned char)1) [L495] COND TRUE ! tmp___11 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L496] CALL, EXPR read_side2_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L118] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L121] COND TRUE (int )index == 1 [L122] return (side2Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L496] RET, EXPR read_side2_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L496] tmp___12 = read_side2_failed_history((unsigned char)1) [L497] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L510] CALL, EXPR read_active_side_history((unsigned char)2) VAL [\old(index)=2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L148] COND FALSE !((int )index == 0) VAL [\old(index)=2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=2, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L151] COND FALSE !((int )index == 1) VAL [\old(index)=2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, index=2, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L154] COND TRUE (int )index == 2 [L155] return (active_side_History_2); VAL [\old(index)=2, \result=-2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L510] RET, EXPR read_active_side_history((unsigned char)2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L510] tmp___20 = read_active_side_history((unsigned char)2) [L511] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L529] return (1); VAL [\result=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L596] RET, EXPR check() [L596] c1 = check() [L597] CALL assert(c1) VAL [\old(arg)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L609] COND FALSE !(! arg) VAL [\old(arg)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L597] RET assert(c1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, c1=1, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, i2=0, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L598] i2 ++ VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, c1=1, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, i2=1, manual_selection_History_0=-1, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L574] COND TRUE i2 < 10 [L576] CALL Console_task_each_pals_period() [L251] msg_t manual_selection ; [L252] char tmp ; [L255] tmp = __VERIFIER_nondet_char() [L256] manual_selection = tmp [L257] CALL write_manual_selection_history(manual_selection) [L167] manual_selection_History_2 = manual_selection_History_1 [L168] manual_selection_History_1 = manual_selection_History_0 [L169] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L257] RET write_manual_selection_history(manual_selection) [L258] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L259] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L260] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L576] RET Console_task_each_pals_period() [L577] CALL Side1_activestandby_task_each_pals_period() [L266] int8_t side1 ; [L267] int8_t side2 ; [L268] msg_t manual_selection ; [L269] int8_t next_state ; [L272] side1 = nomsg [L273] side2 = nomsg [L274] manual_selection = (msg_t )0 [L275] side1Failed = __VERIFIER_nondet_bool() [L276] CALL write_side1_failed_history(side1Failed) [L77] side1Failed_History_2 = side1Failed_History_1 [L78] side1Failed_History_1 = side1Failed_History_0 [L79] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L276] RET write_side1_failed_history(side1Failed) [L277] COND FALSE !(\read(side1Failed)) [L284] side1 = s1s1_old [L285] s1s1_old = nomsg [L286] side2 = s2s1_old [L287] s2s1_old = nomsg [L288] manual_selection = cs1_old [L289] cs1_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L290] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L293] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L294] COND TRUE (int )side2 != (int )nomsg [L295] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, next_state=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L314] s1s1_new = next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new [L315] s1s2_new = next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new [L316] s1p_new = next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new [L317] side1_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L577] RET Side1_activestandby_task_each_pals_period() [L578] CALL Side2_activestandby_task_each_pals_period() [L323] int8_t side1 ; [L324] int8_t side2 ; [L325] msg_t manual_selection ; [L326] int8_t next_state ; [L329] side1 = nomsg [L330] side2 = nomsg [L331] manual_selection = (msg_t )0 [L332] side2Failed = __VERIFIER_nondet_bool() [L333] CALL write_side2_failed_history(side2Failed) [L107] side2Failed_History_2 = side2Failed_History_1 [L108] side2Failed_History_1 = side2Failed_History_0 [L109] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L333] RET write_side2_failed_history(side2Failed) [L334] COND TRUE \read(side2Failed) [L335] s2s1_new = nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new [L336] s2s2_new = nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new [L337] s2p_new = nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new [L338] side2_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L578] RET Side2_activestandby_task_each_pals_period() [L579] CALL Pendulum_prism_task_each_pals_period() [L380] int8_t active_side ; [L381] int8_t tmp ; [L382] int8_t side1 ; [L383] int8_t side2 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L386] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [\old(index)=0, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L386] RET, EXPR read_active_side_history((unsigned char)0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L386] tmp = read_active_side_history((unsigned char)0) [L387] active_side = tmp [L388] side1 = nomsg [L389] side2 = nomsg [L390] side1 = s1p_old [L391] s1p_old = nomsg [L392] side2 = s2p_old [L393] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L394] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L397] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L400] COND FALSE !((int )side1 == 0) [L407] active_side = (int8_t )0 VAL [active_side=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L409] CALL write_active_side_history(active_side) [L137] active_side_History_2 = active_side_History_1 [L138] active_side_History_1 = active_side_History_0 [L139] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=-1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L409] RET write_active_side_history(active_side) [L579] RET Pendulum_prism_task_each_pals_period() [L580] cs1_old = cs1_new [L581] cs1_new = nomsg [L582] cs2_old = cs2_new [L583] cs2_new = nomsg [L584] s1s2_old = s1s2_new [L585] s1s2_new = nomsg [L586] s1s1_old = s1s1_new [L587] s1s1_new = nomsg [L588] s2s1_old = s2s1_new [L589] s2s1_new = nomsg [L590] s2s2_old = s2s2_new [L591] s2s2_new = nomsg [L592] s1p_old = s1p_new [L593] s1p_new = nomsg [L594] s2p_old = s2p_new [L595] s2p_new = nomsg [L596] CALL, EXPR check() [L415] int tmp ; [L416] msg_t tmp___0 ; [L417] _Bool tmp___1 ; [L418] _Bool tmp___2 ; [L419] _Bool tmp___3 ; [L420] _Bool tmp___4 ; [L421] int8_t tmp___5 ; [L422] _Bool tmp___6 ; [L423] _Bool tmp___7 ; [L424] _Bool tmp___8 ; [L425] int8_t tmp___9 ; [L426] _Bool tmp___10 ; [L427] _Bool tmp___11 ; [L428] _Bool tmp___12 ; [L429] msg_t tmp___13 ; [L430] _Bool tmp___14 ; [L431] _Bool tmp___15 ; [L432] _Bool tmp___16 ; [L433] _Bool tmp___17 ; [L434] int8_t tmp___18 ; [L435] int8_t tmp___19 ; [L436] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L439] COND TRUE ! side1Failed [L440] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L447] CALL assume_abort_if_not((_Bool )tmp) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L58] COND FALSE !(!cond) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L447] RET assume_abort_if_not((_Bool )tmp) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L448] CALL, EXPR read_manual_selection_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L178] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, index=1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L181] COND TRUE (int )index == 1 [L182] return (manual_selection_History_1); VAL [\old(index)=1, \result=-1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L448] RET, EXPR read_manual_selection_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L448] tmp___0 = read_manual_selection_history((unsigned char)1) [L449] COND FALSE !(! tmp___0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L478] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, index=1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L478] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L478] tmp___7 = read_side1_failed_history((unsigned char)1) [L479] COND TRUE \read(tmp___7) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L480] CALL, EXPR read_side2_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L118] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, index=1, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L121] COND TRUE (int )index == 1 [L122] return (side2Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L480] RET, EXPR read_side2_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L480] tmp___8 = read_side2_failed_history((unsigned char)1) [L481] COND TRUE ! tmp___8 VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L482] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [\old(index)=0, \result=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L482] RET, EXPR read_active_side_history((unsigned char)0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L482] tmp___5 = read_active_side_history((unsigned char)0) [L483] COND TRUE ! ((int )tmp___5 == 2) [L484] return (0); VAL [\result=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L596] RET, EXPR check() [L596] c1 = check() [L597] CALL assert(c1) VAL [\old(arg)=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L609] COND TRUE ! arg VAL [\old(arg)=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L611] reach_error() VAL [\old(arg)=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=-1, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 8 procedures, 178 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 64.0s, OverallIterations: 35, TraceHistogramMax: 5, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.1s, AutomataDifference: 29.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 14143 SdHoareTripleChecker+Valid, 7.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 14053 mSDsluCounter, 57076 SdHoareTripleChecker+Invalid, 6.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 46104 mSDsCounter, 3477 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 13406 IncrementalHoareTripleChecker+Invalid, 16883 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 3477 mSolverCounterUnsat, 10972 mSDtfsCounter, 13406 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 3115 GetRequests, 2635 SyntacticMatches, 1 SemanticMatches, 479 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5398 ImplicationChecksByTransitivity, 8.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=19411occurred in iteration=33, InterpolantAutomatonStates: 376, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 14.2s AutomataMinimizationTime, 34 MinimizatonAttempts, 16520 StatesRemovedByMinimization, 26 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.4s SsaConstructionTime, 1.5s SatisfiabilityAnalysisTime, 14.8s InterpolantComputationTime, 4999 NumberOfCodeBlocks, 4999 NumberOfCodeBlocksAsserted, 44 NumberOfCheckSat, 5949 ConstructedInterpolants, 0 QuantifiedInterpolants, 20792 SizeOfPredicates, 26 NumberOfNonLiveVariables, 6837 ConjunctsInSsa, 254 ConjunctsInUnsatCore, 50 InterpolantComputations, 27 PerfectInterpolantSequences, 2385/2649 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2025-03-03 14:46:54,041 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE