./Ultimate.py --spec ../sv-benchmarks/c/properties/unreach-call.prp --file ../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerReach.xml -i ../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ac8e60fb32c268c01bf0cc1d1cd76454411c67e3ab15d16b4eca5e74b982e97f --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-03 14:45:48,361 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-03 14:45:48,419 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Reach-32bit-Automizer_Default.epf [2025-03-03 14:45:48,426 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-03 14:45:48,428 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-03 14:45:48,449 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-03 14:45:48,450 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-03 14:45:48,450 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-03 14:45:48,450 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-03 14:45:48,451 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-03 14:45:48,451 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2025-03-03 14:45:48,451 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2025-03-03 14:45:48,452 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * Use SBE=true [2025-03-03 14:45:48,452 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-03 14:45:48,452 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-03 14:45:48,452 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-03 14:45:48,453 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2025-03-03 14:45:48,453 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2025-03-03 14:45:48,453 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2025-03-03 14:45:48,453 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-03 14:45:48,453 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2025-03-03 14:45:48,453 INFO L153 SettingsManager]: * Compute procedure contracts=false [2025-03-03 14:45:48,454 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2025-03-03 14:45:48,454 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-03 14:45:48,454 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2025-03-03 14:45:48,454 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2025-03-03 14:45:48,454 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2025-03-03 14:45:48,454 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2025-03-03 14:45:48,454 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2025-03-03 14:45:48,454 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ac8e60fb32c268c01bf0cc1d1cd76454411c67e3ab15d16b4eca5e74b982e97f [2025-03-03 14:45:48,688 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-03 14:45:48,696 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-03 14:45:48,698 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-03 14:45:48,699 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-03 14:45:48,699 INFO L274 PluginConnector]: CDTParser initialized [2025-03-03 14:45:48,700 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2025-03-03 14:45:49,824 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/37d1e1dc4/9d67e21523c04cefa6c6e27d73ed7ecd/FLAGcf73da47b [2025-03-03 14:45:50,081 INFO L384 CDTParser]: Found 1 translation units. [2025-03-03 14:45:50,081 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2025-03-03 14:45:50,091 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/37d1e1dc4/9d67e21523c04cefa6c6e27d73ed7ecd/FLAGcf73da47b [2025-03-03 14:45:50,395 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/37d1e1dc4/9d67e21523c04cefa6c6e27d73ed7ecd [2025-03-03 14:45:50,397 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-03 14:45:50,398 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-03 14:45:50,399 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-03 14:45:50,399 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-03 14:45:50,402 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-03 14:45:50,403 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,404 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@322b4289 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50, skipping insertion in model container [2025-03-03 14:45:50,405 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,425 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-03 14:45:50,635 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c[14522,14535] [2025-03-03 14:45:50,639 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-03 14:45:50,650 INFO L200 MainTranslator]: Completed pre-run [2025-03-03 14:45:50,709 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/seq-mthreaded/pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c[14522,14535] [2025-03-03 14:45:50,710 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-03 14:45:50,726 INFO L204 MainTranslator]: Completed translation [2025-03-03 14:45:50,727 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50 WrapperNode [2025-03-03 14:45:50,727 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-03 14:45:50,728 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-03 14:45:50,728 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-03 14:45:50,728 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-03 14:45:50,732 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,747 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,784 INFO L138 Inliner]: procedures = 32, calls = 48, calls flagged for inlining = 12, calls inlined = 12, statements flattened = 499 [2025-03-03 14:45:50,792 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-03 14:45:50,792 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-03 14:45:50,792 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-03 14:45:50,792 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-03 14:45:50,799 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,800 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,808 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,834 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-03 14:45:50,835 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,835 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,844 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,845 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,847 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,848 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,850 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-03 14:45:50,850 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-03 14:45:50,851 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-03 14:45:50,851 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-03 14:45:50,851 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50" (1/1) ... [2025-03-03 14:45:50,855 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2025-03-03 14:45:50,870 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:45:50,885 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2025-03-03 14:45:50,887 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2025-03-03 14:45:50,906 INFO L130 BoogieDeclarations]: Found specification of procedure read_manual_selection_history [2025-03-03 14:45:50,906 INFO L138 BoogieDeclarations]: Found implementation of procedure read_manual_selection_history [2025-03-03 14:45:50,906 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-03 14:45:50,906 INFO L130 BoogieDeclarations]: Found specification of procedure read_side2_failed_history [2025-03-03 14:45:50,906 INFO L138 BoogieDeclarations]: Found implementation of procedure read_side2_failed_history [2025-03-03 14:45:50,907 INFO L130 BoogieDeclarations]: Found specification of procedure assert [2025-03-03 14:45:50,907 INFO L138 BoogieDeclarations]: Found implementation of procedure assert [2025-03-03 14:45:50,907 INFO L130 BoogieDeclarations]: Found specification of procedure flip_the_side [2025-03-03 14:45:50,907 INFO L138 BoogieDeclarations]: Found implementation of procedure flip_the_side [2025-03-03 14:45:50,907 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2025-03-03 14:45:50,907 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2025-03-03 14:45:50,907 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-03 14:45:50,907 INFO L130 BoogieDeclarations]: Found specification of procedure read_side1_failed_history [2025-03-03 14:45:50,907 INFO L138 BoogieDeclarations]: Found implementation of procedure read_side1_failed_history [2025-03-03 14:45:50,908 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-03 14:45:50,908 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-03 14:45:50,908 INFO L130 BoogieDeclarations]: Found specification of procedure read_active_side_history [2025-03-03 14:45:50,908 INFO L138 BoogieDeclarations]: Found implementation of procedure read_active_side_history [2025-03-03 14:45:50,982 INFO L256 CfgBuilder]: Building ICFG [2025-03-03 14:45:50,984 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-03 14:45:51,432 INFO L? ?]: Removed 113 outVars from TransFormulas that were not future-live. [2025-03-03 14:45:51,433 INFO L307 CfgBuilder]: Performing block encoding [2025-03-03 14:45:51,445 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-03 14:45:51,445 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-03 14:45:51,445 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 03.03 02:45:51 BoogieIcfgContainer [2025-03-03 14:45:51,445 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-03 14:45:51,447 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2025-03-03 14:45:51,447 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2025-03-03 14:45:51,450 INFO L274 PluginConnector]: TraceAbstraction initialized [2025-03-03 14:45:51,451 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.03 02:45:50" (1/3) ... [2025-03-03 14:45:51,452 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6cf527ca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.03 02:45:51, skipping insertion in model container [2025-03-03 14:45:51,452 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.03 02:45:50" (2/3) ... [2025-03-03 14:45:51,453 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6cf527ca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.03 02:45:51, skipping insertion in model container [2025-03-03 14:45:51,453 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 03.03 02:45:51" (3/3) ... [2025-03-03 14:45:51,454 INFO L128 eAbstractionObserver]: Analyzing ICFG pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c [2025-03-03 14:45:51,465 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2025-03-03 14:45:51,467 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG pals_STARTPALS_ActiveStandby.4_1.ufo.UNBOUNDED.pals.c that has 8 procedures, 177 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2025-03-03 14:45:51,544 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2025-03-03 14:45:51,552 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@6bb2947, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2025-03-03 14:45:51,552 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2025-03-03 14:45:51,558 INFO L276 IsEmpty]: Start isEmpty. Operand has 177 states, 137 states have (on average 1.5474452554744527) internal successors, (212), 139 states have internal predecessors, (212), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-03 14:45:51,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2025-03-03 14:45:51,564 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:51,564 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:51,565 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:51,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:51,569 INFO L85 PathProgramCache]: Analyzing trace with hash 694007597, now seen corresponding path program 1 times [2025-03-03 14:45:51,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:51,577 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445842457] [2025-03-03 14:45:51,577 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:51,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:51,641 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-03 14:45:51,682 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-03 14:45:51,682 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:51,683 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:51,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-03 14:45:51,806 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:51,806 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445842457] [2025-03-03 14:45:51,806 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445842457] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:51,806 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:51,807 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-03 14:45:51,807 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1333293873] [2025-03-03 14:45:51,808 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:51,811 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2025-03-03 14:45:51,811 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:51,824 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-03 14:45:51,824 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-03 14:45:51,826 INFO L87 Difference]: Start difference. First operand has 177 states, 137 states have (on average 1.5474452554744527) internal successors, (212), 139 states have internal predecessors, (212), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) Second operand has 2 states, 2 states have (on average 12.0) internal successors, (24), 2 states have internal predecessors, (24), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-03 14:45:51,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:51,860 INFO L93 Difference]: Finished difference Result 335 states and 546 transitions. [2025-03-03 14:45:51,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-03 14:45:51,861 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 12.0) internal successors, (24), 2 states have internal predecessors, (24), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 28 [2025-03-03 14:45:51,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:51,866 INFO L225 Difference]: With dead ends: 335 [2025-03-03 14:45:51,867 INFO L226 Difference]: Without dead ends: 174 [2025-03-03 14:45:51,869 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-03 14:45:51,871 INFO L435 NwaCegarLoop]: 269 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 269 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:51,871 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 269 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:51,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2025-03-03 14:45:51,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2025-03-03 14:45:51,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 174 states, 135 states have (on average 1.5333333333333334) internal successors, (207), 136 states have internal predecessors, (207), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-03 14:45:51,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 269 transitions. [2025-03-03 14:45:51,905 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 269 transitions. Word has length 28 [2025-03-03 14:45:51,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:51,906 INFO L471 AbstractCegarLoop]: Abstraction has 174 states and 269 transitions. [2025-03-03 14:45:51,906 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 12.0) internal successors, (24), 2 states have internal predecessors, (24), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-03 14:45:51,906 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 269 transitions. [2025-03-03 14:45:51,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2025-03-03 14:45:51,910 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:51,910 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:51,910 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2025-03-03 14:45:51,910 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:51,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:51,911 INFO L85 PathProgramCache]: Analyzing trace with hash -1344048692, now seen corresponding path program 1 times [2025-03-03 14:45:51,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:51,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2132417308] [2025-03-03 14:45:51,912 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:51,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:51,930 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-03 14:45:51,952 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-03 14:45:51,954 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:51,954 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:52,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-03 14:45:52,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:52,112 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2132417308] [2025-03-03 14:45:52,113 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2132417308] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:52,113 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:52,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-03 14:45:52,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [311365379] [2025-03-03 14:45:52,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:52,114 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2025-03-03 14:45:52,114 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:52,115 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-03 14:45:52,116 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-03 14:45:52,116 INFO L87 Difference]: Start difference. First operand 174 states and 269 transitions. Second operand has 6 states, 5 states have (on average 4.8) internal successors, (24), 6 states have internal predecessors, (24), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-03 14:45:52,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:52,188 INFO L93 Difference]: Finished difference Result 334 states and 512 transitions. [2025-03-03 14:45:52,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-03 14:45:52,189 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 4.8) internal successors, (24), 6 states have internal predecessors, (24), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 28 [2025-03-03 14:45:52,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:52,190 INFO L225 Difference]: With dead ends: 334 [2025-03-03 14:45:52,190 INFO L226 Difference]: Without dead ends: 174 [2025-03-03 14:45:52,191 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-03 14:45:52,192 INFO L435 NwaCegarLoop]: 265 mSDtfsCounter, 0 mSDsluCounter, 1038 mSDsCounter, 0 mSdLazyCounter, 27 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1303 SdHoareTripleChecker+Invalid, 38 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 27 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:52,192 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1303 Invalid, 38 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 27 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:52,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2025-03-03 14:45:52,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2025-03-03 14:45:52,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 174 states, 135 states have (on average 1.4444444444444444) internal successors, (195), 136 states have internal predecessors, (195), 31 states have call successors, (31), 7 states have call predecessors, (31), 7 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-03 14:45:52,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 257 transitions. [2025-03-03 14:45:52,202 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 257 transitions. Word has length 28 [2025-03-03 14:45:52,202 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:52,202 INFO L471 AbstractCegarLoop]: Abstraction has 174 states and 257 transitions. [2025-03-03 14:45:52,202 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 4.8) internal successors, (24), 6 states have internal predecessors, (24), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-03 14:45:52,202 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 257 transitions. [2025-03-03 14:45:52,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2025-03-03 14:45:52,203 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:52,203 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:52,203 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2025-03-03 14:45:52,204 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:52,204 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:52,204 INFO L85 PathProgramCache]: Analyzing trace with hash -1871439799, now seen corresponding path program 1 times [2025-03-03 14:45:52,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:52,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883496738] [2025-03-03 14:45:52,204 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:52,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:52,230 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-03 14:45:52,263 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-03 14:45:52,264 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:52,264 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:52,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-03 14:45:52,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:52,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883496738] [2025-03-03 14:45:52,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1883496738] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:52,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:52,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:52,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1964058586] [2025-03-03 14:45:52,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:52,423 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:52,424 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:52,424 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:52,424 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:52,425 INFO L87 Difference]: Start difference. First operand 174 states and 257 transitions. Second operand has 4 states, 4 states have (on average 8.75) internal successors, (35), 3 states have internal predecessors, (35), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-03 14:45:52,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:52,480 INFO L93 Difference]: Finished difference Result 335 states and 504 transitions. [2025-03-03 14:45:52,480 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:52,481 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 8.75) internal successors, (35), 3 states have internal predecessors, (35), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 39 [2025-03-03 14:45:52,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:52,482 INFO L225 Difference]: With dead ends: 335 [2025-03-03 14:45:52,483 INFO L226 Difference]: Without dead ends: 178 [2025-03-03 14:45:52,485 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:52,485 INFO L435 NwaCegarLoop]: 251 mSDtfsCounter, 3 mSDsluCounter, 492 mSDsCounter, 0 mSdLazyCounter, 24 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 743 SdHoareTripleChecker+Invalid, 27 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 24 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:52,485 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 743 Invalid, 27 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 24 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:52,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states. [2025-03-03 14:45:52,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2025-03-03 14:45:52,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 138 states have (on average 1.434782608695652) internal successors, (198), 139 states have internal predecessors, (198), 31 states have call successors, (31), 8 states have call predecessors, (31), 8 states have return successors, (31), 31 states have call predecessors, (31), 31 states have call successors, (31) [2025-03-03 14:45:52,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 260 transitions. [2025-03-03 14:45:52,504 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 260 transitions. Word has length 39 [2025-03-03 14:45:52,504 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:52,504 INFO L471 AbstractCegarLoop]: Abstraction has 178 states and 260 transitions. [2025-03-03 14:45:52,504 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 8.75) internal successors, (35), 3 states have internal predecessors, (35), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2025-03-03 14:45:52,504 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 260 transitions. [2025-03-03 14:45:52,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2025-03-03 14:45:52,505 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:52,505 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:52,505 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2025-03-03 14:45:52,505 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:52,505 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:52,505 INFO L85 PathProgramCache]: Analyzing trace with hash -2048793082, now seen corresponding path program 1 times [2025-03-03 14:45:52,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:52,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248986283] [2025-03-03 14:45:52,506 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:52,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:52,522 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 55 statements into 1 equivalence classes. [2025-03-03 14:45:52,536 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 55 of 55 statements. [2025-03-03 14:45:52,537 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:52,537 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:52,606 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:52,606 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:52,606 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248986283] [2025-03-03 14:45:52,606 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248986283] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:52,606 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:52,606 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-03 14:45:52,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089919695] [2025-03-03 14:45:52,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:52,607 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-03-03 14:45:52,607 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:52,607 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-03 14:45:52,607 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-03 14:45:52,608 INFO L87 Difference]: Start difference. First operand 178 states and 260 transitions. Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:52,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:52,644 INFO L93 Difference]: Finished difference Result 488 states and 723 transitions. [2025-03-03 14:45:52,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-03 14:45:52,645 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 55 [2025-03-03 14:45:52,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:52,648 INFO L225 Difference]: With dead ends: 488 [2025-03-03 14:45:52,648 INFO L226 Difference]: Without dead ends: 327 [2025-03-03 14:45:52,649 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-03 14:45:52,650 INFO L435 NwaCegarLoop]: 267 mSDtfsCounter, 208 mSDsluCounter, 248 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 208 SdHoareTripleChecker+Valid, 515 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:52,650 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [208 Valid, 515 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:52,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states. [2025-03-03 14:45:52,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 322. [2025-03-03 14:45:52,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322 states, 245 states have (on average 1.453061224489796) internal successors, (356), 247 states have internal predecessors, (356), 60 states have call successors, (60), 16 states have call predecessors, (60), 16 states have return successors, (60), 59 states have call predecessors, (60), 60 states have call successors, (60) [2025-03-03 14:45:52,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 476 transitions. [2025-03-03 14:45:52,679 INFO L78 Accepts]: Start accepts. Automaton has 322 states and 476 transitions. Word has length 55 [2025-03-03 14:45:52,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:52,679 INFO L471 AbstractCegarLoop]: Abstraction has 322 states and 476 transitions. [2025-03-03 14:45:52,679 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:52,679 INFO L276 IsEmpty]: Start isEmpty. Operand 322 states and 476 transitions. [2025-03-03 14:45:52,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2025-03-03 14:45:52,682 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:52,682 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:52,682 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2025-03-03 14:45:52,682 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:52,682 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:52,682 INFO L85 PathProgramCache]: Analyzing trace with hash 71981321, now seen corresponding path program 1 times [2025-03-03 14:45:52,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:52,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342091789] [2025-03-03 14:45:52,682 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:52,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:52,704 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-03-03 14:45:52,724 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-03-03 14:45:52,725 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:52,725 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:52,789 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:52,789 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:52,789 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [342091789] [2025-03-03 14:45:52,789 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [342091789] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:52,789 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:52,789 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-03 14:45:52,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [930567159] [2025-03-03 14:45:52,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:52,790 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-03-03 14:45:52,790 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:52,791 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-03 14:45:52,791 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-03 14:45:52,792 INFO L87 Difference]: Start difference. First operand 322 states and 476 transitions. Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:52,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:52,845 INFO L93 Difference]: Finished difference Result 905 states and 1349 transitions. [2025-03-03 14:45:52,846 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-03 14:45:52,846 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 56 [2025-03-03 14:45:52,846 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:52,853 INFO L225 Difference]: With dead ends: 905 [2025-03-03 14:45:52,854 INFO L226 Difference]: Without dead ends: 600 [2025-03-03 14:45:52,855 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-03 14:45:52,857 INFO L435 NwaCegarLoop]: 287 mSDtfsCounter, 210 mSDsluCounter, 250 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 210 SdHoareTripleChecker+Valid, 537 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:52,857 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [210 Valid, 537 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:52,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 600 states. [2025-03-03 14:45:52,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 600 to 594. [2025-03-03 14:45:52,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 594 states, 445 states have (on average 1.4629213483146069) internal successors, (651), 449 states have internal predecessors, (651), 117 states have call successors, (117), 31 states have call predecessors, (117), 31 states have return successors, (117), 114 states have call predecessors, (117), 117 states have call successors, (117) [2025-03-03 14:45:52,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 594 states to 594 states and 885 transitions. [2025-03-03 14:45:52,900 INFO L78 Accepts]: Start accepts. Automaton has 594 states and 885 transitions. Word has length 56 [2025-03-03 14:45:52,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:52,900 INFO L471 AbstractCegarLoop]: Abstraction has 594 states and 885 transitions. [2025-03-03 14:45:52,901 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:52,901 INFO L276 IsEmpty]: Start isEmpty. Operand 594 states and 885 transitions. [2025-03-03 14:45:52,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2025-03-03 14:45:52,906 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:52,906 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:52,906 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2025-03-03 14:45:52,907 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:52,907 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:52,907 INFO L85 PathProgramCache]: Analyzing trace with hash 1579533130, now seen corresponding path program 1 times [2025-03-03 14:45:52,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:52,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783939083] [2025-03-03 14:45:52,921 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:52,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:52,935 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-03-03 14:45:52,961 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-03-03 14:45:52,962 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:52,962 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:53,060 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:53,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:53,060 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783939083] [2025-03-03 14:45:53,060 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [783939083] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:53,060 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:53,061 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-03 14:45:53,061 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1462382567] [2025-03-03 14:45:53,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:53,062 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-03-03 14:45:53,062 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:53,062 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-03 14:45:53,062 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:53,062 INFO L87 Difference]: Start difference. First operand 594 states and 885 transitions. Second operand has 5 states, 5 states have (on average 9.0) internal successors, (45), 5 states have internal predecessors, (45), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:53,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:53,253 INFO L93 Difference]: Finished difference Result 1271 states and 1888 transitions. [2025-03-03 14:45:53,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-03 14:45:53,254 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 9.0) internal successors, (45), 5 states have internal predecessors, (45), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 56 [2025-03-03 14:45:53,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:53,261 INFO L225 Difference]: With dead ends: 1271 [2025-03-03 14:45:53,261 INFO L226 Difference]: Without dead ends: 694 [2025-03-03 14:45:53,264 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:53,264 INFO L435 NwaCegarLoop]: 225 mSDtfsCounter, 355 mSDsluCounter, 440 mSDsCounter, 0 mSdLazyCounter, 94 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 355 SdHoareTripleChecker+Valid, 665 SdHoareTripleChecker+Invalid, 108 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 94 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:53,264 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [355 Valid, 665 Invalid, 108 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 94 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:45:53,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 694 states. [2025-03-03 14:45:53,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 694 to 682. [2025-03-03 14:45:53,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 682 states, 520 states have (on average 1.448076923076923) internal successors, (753), 523 states have internal predecessors, (753), 124 states have call successors, (124), 37 states have call predecessors, (124), 37 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:53,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 682 states to 682 states and 1001 transitions. [2025-03-03 14:45:53,318 INFO L78 Accepts]: Start accepts. Automaton has 682 states and 1001 transitions. Word has length 56 [2025-03-03 14:45:53,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:53,318 INFO L471 AbstractCegarLoop]: Abstraction has 682 states and 1001 transitions. [2025-03-03 14:45:53,319 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 9.0) internal successors, (45), 5 states have internal predecessors, (45), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:53,319 INFO L276 IsEmpty]: Start isEmpty. Operand 682 states and 1001 transitions. [2025-03-03 14:45:53,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2025-03-03 14:45:53,320 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:53,320 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:53,320 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2025-03-03 14:45:53,321 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:53,321 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:53,321 INFO L85 PathProgramCache]: Analyzing trace with hash 1741593550, now seen corresponding path program 1 times [2025-03-03 14:45:53,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:53,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711701086] [2025-03-03 14:45:53,322 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:53,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:53,338 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 57 statements into 1 equivalence classes. [2025-03-03 14:45:53,356 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 57 of 57 statements. [2025-03-03 14:45:53,357 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:53,357 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:53,457 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:53,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:53,458 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1711701086] [2025-03-03 14:45:53,458 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1711701086] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:53,458 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:53,458 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-03 14:45:53,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [623696029] [2025-03-03 14:45:53,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:53,459 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-03-03 14:45:53,459 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:53,459 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-03 14:45:53,459 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:53,460 INFO L87 Difference]: Start difference. First operand 682 states and 1001 transitions. Second operand has 5 states, 5 states have (on average 9.2) internal successors, (46), 5 states have internal predecessors, (46), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:53,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:53,626 INFO L93 Difference]: Finished difference Result 1271 states and 1880 transitions. [2025-03-03 14:45:53,627 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-03 14:45:53,627 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 9.2) internal successors, (46), 5 states have internal predecessors, (46), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 57 [2025-03-03 14:45:53,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:53,632 INFO L225 Difference]: With dead ends: 1271 [2025-03-03 14:45:53,632 INFO L226 Difference]: Without dead ends: 694 [2025-03-03 14:45:53,634 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:53,635 INFO L435 NwaCegarLoop]: 226 mSDtfsCounter, 352 mSDsluCounter, 442 mSDsCounter, 0 mSdLazyCounter, 91 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 352 SdHoareTripleChecker+Valid, 668 SdHoareTripleChecker+Invalid, 104 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 91 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:53,636 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [352 Valid, 668 Invalid, 104 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 91 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:45:53,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 694 states. [2025-03-03 14:45:53,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 694 to 682. [2025-03-03 14:45:53,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 682 states, 520 states have (on average 1.4403846153846154) internal successors, (749), 523 states have internal predecessors, (749), 124 states have call successors, (124), 37 states have call predecessors, (124), 37 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:53,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 682 states to 682 states and 997 transitions. [2025-03-03 14:45:53,688 INFO L78 Accepts]: Start accepts. Automaton has 682 states and 997 transitions. Word has length 57 [2025-03-03 14:45:53,689 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:53,689 INFO L471 AbstractCegarLoop]: Abstraction has 682 states and 997 transitions. [2025-03-03 14:45:53,689 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 9.2) internal successors, (46), 5 states have internal predecessors, (46), 3 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-03 14:45:53,689 INFO L276 IsEmpty]: Start isEmpty. Operand 682 states and 997 transitions. [2025-03-03 14:45:53,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2025-03-03 14:45:53,691 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:53,691 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:53,691 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2025-03-03 14:45:53,691 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:53,691 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:53,692 INFO L85 PathProgramCache]: Analyzing trace with hash 821324773, now seen corresponding path program 1 times [2025-03-03 14:45:53,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:53,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [931053858] [2025-03-03 14:45:53,692 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:53,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:53,709 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 58 statements into 1 equivalence classes. [2025-03-03 14:45:53,726 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 58 of 58 statements. [2025-03-03 14:45:53,726 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:53,726 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:53,892 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:53,892 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:53,892 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [931053858] [2025-03-03 14:45:53,893 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [931053858] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:53,893 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:53,893 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:53,893 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [372052660] [2025-03-03 14:45:53,893 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:53,893 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:53,893 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:53,894 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:53,894 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:53,894 INFO L87 Difference]: Start difference. First operand 682 states and 997 transitions. Second operand has 4 states, 4 states have (on average 11.75) internal successors, (47), 3 states have internal predecessors, (47), 2 states have call successors, (5), 3 states have call predecessors, (5), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2025-03-03 14:45:53,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:53,943 INFO L93 Difference]: Finished difference Result 1279 states and 1892 transitions. [2025-03-03 14:45:53,943 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:53,943 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 11.75) internal successors, (47), 3 states have internal predecessors, (47), 2 states have call successors, (5), 3 states have call predecessors, (5), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 58 [2025-03-03 14:45:53,944 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:53,947 INFO L225 Difference]: With dead ends: 1279 [2025-03-03 14:45:53,947 INFO L226 Difference]: Without dead ends: 702 [2025-03-03 14:45:53,949 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:53,950 INFO L435 NwaCegarLoop]: 253 mSDtfsCounter, 4 mSDsluCounter, 502 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 755 SdHoareTripleChecker+Invalid, 16 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:53,950 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 755 Invalid, 16 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:53,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 702 states. [2025-03-03 14:45:53,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 702 to 702. [2025-03-03 14:45:53,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 702 states, 536 states have (on average 1.4272388059701493) internal successors, (765), 539 states have internal predecessors, (765), 124 states have call successors, (124), 41 states have call predecessors, (124), 41 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:53,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 702 states to 702 states and 1013 transitions. [2025-03-03 14:45:53,986 INFO L78 Accepts]: Start accepts. Automaton has 702 states and 1013 transitions. Word has length 58 [2025-03-03 14:45:53,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:53,986 INFO L471 AbstractCegarLoop]: Abstraction has 702 states and 1013 transitions. [2025-03-03 14:45:53,986 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 11.75) internal successors, (47), 3 states have internal predecessors, (47), 2 states have call successors, (5), 3 states have call predecessors, (5), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2025-03-03 14:45:53,986 INFO L276 IsEmpty]: Start isEmpty. Operand 702 states and 1013 transitions. [2025-03-03 14:45:53,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2025-03-03 14:45:53,987 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:53,987 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:53,987 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2025-03-03 14:45:53,987 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:53,988 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:53,988 INFO L85 PathProgramCache]: Analyzing trace with hash -274372889, now seen corresponding path program 1 times [2025-03-03 14:45:53,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:53,988 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374509025] [2025-03-03 14:45:53,988 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:53,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:53,998 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 66 statements into 1 equivalence classes. [2025-03-03 14:45:54,008 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 66 of 66 statements. [2025-03-03 14:45:54,009 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:54,009 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:54,143 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:54,143 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:54,143 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [374509025] [2025-03-03 14:45:54,143 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [374509025] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:54,143 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:54,143 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:54,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1046218829] [2025-03-03 14:45:54,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:54,144 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:54,144 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:54,144 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:54,144 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:54,144 INFO L87 Difference]: Start difference. First operand 702 states and 1013 transitions. Second operand has 4 states, 4 states have (on average 13.25) internal successors, (53), 3 states have internal predecessors, (53), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (4), 1 states have call predecessors, (4), 1 states have call successors, (4) [2025-03-03 14:45:54,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:54,202 INFO L93 Difference]: Finished difference Result 1319 states and 1936 transitions. [2025-03-03 14:45:54,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:54,203 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 13.25) internal successors, (53), 3 states have internal predecessors, (53), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (4), 1 states have call predecessors, (4), 1 states have call successors, (4) Word has length 66 [2025-03-03 14:45:54,203 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:54,207 INFO L225 Difference]: With dead ends: 1319 [2025-03-03 14:45:54,207 INFO L226 Difference]: Without dead ends: 722 [2025-03-03 14:45:54,208 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:54,209 INFO L435 NwaCegarLoop]: 250 mSDtfsCounter, 4 mSDsluCounter, 491 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 741 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:54,209 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 741 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:54,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 722 states. [2025-03-03 14:45:54,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 722 to 722. [2025-03-03 14:45:54,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 722 states, 552 states have (on average 1.414855072463768) internal successors, (781), 555 states have internal predecessors, (781), 124 states have call successors, (124), 45 states have call predecessors, (124), 45 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:54,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 722 states and 1029 transitions. [2025-03-03 14:45:54,241 INFO L78 Accepts]: Start accepts. Automaton has 722 states and 1029 transitions. Word has length 66 [2025-03-03 14:45:54,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:54,242 INFO L471 AbstractCegarLoop]: Abstraction has 722 states and 1029 transitions. [2025-03-03 14:45:54,242 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 13.25) internal successors, (53), 3 states have internal predecessors, (53), 2 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (4), 1 states have call predecessors, (4), 1 states have call successors, (4) [2025-03-03 14:45:54,242 INFO L276 IsEmpty]: Start isEmpty. Operand 722 states and 1029 transitions. [2025-03-03 14:45:54,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2025-03-03 14:45:54,243 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:54,243 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:54,243 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2025-03-03 14:45:54,243 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:54,244 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:54,244 INFO L85 PathProgramCache]: Analyzing trace with hash -1001852371, now seen corresponding path program 1 times [2025-03-03 14:45:54,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:54,244 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1522365399] [2025-03-03 14:45:54,244 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:54,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:54,253 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes. [2025-03-03 14:45:54,282 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements. [2025-03-03 14:45:54,282 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:54,282 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:54,372 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:54,372 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:54,372 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1522365399] [2025-03-03 14:45:54,372 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1522365399] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:54,372 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:54,373 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:54,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880352076] [2025-03-03 14:45:54,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:54,373 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:54,373 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:54,373 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:54,374 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:54,374 INFO L87 Difference]: Start difference. First operand 722 states and 1029 transitions. Second operand has 4 states, 4 states have (on average 14.75) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-03 14:45:54,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:54,425 INFO L93 Difference]: Finished difference Result 1355 states and 1952 transitions. [2025-03-03 14:45:54,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:54,425 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.75) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 74 [2025-03-03 14:45:54,426 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:54,429 INFO L225 Difference]: With dead ends: 1355 [2025-03-03 14:45:54,430 INFO L226 Difference]: Without dead ends: 738 [2025-03-03 14:45:54,431 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:54,432 INFO L435 NwaCegarLoop]: 255 mSDtfsCounter, 3 mSDsluCounter, 496 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 751 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:54,432 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 751 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:54,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 738 states. [2025-03-03 14:45:54,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 738 to 738. [2025-03-03 14:45:54,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 738 states, 564 states have (on average 1.4060283687943262) internal successors, (793), 567 states have internal predecessors, (793), 124 states have call successors, (124), 49 states have call predecessors, (124), 49 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:54,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 738 states to 738 states and 1041 transitions. [2025-03-03 14:45:54,467 INFO L78 Accepts]: Start accepts. Automaton has 738 states and 1041 transitions. Word has length 74 [2025-03-03 14:45:54,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:54,467 INFO L471 AbstractCegarLoop]: Abstraction has 738 states and 1041 transitions. [2025-03-03 14:45:54,468 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.75) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-03 14:45:54,468 INFO L276 IsEmpty]: Start isEmpty. Operand 738 states and 1041 transitions. [2025-03-03 14:45:54,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2025-03-03 14:45:54,469 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:54,469 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:54,469 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2025-03-03 14:45:54,469 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:54,470 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:54,470 INFO L85 PathProgramCache]: Analyzing trace with hash -1633780634, now seen corresponding path program 1 times [2025-03-03 14:45:54,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:54,471 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [784827937] [2025-03-03 14:45:54,471 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:54,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:54,481 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes. [2025-03-03 14:45:54,492 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements. [2025-03-03 14:45:54,492 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:54,492 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:54,593 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2025-03-03 14:45:54,593 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:54,593 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [784827937] [2025-03-03 14:45:54,593 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [784827937] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:54,594 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:54,594 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:54,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408657827] [2025-03-03 14:45:54,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:54,594 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:54,594 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:54,594 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:54,594 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:54,594 INFO L87 Difference]: Start difference. First operand 738 states and 1041 transitions. Second operand has 4 states, 4 states have (on average 14.75) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-03 14:45:54,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:54,654 INFO L93 Difference]: Finished difference Result 1391 states and 1992 transitions. [2025-03-03 14:45:54,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:54,655 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.75) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 74 [2025-03-03 14:45:54,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:54,659 INFO L225 Difference]: With dead ends: 1391 [2025-03-03 14:45:54,659 INFO L226 Difference]: Without dead ends: 758 [2025-03-03 14:45:54,661 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:54,661 INFO L435 NwaCegarLoop]: 250 mSDtfsCounter, 4 mSDsluCounter, 491 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 741 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:54,661 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 741 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:54,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 758 states. [2025-03-03 14:45:54,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 758 to 758. [2025-03-03 14:45:54,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 758 states, 580 states have (on average 1.3948275862068966) internal successors, (809), 583 states have internal predecessors, (809), 124 states have call successors, (124), 53 states have call predecessors, (124), 53 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:54,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 758 states to 758 states and 1057 transitions. [2025-03-03 14:45:54,712 INFO L78 Accepts]: Start accepts. Automaton has 758 states and 1057 transitions. Word has length 74 [2025-03-03 14:45:54,712 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:54,712 INFO L471 AbstractCegarLoop]: Abstraction has 758 states and 1057 transitions. [2025-03-03 14:45:54,712 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.75) internal successors, (59), 3 states have internal predecessors, (59), 2 states have call successors, (7), 3 states have call predecessors, (7), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2025-03-03 14:45:54,713 INFO L276 IsEmpty]: Start isEmpty. Operand 758 states and 1057 transitions. [2025-03-03 14:45:54,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2025-03-03 14:45:54,714 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:54,714 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:54,714 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2025-03-03 14:45:54,714 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:54,715 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:54,715 INFO L85 PathProgramCache]: Analyzing trace with hash 1674046212, now seen corresponding path program 1 times [2025-03-03 14:45:54,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:54,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [57936798] [2025-03-03 14:45:54,715 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:54,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:54,725 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 82 statements into 1 equivalence classes. [2025-03-03 14:45:54,737 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 82 of 82 statements. [2025-03-03 14:45:54,737 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:54,737 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:54,863 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-03 14:45:54,863 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:54,863 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [57936798] [2025-03-03 14:45:54,863 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [57936798] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:54,864 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:54,864 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:54,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [304721035] [2025-03-03 14:45:54,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:54,864 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:54,864 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:54,864 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:54,864 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:54,864 INFO L87 Difference]: Start difference. First operand 758 states and 1057 transitions. Second operand has 4 states, 4 states have (on average 15.25) internal successors, (61), 3 states have internal predecessors, (61), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 1 states have call predecessors, (6), 1 states have call successors, (6) [2025-03-03 14:45:54,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:54,935 INFO L93 Difference]: Finished difference Result 1435 states and 2020 transitions. [2025-03-03 14:45:54,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:54,936 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 15.25) internal successors, (61), 3 states have internal predecessors, (61), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 1 states have call predecessors, (6), 1 states have call successors, (6) Word has length 82 [2025-03-03 14:45:54,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:54,940 INFO L225 Difference]: With dead ends: 1435 [2025-03-03 14:45:54,941 INFO L226 Difference]: Without dead ends: 782 [2025-03-03 14:45:54,943 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:54,944 INFO L435 NwaCegarLoop]: 254 mSDtfsCounter, 5 mSDsluCounter, 499 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5 SdHoareTripleChecker+Valid, 753 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:54,944 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [5 Valid, 753 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 20 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:54,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 782 states. [2025-03-03 14:45:54,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 782 to 782. [2025-03-03 14:45:54,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 782 states, 600 states have (on average 1.3816666666666666) internal successors, (829), 603 states have internal predecessors, (829), 124 states have call successors, (124), 57 states have call predecessors, (124), 57 states have return successors, (124), 121 states have call predecessors, (124), 124 states have call successors, (124) [2025-03-03 14:45:54,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 782 states to 782 states and 1077 transitions. [2025-03-03 14:45:54,980 INFO L78 Accepts]: Start accepts. Automaton has 782 states and 1077 transitions. Word has length 82 [2025-03-03 14:45:54,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:54,981 INFO L471 AbstractCegarLoop]: Abstraction has 782 states and 1077 transitions. [2025-03-03 14:45:54,981 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 15.25) internal successors, (61), 3 states have internal predecessors, (61), 2 states have call successors, (8), 3 states have call predecessors, (8), 1 states have return successors, (6), 1 states have call predecessors, (6), 1 states have call successors, (6) [2025-03-03 14:45:54,981 INFO L276 IsEmpty]: Start isEmpty. Operand 782 states and 1077 transitions. [2025-03-03 14:45:54,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2025-03-03 14:45:54,984 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:54,984 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:54,984 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2025-03-03 14:45:54,984 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:54,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:54,985 INFO L85 PathProgramCache]: Analyzing trace with hash 1130128505, now seen corresponding path program 1 times [2025-03-03 14:45:54,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:54,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170111251] [2025-03-03 14:45:54,985 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:54,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:54,997 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 85 statements into 1 equivalence classes. [2025-03-03 14:45:55,065 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 85 of 85 statements. [2025-03-03 14:45:55,065 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:55,065 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:55,480 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2025-03-03 14:45:55,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:55,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [170111251] [2025-03-03 14:45:55,480 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [170111251] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:55,480 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:55,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-03 14:45:55,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1560052798] [2025-03-03 14:45:55,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:55,481 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-03 14:45:55,481 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:55,481 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-03 14:45:55,481 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:55,482 INFO L87 Difference]: Start difference. First operand 782 states and 1077 transitions. Second operand has 7 states, 7 states have (on average 9.142857142857142) internal successors, (64), 6 states have internal predecessors, (64), 3 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 4 states have call predecessors, (7), 3 states have call successors, (7) [2025-03-03 14:45:55,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:55,719 INFO L93 Difference]: Finished difference Result 2029 states and 2783 transitions. [2025-03-03 14:45:55,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-03 14:45:55,720 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 9.142857142857142) internal successors, (64), 6 states have internal predecessors, (64), 3 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 4 states have call predecessors, (7), 3 states have call successors, (7) Word has length 85 [2025-03-03 14:45:55,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:55,727 INFO L225 Difference]: With dead ends: 2029 [2025-03-03 14:45:55,727 INFO L226 Difference]: Without dead ends: 1352 [2025-03-03 14:45:55,729 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:45:55,729 INFO L435 NwaCegarLoop]: 259 mSDtfsCounter, 196 mSDsluCounter, 1193 mSDsCounter, 0 mSdLazyCounter, 102 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 200 SdHoareTripleChecker+Valid, 1452 SdHoareTripleChecker+Invalid, 105 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 102 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:55,729 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [200 Valid, 1452 Invalid, 105 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 102 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:45:55,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1352 states. [2025-03-03 14:45:55,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1352 to 1066. [2025-03-03 14:45:55,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1066 states, 811 states have (on average 1.369913686806412) internal successors, (1111), 816 states have internal predecessors, (1111), 172 states have call successors, (172), 82 states have call predecessors, (172), 82 states have return successors, (172), 167 states have call predecessors, (172), 172 states have call successors, (172) [2025-03-03 14:45:55,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1066 states to 1066 states and 1455 transitions. [2025-03-03 14:45:55,807 INFO L78 Accepts]: Start accepts. Automaton has 1066 states and 1455 transitions. Word has length 85 [2025-03-03 14:45:55,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:55,808 INFO L471 AbstractCegarLoop]: Abstraction has 1066 states and 1455 transitions. [2025-03-03 14:45:55,808 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 9.142857142857142) internal successors, (64), 6 states have internal predecessors, (64), 3 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 4 states have call predecessors, (7), 3 states have call successors, (7) [2025-03-03 14:45:55,808 INFO L276 IsEmpty]: Start isEmpty. Operand 1066 states and 1455 transitions. [2025-03-03 14:45:55,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2025-03-03 14:45:55,810 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:55,810 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:55,810 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2025-03-03 14:45:55,810 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:55,810 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:55,811 INFO L85 PathProgramCache]: Analyzing trace with hash 1474332186, now seen corresponding path program 1 times [2025-03-03 14:45:55,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:55,811 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266107430] [2025-03-03 14:45:55,811 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:55,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:55,823 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-03 14:45:55,837 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-03 14:45:55,837 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:55,837 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:55,934 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2025-03-03 14:45:55,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:55,935 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266107430] [2025-03-03 14:45:55,935 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266107430] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:55,935 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:55,935 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:55,935 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918935769] [2025-03-03 14:45:55,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:55,935 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:55,935 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:55,936 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:55,936 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:55,936 INFO L87 Difference]: Start difference. First operand 1066 states and 1455 transitions. Second operand has 4 states, 4 states have (on average 17.0) internal successors, (68), 3 states have internal predecessors, (68), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-03 14:45:56,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:56,016 INFO L93 Difference]: Finished difference Result 1983 states and 2728 transitions. [2025-03-03 14:45:56,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:45:56,017 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 17.0) internal successors, (68), 3 states have internal predecessors, (68), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) Word has length 89 [2025-03-03 14:45:56,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:56,023 INFO L225 Difference]: With dead ends: 1983 [2025-03-03 14:45:56,023 INFO L226 Difference]: Without dead ends: 1090 [2025-03-03 14:45:56,026 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:56,026 INFO L435 NwaCegarLoop]: 255 mSDtfsCounter, 3 mSDsluCounter, 496 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 751 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:56,026 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 751 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:56,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1090 states. [2025-03-03 14:45:56,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1090 to 1090. [2025-03-03 14:45:56,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1090 states, 829 states have (on average 1.3618817852834741) internal successors, (1129), 834 states have internal predecessors, (1129), 172 states have call successors, (172), 88 states have call predecessors, (172), 88 states have return successors, (172), 167 states have call predecessors, (172), 172 states have call successors, (172) [2025-03-03 14:45:56,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1090 states to 1090 states and 1473 transitions. [2025-03-03 14:45:56,083 INFO L78 Accepts]: Start accepts. Automaton has 1090 states and 1473 transitions. Word has length 89 [2025-03-03 14:45:56,083 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:56,083 INFO L471 AbstractCegarLoop]: Abstraction has 1090 states and 1473 transitions. [2025-03-03 14:45:56,084 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 17.0) internal successors, (68), 3 states have internal predecessors, (68), 2 states have call successors, (9), 3 states have call predecessors, (9), 1 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-03 14:45:56,084 INFO L276 IsEmpty]: Start isEmpty. Operand 1090 states and 1473 transitions. [2025-03-03 14:45:56,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2025-03-03 14:45:56,085 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:56,085 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:56,085 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2025-03-03 14:45:56,085 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:56,085 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:56,085 INFO L85 PathProgramCache]: Analyzing trace with hash 339197356, now seen corresponding path program 1 times [2025-03-03 14:45:56,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:56,086 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139093375] [2025-03-03 14:45:56,086 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:56,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:56,095 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 88 statements into 1 equivalence classes. [2025-03-03 14:45:56,104 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 88 of 88 statements. [2025-03-03 14:45:56,105 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:56,105 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:56,321 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2025-03-03 14:45:56,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:56,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139093375] [2025-03-03 14:45:56,322 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139093375] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:45:56,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [69508272] [2025-03-03 14:45:56,322 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:56,323 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:45:56,323 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:45:56,325 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:45:56,326 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2025-03-03 14:45:56,408 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 88 statements into 1 equivalence classes. [2025-03-03 14:45:56,461 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 88 of 88 statements. [2025-03-03 14:45:56,461 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:56,461 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:56,467 INFO L256 TraceCheckSpWp]: Trace formula consists of 474 conjuncts, 13 conjuncts are in the unsatisfiable core [2025-03-03 14:45:56,473 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:45:56,571 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2025-03-03 14:45:56,571 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-03-03 14:45:56,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [69508272] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:56,571 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-03-03 14:45:56,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [10] total 15 [2025-03-03 14:45:56,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523093920] [2025-03-03 14:45:56,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:56,573 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2025-03-03 14:45:56,573 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:56,573 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-03 14:45:56,574 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=180, Unknown=0, NotChecked=0, Total=210 [2025-03-03 14:45:56,574 INFO L87 Difference]: Start difference. First operand 1090 states and 1473 transitions. Second operand has 8 states, 7 states have (on average 9.142857142857142) internal successors, (64), 7 states have internal predecessors, (64), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-03 14:45:56,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:56,749 INFO L93 Difference]: Finished difference Result 2339 states and 3279 transitions. [2025-03-03 14:45:56,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-03 14:45:56,750 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 9.142857142857142) internal successors, (64), 7 states have internal predecessors, (64), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) Word has length 88 [2025-03-03 14:45:56,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:56,757 INFO L225 Difference]: With dead ends: 2339 [2025-03-03 14:45:56,757 INFO L226 Difference]: Without dead ends: 1510 [2025-03-03 14:45:56,760 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 101 GetRequests, 85 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=261, Unknown=0, NotChecked=0, Total=306 [2025-03-03 14:45:56,761 INFO L435 NwaCegarLoop]: 430 mSDtfsCounter, 135 mSDsluCounter, 2384 mSDsCounter, 0 mSdLazyCounter, 124 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 161 SdHoareTripleChecker+Valid, 2814 SdHoareTripleChecker+Invalid, 126 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 124 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:56,761 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [161 Valid, 2814 Invalid, 126 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 124 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:45:56,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1510 states. [2025-03-03 14:45:56,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1510 to 1098. [2025-03-03 14:45:56,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1098 states, 833 states have (on average 1.3529411764705883) internal successors, (1127), 840 states have internal predecessors, (1127), 174 states have call successors, (174), 90 states have call predecessors, (174), 90 states have return successors, (174), 167 states have call predecessors, (174), 174 states have call successors, (174) [2025-03-03 14:45:56,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1098 states to 1098 states and 1475 transitions. [2025-03-03 14:45:56,831 INFO L78 Accepts]: Start accepts. Automaton has 1098 states and 1475 transitions. Word has length 88 [2025-03-03 14:45:56,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:56,832 INFO L471 AbstractCegarLoop]: Abstraction has 1098 states and 1475 transitions. [2025-03-03 14:45:56,832 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 9.142857142857142) internal successors, (64), 7 states have internal predecessors, (64), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (7), 1 states have call predecessors, (7), 1 states have call successors, (7) [2025-03-03 14:45:56,832 INFO L276 IsEmpty]: Start isEmpty. Operand 1098 states and 1475 transitions. [2025-03-03 14:45:56,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2025-03-03 14:45:56,834 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:56,834 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:56,842 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2025-03-03 14:45:57,035 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable14 [2025-03-03 14:45:57,035 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:57,035 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:57,035 INFO L85 PathProgramCache]: Analyzing trace with hash -1078337159, now seen corresponding path program 1 times [2025-03-03 14:45:57,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:57,035 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876950526] [2025-03-03 14:45:57,035 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:57,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:57,046 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 91 statements into 1 equivalence classes. [2025-03-03 14:45:57,057 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 91 of 91 statements. [2025-03-03 14:45:57,057 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:57,057 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:57,142 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2025-03-03 14:45:57,143 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:57,143 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [876950526] [2025-03-03 14:45:57,143 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [876950526] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:57,143 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:57,143 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-03 14:45:57,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1722340776] [2025-03-03 14:45:57,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:57,143 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-03 14:45:57,143 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:57,144 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-03 14:45:57,144 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:57,144 INFO L87 Difference]: Start difference. First operand 1098 states and 1475 transitions. Second operand has 7 states, 7 states have (on average 9.571428571428571) internal successors, (67), 6 states have internal predecessors, (67), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) [2025-03-03 14:45:57,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:57,314 INFO L93 Difference]: Finished difference Result 1978 states and 2660 transitions. [2025-03-03 14:45:57,314 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-03 14:45:57,314 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 9.571428571428571) internal successors, (67), 6 states have internal predecessors, (67), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) Word has length 91 [2025-03-03 14:45:57,314 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:57,320 INFO L225 Difference]: With dead ends: 1978 [2025-03-03 14:45:57,320 INFO L226 Difference]: Without dead ends: 1135 [2025-03-03 14:45:57,322 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:45:57,323 INFO L435 NwaCegarLoop]: 255 mSDtfsCounter, 249 mSDsluCounter, 1206 mSDsCounter, 0 mSdLazyCounter, 75 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 250 SdHoareTripleChecker+Valid, 1461 SdHoareTripleChecker+Invalid, 90 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 75 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:57,323 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [250 Valid, 1461 Invalid, 90 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 75 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:45:57,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1135 states. [2025-03-03 14:45:57,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1135 to 1101. [2025-03-03 14:45:57,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1101 states, 847 states have (on average 1.345926800472255) internal successors, (1140), 859 states have internal predecessors, (1140), 162 states have call successors, (162), 91 states have call predecessors, (162), 91 states have return successors, (162), 150 states have call predecessors, (162), 162 states have call successors, (162) [2025-03-03 14:45:57,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1101 states to 1101 states and 1464 transitions. [2025-03-03 14:45:57,377 INFO L78 Accepts]: Start accepts. Automaton has 1101 states and 1464 transitions. Word has length 91 [2025-03-03 14:45:57,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:57,377 INFO L471 AbstractCegarLoop]: Abstraction has 1101 states and 1464 transitions. [2025-03-03 14:45:57,377 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 9.571428571428571) internal successors, (67), 6 states have internal predecessors, (67), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (7), 3 states have call predecessors, (7), 2 states have call successors, (7) [2025-03-03 14:45:57,378 INFO L276 IsEmpty]: Start isEmpty. Operand 1101 states and 1464 transitions. [2025-03-03 14:45:57,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2025-03-03 14:45:57,379 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:57,379 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:57,380 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2025-03-03 14:45:57,380 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:57,380 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:57,380 INFO L85 PathProgramCache]: Analyzing trace with hash -817180062, now seen corresponding path program 1 times [2025-03-03 14:45:57,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:57,380 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307592239] [2025-03-03 14:45:57,380 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:57,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:57,390 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 93 statements into 1 equivalence classes. [2025-03-03 14:45:57,446 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 93 of 93 statements. [2025-03-03 14:45:57,446 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:57,446 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:57,802 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2025-03-03 14:45:57,803 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:57,803 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307592239] [2025-03-03 14:45:57,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1307592239] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:57,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:57,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-03 14:45:57,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [625498489] [2025-03-03 14:45:57,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:57,804 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-03 14:45:57,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:57,804 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-03 14:45:57,805 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:57,805 INFO L87 Difference]: Start difference. First operand 1101 states and 1464 transitions. Second operand has 7 states, 7 states have (on average 9.428571428571429) internal successors, (66), 6 states have internal predecessors, (66), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-03 14:45:58,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:58,009 INFO L93 Difference]: Finished difference Result 1965 states and 2621 transitions. [2025-03-03 14:45:58,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-03 14:45:58,010 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 9.428571428571429) internal successors, (66), 6 states have internal predecessors, (66), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) Word has length 93 [2025-03-03 14:45:58,010 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:58,016 INFO L225 Difference]: With dead ends: 1965 [2025-03-03 14:45:58,016 INFO L226 Difference]: Without dead ends: 1099 [2025-03-03 14:45:58,018 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:45:58,018 INFO L435 NwaCegarLoop]: 284 mSDtfsCounter, 150 mSDsluCounter, 1293 mSDsCounter, 0 mSdLazyCounter, 78 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 152 SdHoareTripleChecker+Valid, 1577 SdHoareTripleChecker+Invalid, 80 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 78 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:58,018 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [152 Valid, 1577 Invalid, 80 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 78 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:45:58,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1099 states. [2025-03-03 14:45:58,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1099 to 992. [2025-03-03 14:45:58,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 992 states, 765 states have (on average 1.3477124183006537) internal successors, (1031), 775 states have internal predecessors, (1031), 145 states have call successors, (145), 81 states have call predecessors, (145), 81 states have return successors, (145), 135 states have call predecessors, (145), 145 states have call successors, (145) [2025-03-03 14:45:58,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 992 states to 992 states and 1321 transitions. [2025-03-03 14:45:58,070 INFO L78 Accepts]: Start accepts. Automaton has 992 states and 1321 transitions. Word has length 93 [2025-03-03 14:45:58,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:58,071 INFO L471 AbstractCegarLoop]: Abstraction has 992 states and 1321 transitions. [2025-03-03 14:45:58,071 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 9.428571428571429) internal successors, (66), 6 states have internal predecessors, (66), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-03 14:45:58,071 INFO L276 IsEmpty]: Start isEmpty. Operand 992 states and 1321 transitions. [2025-03-03 14:45:58,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2025-03-03 14:45:58,072 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:58,072 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:58,072 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2025-03-03 14:45:58,072 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:58,072 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:58,072 INFO L85 PathProgramCache]: Analyzing trace with hash 358797666, now seen corresponding path program 1 times [2025-03-03 14:45:58,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:58,072 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355479759] [2025-03-03 14:45:58,072 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:58,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:58,085 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 94 statements into 1 equivalence classes. [2025-03-03 14:45:58,101 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 94 of 94 statements. [2025-03-03 14:45:58,102 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:58,102 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:58,460 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2025-03-03 14:45:58,461 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:58,461 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355479759] [2025-03-03 14:45:58,461 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355479759] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:58,461 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:58,461 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-03 14:45:58,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257119833] [2025-03-03 14:45:58,461 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:58,461 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-03 14:45:58,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:58,462 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-03 14:45:58,462 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:58,462 INFO L87 Difference]: Start difference. First operand 992 states and 1321 transitions. Second operand has 7 states, 7 states have (on average 10.142857142857142) internal successors, (71), 6 states have internal predecessors, (71), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 3 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:45:58,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:58,800 INFO L93 Difference]: Finished difference Result 1910 states and 2538 transitions. [2025-03-03 14:45:58,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-03 14:45:58,800 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 10.142857142857142) internal successors, (71), 6 states have internal predecessors, (71), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 3 states have call predecessors, (8), 2 states have call successors, (8) Word has length 94 [2025-03-03 14:45:58,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:58,805 INFO L225 Difference]: With dead ends: 1910 [2025-03-03 14:45:58,805 INFO L226 Difference]: Without dead ends: 1083 [2025-03-03 14:45:58,807 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:45:58,808 INFO L435 NwaCegarLoop]: 317 mSDtfsCounter, 511 mSDsluCounter, 1090 mSDsCounter, 0 mSdLazyCounter, 179 mSolverCounterSat, 51 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 517 SdHoareTripleChecker+Valid, 1407 SdHoareTripleChecker+Invalid, 230 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 51 IncrementalHoareTripleChecker+Valid, 179 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:58,808 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [517 Valid, 1407 Invalid, 230 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [51 Valid, 179 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-03-03 14:45:58,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1083 states. [2025-03-03 14:45:58,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1083 to 1030. [2025-03-03 14:45:58,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1030 states, 788 states have (on average 1.3261421319796953) internal successors, (1045), 799 states have internal predecessors, (1045), 154 states have call successors, (154), 87 states have call predecessors, (154), 87 states have return successors, (154), 143 states have call predecessors, (154), 154 states have call successors, (154) [2025-03-03 14:45:58,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1030 states to 1030 states and 1353 transitions. [2025-03-03 14:45:58,864 INFO L78 Accepts]: Start accepts. Automaton has 1030 states and 1353 transitions. Word has length 94 [2025-03-03 14:45:58,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:58,864 INFO L471 AbstractCegarLoop]: Abstraction has 1030 states and 1353 transitions. [2025-03-03 14:45:58,864 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 10.142857142857142) internal successors, (71), 6 states have internal predecessors, (71), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 3 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:45:58,865 INFO L276 IsEmpty]: Start isEmpty. Operand 1030 states and 1353 transitions. [2025-03-03 14:45:58,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2025-03-03 14:45:58,865 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:58,865 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:58,866 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2025-03-03 14:45:58,866 INFO L396 AbstractCegarLoop]: === Iteration 19 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:58,866 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:58,866 INFO L85 PathProgramCache]: Analyzing trace with hash 513865440, now seen corresponding path program 1 times [2025-03-03 14:45:58,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:58,866 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [521227170] [2025-03-03 14:45:58,866 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:58,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:58,878 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 96 statements into 1 equivalence classes. [2025-03-03 14:45:58,897 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 96 of 96 statements. [2025-03-03 14:45:58,898 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:58,898 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:59,219 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2025-03-03 14:45:59,220 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:59,220 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [521227170] [2025-03-03 14:45:59,220 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [521227170] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:59,220 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:59,220 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-03 14:45:59,220 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1758525421] [2025-03-03 14:45:59,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:59,221 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-03 14:45:59,221 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:59,221 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-03 14:45:59,221 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:45:59,221 INFO L87 Difference]: Start difference. First operand 1030 states and 1353 transitions. Second operand has 7 states, 7 states have (on average 10.428571428571429) internal successors, (73), 6 states have internal predecessors, (73), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-03 14:45:59,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:59,577 INFO L93 Difference]: Finished difference Result 1995 states and 2604 transitions. [2025-03-03 14:45:59,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-03 14:45:59,577 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 10.428571428571429) internal successors, (73), 6 states have internal predecessors, (73), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) Word has length 96 [2025-03-03 14:45:59,578 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:59,583 INFO L225 Difference]: With dead ends: 1995 [2025-03-03 14:45:59,583 INFO L226 Difference]: Without dead ends: 1143 [2025-03-03 14:45:59,585 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:45:59,585 INFO L435 NwaCegarLoop]: 277 mSDtfsCounter, 506 mSDsluCounter, 945 mSDsCounter, 0 mSdLazyCounter, 177 mSolverCounterSat, 51 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 512 SdHoareTripleChecker+Valid, 1222 SdHoareTripleChecker+Invalid, 228 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 51 IncrementalHoareTripleChecker+Valid, 177 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:59,585 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [512 Valid, 1222 Invalid, 228 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [51 Valid, 177 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2025-03-03 14:45:59,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states. [2025-03-03 14:45:59,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 1052. [2025-03-03 14:45:59,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1052 states, 802 states have (on average 1.3104738154613467) internal successors, (1051), 814 states have internal predecessors, (1051), 157 states have call successors, (157), 92 states have call predecessors, (157), 92 states have return successors, (157), 145 states have call predecessors, (157), 157 states have call successors, (157) [2025-03-03 14:45:59,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1052 states to 1052 states and 1365 transitions. [2025-03-03 14:45:59,674 INFO L78 Accepts]: Start accepts. Automaton has 1052 states and 1365 transitions. Word has length 96 [2025-03-03 14:45:59,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:45:59,674 INFO L471 AbstractCegarLoop]: Abstraction has 1052 states and 1365 transitions. [2025-03-03 14:45:59,674 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 10.428571428571429) internal successors, (73), 6 states have internal predecessors, (73), 3 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (8), 4 states have call predecessors, (8), 3 states have call successors, (8) [2025-03-03 14:45:59,674 INFO L276 IsEmpty]: Start isEmpty. Operand 1052 states and 1365 transitions. [2025-03-03 14:45:59,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2025-03-03 14:45:59,675 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:45:59,675 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:45:59,675 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2025-03-03 14:45:59,675 INFO L396 AbstractCegarLoop]: === Iteration 20 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:45:59,676 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:45:59,676 INFO L85 PathProgramCache]: Analyzing trace with hash -1665753688, now seen corresponding path program 1 times [2025-03-03 14:45:59,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:45:59,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1224198835] [2025-03-03 14:45:59,676 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:45:59,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:45:59,685 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 97 statements into 1 equivalence classes. [2025-03-03 14:45:59,698 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 97 of 97 statements. [2025-03-03 14:45:59,698 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:45:59,698 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:45:59,748 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-03 14:45:59,748 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:45:59,748 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1224198835] [2025-03-03 14:45:59,748 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1224198835] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:45:59,748 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:45:59,748 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:45:59,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1302978307] [2025-03-03 14:45:59,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:45:59,749 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:45:59,749 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:45:59,749 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:45:59,749 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:45:59,749 INFO L87 Difference]: Start difference. First operand 1052 states and 1365 transitions. Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 4 states have internal predecessors, (73), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:45:59,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:45:59,900 INFO L93 Difference]: Finished difference Result 2746 states and 3589 transitions. [2025-03-03 14:45:59,900 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-03 14:45:59,900 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 18.25) internal successors, (73), 4 states have internal predecessors, (73), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 97 [2025-03-03 14:45:59,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:45:59,909 INFO L225 Difference]: With dead ends: 2746 [2025-03-03 14:45:59,909 INFO L226 Difference]: Without dead ends: 1950 [2025-03-03 14:45:59,911 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:45:59,911 INFO L435 NwaCegarLoop]: 460 mSDtfsCounter, 197 mSDsluCounter, 687 mSDsCounter, 0 mSdLazyCounter, 35 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 197 SdHoareTripleChecker+Valid, 1147 SdHoareTripleChecker+Invalid, 42 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 35 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:45:59,911 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [197 Valid, 1147 Invalid, 42 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 35 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:45:59,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1950 states. [2025-03-03 14:46:00,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1950 to 1771. [2025-03-03 14:46:00,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1771 states, 1333 states have (on average 1.3113278319579895) internal successors, (1748), 1353 states have internal predecessors, (1748), 280 states have call successors, (280), 157 states have call predecessors, (280), 157 states have return successors, (280), 260 states have call predecessors, (280), 280 states have call successors, (280) [2025-03-03 14:46:00,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1771 states to 1771 states and 2308 transitions. [2025-03-03 14:46:00,060 INFO L78 Accepts]: Start accepts. Automaton has 1771 states and 2308 transitions. Word has length 97 [2025-03-03 14:46:00,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:00,060 INFO L471 AbstractCegarLoop]: Abstraction has 1771 states and 2308 transitions. [2025-03-03 14:46:00,060 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 18.25) internal successors, (73), 4 states have internal predecessors, (73), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:00,060 INFO L276 IsEmpty]: Start isEmpty. Operand 1771 states and 2308 transitions. [2025-03-03 14:46:00,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2025-03-03 14:46:00,061 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:00,062 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:00,062 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2025-03-03 14:46:00,062 INFO L396 AbstractCegarLoop]: === Iteration 21 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:00,062 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:00,062 INFO L85 PathProgramCache]: Analyzing trace with hash -966329109, now seen corresponding path program 1 times [2025-03-03 14:46:00,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:00,063 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1642563135] [2025-03-03 14:46:00,063 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:00,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:00,077 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 99 statements into 1 equivalence classes. [2025-03-03 14:46:00,088 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 99 of 99 statements. [2025-03-03 14:46:00,088 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:00,088 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:00,151 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-03 14:46:00,151 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:00,151 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1642563135] [2025-03-03 14:46:00,152 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1642563135] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:46:00,152 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:46:00,152 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:46:00,152 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1191562563] [2025-03-03 14:46:00,152 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:46:00,152 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:46:00,152 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:00,153 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:46:00,153 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:46:00,153 INFO L87 Difference]: Start difference. First operand 1771 states and 2308 transitions. Second operand has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:00,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:00,360 INFO L93 Difference]: Finished difference Result 4115 states and 5385 transitions. [2025-03-03 14:46:00,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-03 14:46:00,360 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 99 [2025-03-03 14:46:00,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:00,372 INFO L225 Difference]: With dead ends: 4115 [2025-03-03 14:46:00,373 INFO L226 Difference]: Without dead ends: 2669 [2025-03-03 14:46:00,377 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:46:00,378 INFO L435 NwaCegarLoop]: 478 mSDtfsCounter, 198 mSDsluCounter, 703 mSDsCounter, 0 mSdLazyCounter, 40 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 198 SdHoareTripleChecker+Valid, 1181 SdHoareTripleChecker+Invalid, 46 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 40 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:00,378 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [198 Valid, 1181 Invalid, 46 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 40 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:46:00,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2669 states. [2025-03-03 14:46:00,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2669 to 2488. [2025-03-03 14:46:00,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2488 states, 1862 states have (on average 1.3098818474758325) internal successors, (2439), 1890 states have internal predecessors, (2439), 403 states have call successors, (403), 222 states have call predecessors, (403), 222 states have return successors, (403), 375 states have call predecessors, (403), 403 states have call successors, (403) [2025-03-03 14:46:00,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2488 states to 2488 states and 3245 transitions. [2025-03-03 14:46:00,557 INFO L78 Accepts]: Start accepts. Automaton has 2488 states and 3245 transitions. Word has length 99 [2025-03-03 14:46:00,558 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:00,558 INFO L471 AbstractCegarLoop]: Abstraction has 2488 states and 3245 transitions. [2025-03-03 14:46:00,558 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:00,558 INFO L276 IsEmpty]: Start isEmpty. Operand 2488 states and 3245 transitions. [2025-03-03 14:46:00,559 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2025-03-03 14:46:00,559 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:00,559 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:00,560 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2025-03-03 14:46:00,560 INFO L396 AbstractCegarLoop]: === Iteration 22 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:00,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:00,560 INFO L85 PathProgramCache]: Analyzing trace with hash -122429907, now seen corresponding path program 1 times [2025-03-03 14:46:00,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:00,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1644915493] [2025-03-03 14:46:00,560 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:00,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:00,569 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 99 statements into 1 equivalence classes. [2025-03-03 14:46:00,577 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 99 of 99 statements. [2025-03-03 14:46:00,577 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:00,577 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:00,620 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-03 14:46:00,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:00,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1644915493] [2025-03-03 14:46:00,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1644915493] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:46:00,621 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:46:00,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:46:00,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1082985739] [2025-03-03 14:46:00,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:46:00,621 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:46:00,621 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:00,622 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:46:00,622 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:46:00,622 INFO L87 Difference]: Start difference. First operand 2488 states and 3245 transitions. Second operand has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:00,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:00,893 INFO L93 Difference]: Finished difference Result 6379 states and 8358 transitions. [2025-03-03 14:46:00,893 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-03 14:46:00,894 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 99 [2025-03-03 14:46:00,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:00,913 INFO L225 Difference]: With dead ends: 6379 [2025-03-03 14:46:00,913 INFO L226 Difference]: Without dead ends: 4320 [2025-03-03 14:46:00,919 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:46:00,921 INFO L435 NwaCegarLoop]: 468 mSDtfsCounter, 204 mSDsluCounter, 701 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 204 SdHoareTripleChecker+Valid, 1169 SdHoareTripleChecker+Invalid, 35 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:00,922 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [204 Valid, 1169 Invalid, 35 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:46:00,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4320 states. [2025-03-03 14:46:01,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4320 to 3988. [2025-03-03 14:46:01,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3988 states, 2951 states have (on average 1.2978651304642495) internal successors, (3830), 2995 states have internal predecessors, (3830), 672 states have call successors, (672), 364 states have call predecessors, (672), 364 states have return successors, (672), 628 states have call predecessors, (672), 672 states have call successors, (672) [2025-03-03 14:46:01,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3988 states to 3988 states and 5174 transitions. [2025-03-03 14:46:01,201 INFO L78 Accepts]: Start accepts. Automaton has 3988 states and 5174 transitions. Word has length 99 [2025-03-03 14:46:01,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:01,201 INFO L471 AbstractCegarLoop]: Abstraction has 3988 states and 5174 transitions. [2025-03-03 14:46:01,201 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 3 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:01,201 INFO L276 IsEmpty]: Start isEmpty. Operand 3988 states and 5174 transitions. [2025-03-03 14:46:01,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2025-03-03 14:46:01,203 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:01,203 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:01,203 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2025-03-03 14:46:01,203 INFO L396 AbstractCegarLoop]: === Iteration 23 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:01,204 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:01,204 INFO L85 PathProgramCache]: Analyzing trace with hash -1512744895, now seen corresponding path program 1 times [2025-03-03 14:46:01,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:01,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431756924] [2025-03-03 14:46:01,204 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:01,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:01,216 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 100 statements into 1 equivalence classes. [2025-03-03 14:46:01,219 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 100 of 100 statements. [2025-03-03 14:46:01,220 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:01,220 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:01,250 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-03 14:46:01,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:01,251 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431756924] [2025-03-03 14:46:01,251 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431756924] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:46:01,251 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:46:01,251 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-03 14:46:01,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [346765300] [2025-03-03 14:46:01,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:46:01,251 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2025-03-03 14:46:01,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:01,252 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-03 14:46:01,252 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-03 14:46:01,252 INFO L87 Difference]: Start difference. First operand 3988 states and 5174 transitions. Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:01,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:01,536 INFO L93 Difference]: Finished difference Result 7667 states and 9991 transitions. [2025-03-03 14:46:01,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-03 14:46:01,537 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 100 [2025-03-03 14:46:01,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:01,570 INFO L225 Difference]: With dead ends: 7667 [2025-03-03 14:46:01,570 INFO L226 Difference]: Without dead ends: 4021 [2025-03-03 14:46:01,585 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-03 14:46:01,586 INFO L435 NwaCegarLoop]: 258 mSDtfsCounter, 6 mSDsluCounter, 223 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 481 SdHoareTripleChecker+Invalid, 40 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:01,586 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 481 Invalid, 40 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:46:01,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4021 states. [2025-03-03 14:46:01,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4021 to 3994. [2025-03-03 14:46:01,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3994 states, 2957 states have (on average 1.2972607372336828) internal successors, (3836), 3001 states have internal predecessors, (3836), 672 states have call successors, (672), 364 states have call predecessors, (672), 364 states have return successors, (672), 628 states have call predecessors, (672), 672 states have call successors, (672) [2025-03-03 14:46:01,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3994 states to 3994 states and 5180 transitions. [2025-03-03 14:46:01,942 INFO L78 Accepts]: Start accepts. Automaton has 3994 states and 5180 transitions. Word has length 100 [2025-03-03 14:46:01,942 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:01,942 INFO L471 AbstractCegarLoop]: Abstraction has 3994 states and 5180 transitions. [2025-03-03 14:46:01,946 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:01,947 INFO L276 IsEmpty]: Start isEmpty. Operand 3994 states and 5180 transitions. [2025-03-03 14:46:01,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2025-03-03 14:46:01,948 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:01,948 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:01,949 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2025-03-03 14:46:01,949 INFO L396 AbstractCegarLoop]: === Iteration 24 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:01,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:01,949 INFO L85 PathProgramCache]: Analyzing trace with hash 741340076, now seen corresponding path program 1 times [2025-03-03 14:46:01,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:01,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281624325] [2025-03-03 14:46:01,949 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:01,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:01,960 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 101 statements into 1 equivalence classes. [2025-03-03 14:46:01,969 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 101 of 101 statements. [2025-03-03 14:46:01,970 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:01,970 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:02,038 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-03 14:46:02,038 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:02,038 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281624325] [2025-03-03 14:46:02,038 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281624325] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:46:02,038 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:46:02,038 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:46:02,039 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1607434136] [2025-03-03 14:46:02,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:46:02,039 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:46:02,039 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:02,039 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:46:02,039 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:46:02,040 INFO L87 Difference]: Start difference. First operand 3994 states and 5180 transitions. Second operand has 4 states, 4 states have (on average 19.25) internal successors, (77), 4 states have internal predecessors, (77), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:02,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:02,278 INFO L93 Difference]: Finished difference Result 7632 states and 9918 transitions. [2025-03-03 14:46:02,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:46:02,278 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 19.25) internal successors, (77), 4 states have internal predecessors, (77), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 101 [2025-03-03 14:46:02,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:02,298 INFO L225 Difference]: With dead ends: 7632 [2025-03-03 14:46:02,298 INFO L226 Difference]: Without dead ends: 3710 [2025-03-03 14:46:02,307 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:46:02,308 INFO L435 NwaCegarLoop]: 260 mSDtfsCounter, 79 mSDsluCounter, 470 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 79 SdHoareTripleChecker+Valid, 730 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:02,309 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [79 Valid, 730 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:46:02,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3710 states. [2025-03-03 14:46:02,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3710 to 3647. [2025-03-03 14:46:02,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3647 states, 2693 states have (on average 1.305607129595247) internal successors, (3516), 2727 states have internal predecessors, (3516), 620 states have call successors, (620), 333 states have call predecessors, (620), 333 states have return successors, (620), 586 states have call predecessors, (620), 620 states have call successors, (620) [2025-03-03 14:46:02,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3647 states to 3647 states and 4756 transitions. [2025-03-03 14:46:02,524 INFO L78 Accepts]: Start accepts. Automaton has 3647 states and 4756 transitions. Word has length 101 [2025-03-03 14:46:02,524 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:02,524 INFO L471 AbstractCegarLoop]: Abstraction has 3647 states and 4756 transitions. [2025-03-03 14:46:02,525 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 19.25) internal successors, (77), 4 states have internal predecessors, (77), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:02,525 INFO L276 IsEmpty]: Start isEmpty. Operand 3647 states and 4756 transitions. [2025-03-03 14:46:02,526 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2025-03-03 14:46:02,526 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:02,526 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:02,527 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2025-03-03 14:46:02,527 INFO L396 AbstractCegarLoop]: === Iteration 25 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:02,527 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:02,527 INFO L85 PathProgramCache]: Analyzing trace with hash -1575153410, now seen corresponding path program 1 times [2025-03-03 14:46:02,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:02,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1829062949] [2025-03-03 14:46:02,527 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:02,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:02,538 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 102 statements into 1 equivalence classes. [2025-03-03 14:46:02,547 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 102 of 102 statements. [2025-03-03 14:46:02,547 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:02,548 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:02,645 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2025-03-03 14:46:02,646 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:02,646 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1829062949] [2025-03-03 14:46:02,646 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1829062949] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:46:02,646 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:46:02,646 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-03 14:46:02,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609624707] [2025-03-03 14:46:02,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:46:02,647 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2025-03-03 14:46:02,647 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:02,647 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-03 14:46:02,647 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-03 14:46:02,648 INFO L87 Difference]: Start difference. First operand 3647 states and 4756 transitions. Second operand has 4 states, 4 states have (on average 19.5) internal successors, (78), 4 states have internal predecessors, (78), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:02,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:02,831 INFO L93 Difference]: Finished difference Result 7103 states and 9281 transitions. [2025-03-03 14:46:02,831 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-03 14:46:02,831 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 19.5) internal successors, (78), 4 states have internal predecessors, (78), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 102 [2025-03-03 14:46:02,832 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:02,846 INFO L225 Difference]: With dead ends: 7103 [2025-03-03 14:46:02,846 INFO L226 Difference]: Without dead ends: 3571 [2025-03-03 14:46:02,855 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2025-03-03 14:46:02,855 INFO L435 NwaCegarLoop]: 265 mSDtfsCounter, 60 mSDsluCounter, 475 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 60 SdHoareTripleChecker+Valid, 740 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:02,856 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [60 Valid, 740 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:46:02,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3571 states. [2025-03-03 14:46:03,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3571 to 2747. [2025-03-03 14:46:03,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2747 states, 2027 states have (on average 1.297483966452886) internal successors, (2630), 2046 states have internal predecessors, (2630), 469 states have call successors, (469), 250 states have call predecessors, (469), 250 states have return successors, (469), 450 states have call predecessors, (469), 469 states have call successors, (469) [2025-03-03 14:46:03,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2747 states to 2747 states and 3568 transitions. [2025-03-03 14:46:03,029 INFO L78 Accepts]: Start accepts. Automaton has 2747 states and 3568 transitions. Word has length 102 [2025-03-03 14:46:03,030 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:03,030 INFO L471 AbstractCegarLoop]: Abstraction has 2747 states and 3568 transitions. [2025-03-03 14:46:03,030 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 19.5) internal successors, (78), 4 states have internal predecessors, (78), 2 states have call successors, (9), 2 states have call predecessors, (9), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2025-03-03 14:46:03,030 INFO L276 IsEmpty]: Start isEmpty. Operand 2747 states and 3568 transitions. [2025-03-03 14:46:03,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 152 [2025-03-03 14:46:03,035 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:03,035 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:03,035 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24 [2025-03-03 14:46:03,035 INFO L396 AbstractCegarLoop]: === Iteration 26 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:03,036 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:03,036 INFO L85 PathProgramCache]: Analyzing trace with hash -1361916819, now seen corresponding path program 1 times [2025-03-03 14:46:03,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:03,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308574685] [2025-03-03 14:46:03,036 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:03,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:03,055 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 151 statements into 1 equivalence classes. [2025-03-03 14:46:03,078 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 151 of 151 statements. [2025-03-03 14:46:03,078 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:03,078 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:03,303 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 16 proven. 12 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-03 14:46:03,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:03,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308574685] [2025-03-03 14:46:03,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308574685] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:03,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [738359730] [2025-03-03 14:46:03,304 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:03,304 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:03,304 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:03,306 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:03,308 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2025-03-03 14:46:03,406 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 151 statements into 1 equivalence classes. [2025-03-03 14:46:03,479 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 151 of 151 statements. [2025-03-03 14:46:03,479 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:03,479 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:03,482 INFO L256 TraceCheckSpWp]: Trace formula consists of 727 conjuncts, 22 conjuncts are in the unsatisfiable core [2025-03-03 14:46:03,486 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:03,518 INFO L134 CoverageAnalysis]: Checked inductivity of 84 backedges. 41 proven. 0 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2025-03-03 14:46:03,519 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-03-03 14:46:03,519 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [738359730] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:46:03,519 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-03-03 14:46:03,519 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 10 [2025-03-03 14:46:03,519 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1374265275] [2025-03-03 14:46:03,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:46:03,519 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2025-03-03 14:46:03,522 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:03,522 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-03 14:46:03,522 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-03-03 14:46:03,522 INFO L87 Difference]: Start difference. First operand 2747 states and 3568 transitions. Second operand has 5 states, 4 states have (on average 25.0) internal successors, (100), 5 states have internal predecessors, (100), 3 states have call successors, (12), 2 states have call predecessors, (12), 3 states have return successors, (12), 2 states have call predecessors, (12), 3 states have call successors, (12) [2025-03-03 14:46:03,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:03,666 INFO L93 Difference]: Finished difference Result 5172 states and 6755 transitions. [2025-03-03 14:46:03,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-03 14:46:03,667 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 4 states have (on average 25.0) internal successors, (100), 5 states have internal predecessors, (100), 3 states have call successors, (12), 2 states have call predecessors, (12), 3 states have return successors, (12), 2 states have call predecessors, (12), 3 states have call successors, (12) Word has length 151 [2025-03-03 14:46:03,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:03,678 INFO L225 Difference]: With dead ends: 5172 [2025-03-03 14:46:03,679 INFO L226 Difference]: Without dead ends: 2580 [2025-03-03 14:46:03,685 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 157 GetRequests, 149 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-03-03 14:46:03,685 INFO L435 NwaCegarLoop]: 254 mSDtfsCounter, 0 mSDsluCounter, 750 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1004 SdHoareTripleChecker+Invalid, 20 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:03,686 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1004 Invalid, 20 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 20 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2025-03-03 14:46:03,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2580 states. [2025-03-03 14:46:03,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2580 to 2565. [2025-03-03 14:46:03,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2565 states, 1890 states have (on average 1.2936507936507937) internal successors, (2445), 1907 states have internal predecessors, (2445), 440 states have call successors, (440), 234 states have call predecessors, (440), 234 states have return successors, (440), 423 states have call predecessors, (440), 440 states have call successors, (440) [2025-03-03 14:46:03,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2565 states to 2565 states and 3325 transitions. [2025-03-03 14:46:03,890 INFO L78 Accepts]: Start accepts. Automaton has 2565 states and 3325 transitions. Word has length 151 [2025-03-03 14:46:03,890 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:03,890 INFO L471 AbstractCegarLoop]: Abstraction has 2565 states and 3325 transitions. [2025-03-03 14:46:03,890 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 4 states have (on average 25.0) internal successors, (100), 5 states have internal predecessors, (100), 3 states have call successors, (12), 2 states have call predecessors, (12), 3 states have return successors, (12), 2 states have call predecessors, (12), 3 states have call successors, (12) [2025-03-03 14:46:03,891 INFO L276 IsEmpty]: Start isEmpty. Operand 2565 states and 3325 transitions. [2025-03-03 14:46:03,895 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 154 [2025-03-03 14:46:03,895 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:03,895 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:03,902 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2025-03-03 14:46:04,096 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable25 [2025-03-03 14:46:04,097 INFO L396 AbstractCegarLoop]: === Iteration 27 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:04,097 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:04,097 INFO L85 PathProgramCache]: Analyzing trace with hash 467357349, now seen corresponding path program 1 times [2025-03-03 14:46:04,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:04,097 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1626747198] [2025-03-03 14:46:04,097 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:04,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:04,116 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 153 statements into 1 equivalence classes. [2025-03-03 14:46:04,147 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 153 of 153 statements. [2025-03-03 14:46:04,147 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:04,147 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:04,702 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 23 proven. 6 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-03 14:46:04,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:04,703 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1626747198] [2025-03-03 14:46:04,703 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1626747198] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:04,703 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1258671087] [2025-03-03 14:46:04,703 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:04,703 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:04,704 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:04,705 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:04,707 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2025-03-03 14:46:04,814 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 153 statements into 1 equivalence classes. [2025-03-03 14:46:04,885 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 153 of 153 statements. [2025-03-03 14:46:04,885 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:04,885 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:04,888 INFO L256 TraceCheckSpWp]: Trace formula consists of 761 conjuncts, 27 conjuncts are in the unsatisfiable core [2025-03-03 14:46:04,893 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:05,170 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 32 proven. 44 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-03 14:46:05,171 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-03 14:46:05,435 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 12 proven. 17 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-03 14:46:05,436 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1258671087] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-03 14:46:05,436 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-03 14:46:05,436 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 11, 8] total 24 [2025-03-03 14:46:05,436 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2004446502] [2025-03-03 14:46:05,436 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-03 14:46:05,437 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 24 states [2025-03-03 14:46:05,437 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:05,437 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2025-03-03 14:46:05,438 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=487, Unknown=0, NotChecked=0, Total=552 [2025-03-03 14:46:05,438 INFO L87 Difference]: Start difference. First operand 2565 states and 3325 transitions. Second operand has 24 states, 24 states have (on average 10.583333333333334) internal successors, (254), 22 states have internal predecessors, (254), 9 states have call successors, (41), 4 states have call predecessors, (41), 7 states have return successors, (40), 11 states have call predecessors, (40), 9 states have call successors, (40) [2025-03-03 14:46:09,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:09,096 INFO L93 Difference]: Finished difference Result 7494 states and 9742 transitions. [2025-03-03 14:46:09,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2025-03-03 14:46:09,096 INFO L78 Accepts]: Start accepts. Automaton has has 24 states, 24 states have (on average 10.583333333333334) internal successors, (254), 22 states have internal predecessors, (254), 9 states have call successors, (41), 4 states have call predecessors, (41), 7 states have return successors, (40), 11 states have call predecessors, (40), 9 states have call successors, (40) Word has length 153 [2025-03-03 14:46:09,096 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:09,145 INFO L225 Difference]: With dead ends: 7494 [2025-03-03 14:46:09,145 INFO L226 Difference]: Without dead ends: 5165 [2025-03-03 14:46:09,151 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 405 GetRequests, 322 SyntacticMatches, 0 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1798 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1040, Invalid=6100, Unknown=0, NotChecked=0, Total=7140 [2025-03-03 14:46:09,152 INFO L435 NwaCegarLoop]: 642 mSDtfsCounter, 2103 mSDsluCounter, 6132 mSDsCounter, 0 mSdLazyCounter, 3212 mSolverCounterSat, 789 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2103 SdHoareTripleChecker+Valid, 6774 SdHoareTripleChecker+Invalid, 4001 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 789 IncrementalHoareTripleChecker+Valid, 3212 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.9s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:09,152 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2103 Valid, 6774 Invalid, 4001 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [789 Valid, 3212 Invalid, 0 Unknown, 0 Unchecked, 1.9s Time] [2025-03-03 14:46:09,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5165 states. [2025-03-03 14:46:09,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5165 to 4484. [2025-03-03 14:46:09,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4484 states, 3304 states have (on average 1.2966101694915255) internal successors, (4284), 3333 states have internal predecessors, (4284), 765 states have call successors, (765), 414 states have call predecessors, (765), 414 states have return successors, (765), 736 states have call predecessors, (765), 765 states have call successors, (765) [2025-03-03 14:46:09,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4484 states to 4484 states and 5814 transitions. [2025-03-03 14:46:09,496 INFO L78 Accepts]: Start accepts. Automaton has 4484 states and 5814 transitions. Word has length 153 [2025-03-03 14:46:09,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:09,497 INFO L471 AbstractCegarLoop]: Abstraction has 4484 states and 5814 transitions. [2025-03-03 14:46:09,497 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 24 states, 24 states have (on average 10.583333333333334) internal successors, (254), 22 states have internal predecessors, (254), 9 states have call successors, (41), 4 states have call predecessors, (41), 7 states have return successors, (40), 11 states have call predecessors, (40), 9 states have call successors, (40) [2025-03-03 14:46:09,497 INFO L276 IsEmpty]: Start isEmpty. Operand 4484 states and 5814 transitions. [2025-03-03 14:46:09,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2025-03-03 14:46:09,503 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:09,503 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:09,510 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2025-03-03 14:46:09,707 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable26,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:09,707 INFO L396 AbstractCegarLoop]: === Iteration 28 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:09,707 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:09,707 INFO L85 PathProgramCache]: Analyzing trace with hash 155593662, now seen corresponding path program 1 times [2025-03-03 14:46:09,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:09,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [208610242] [2025-03-03 14:46:09,708 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:09,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:09,723 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 154 statements into 1 equivalence classes. [2025-03-03 14:46:09,740 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 154 of 154 statements. [2025-03-03 14:46:09,741 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:09,741 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:09,955 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 15 proven. 12 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-03 14:46:09,956 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:09,956 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [208610242] [2025-03-03 14:46:09,956 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [208610242] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:09,956 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1985508607] [2025-03-03 14:46:09,956 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:09,956 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:09,956 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:09,958 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:09,960 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2025-03-03 14:46:10,055 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 154 statements into 1 equivalence classes. [2025-03-03 14:46:10,116 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 154 of 154 statements. [2025-03-03 14:46:10,116 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:10,116 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:10,119 INFO L256 TraceCheckSpWp]: Trace formula consists of 762 conjuncts, 50 conjuncts are in the unsatisfiable core [2025-03-03 14:46:10,124 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:10,576 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 61 proven. 13 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2025-03-03 14:46:10,577 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-03 14:46:10,982 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 15 proven. 12 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-03 14:46:10,982 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1985508607] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-03 14:46:10,982 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-03 14:46:10,982 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 10, 11] total 22 [2025-03-03 14:46:10,982 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2133440414] [2025-03-03 14:46:10,982 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-03 14:46:10,983 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 22 states [2025-03-03 14:46:10,983 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:10,983 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-03-03 14:46:10,984 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=359, Unknown=0, NotChecked=0, Total=462 [2025-03-03 14:46:10,984 INFO L87 Difference]: Start difference. First operand 4484 states and 5814 transitions. Second operand has 22 states, 22 states have (on average 10.909090909090908) internal successors, (240), 22 states have internal predecessors, (240), 9 states have call successors, (37), 5 states have call predecessors, (37), 6 states have return successors, (36), 9 states have call predecessors, (36), 9 states have call successors, (36) [2025-03-03 14:46:12,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:12,642 INFO L93 Difference]: Finished difference Result 10552 states and 13677 transitions. [2025-03-03 14:46:12,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2025-03-03 14:46:12,642 INFO L78 Accepts]: Start accepts. Automaton has has 22 states, 22 states have (on average 10.909090909090908) internal successors, (240), 22 states have internal predecessors, (240), 9 states have call successors, (37), 5 states have call predecessors, (37), 6 states have return successors, (36), 9 states have call predecessors, (36), 9 states have call successors, (36) Word has length 154 [2025-03-03 14:46:12,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:12,666 INFO L225 Difference]: With dead ends: 10552 [2025-03-03 14:46:12,666 INFO L226 Difference]: Without dead ends: 6315 [2025-03-03 14:46:12,675 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 347 GetRequests, 303 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 483 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=577, Invalid=1493, Unknown=0, NotChecked=0, Total=2070 [2025-03-03 14:46:12,676 INFO L435 NwaCegarLoop]: 390 mSDtfsCounter, 1996 mSDsluCounter, 2854 mSDsCounter, 0 mSdLazyCounter, 1533 mSolverCounterSat, 707 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1996 SdHoareTripleChecker+Valid, 3244 SdHoareTripleChecker+Invalid, 2240 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 707 IncrementalHoareTripleChecker+Valid, 1533 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:12,676 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1996 Valid, 3244 Invalid, 2240 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [707 Valid, 1533 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2025-03-03 14:46:12,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6315 states. [2025-03-03 14:46:13,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6315 to 5961. [2025-03-03 14:46:13,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5961 states, 4402 states have (on average 1.2914584279872785) internal successors, (5685), 4440 states have internal predecessors, (5685), 1003 states have call successors, (1003), 555 states have call predecessors, (1003), 555 states have return successors, (1003), 965 states have call predecessors, (1003), 1003 states have call successors, (1003) [2025-03-03 14:46:13,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5961 states to 5961 states and 7691 transitions. [2025-03-03 14:46:13,217 INFO L78 Accepts]: Start accepts. Automaton has 5961 states and 7691 transitions. Word has length 154 [2025-03-03 14:46:13,217 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:13,217 INFO L471 AbstractCegarLoop]: Abstraction has 5961 states and 7691 transitions. [2025-03-03 14:46:13,217 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 22 states, 22 states have (on average 10.909090909090908) internal successors, (240), 22 states have internal predecessors, (240), 9 states have call successors, (37), 5 states have call predecessors, (37), 6 states have return successors, (36), 9 states have call predecessors, (36), 9 states have call successors, (36) [2025-03-03 14:46:13,218 INFO L276 IsEmpty]: Start isEmpty. Operand 5961 states and 7691 transitions. [2025-03-03 14:46:13,225 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2025-03-03 14:46:13,225 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:13,225 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:13,233 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2025-03-03 14:46:13,428 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable27 [2025-03-03 14:46:13,428 INFO L396 AbstractCegarLoop]: === Iteration 29 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:13,429 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:13,429 INFO L85 PathProgramCache]: Analyzing trace with hash 51084085, now seen corresponding path program 1 times [2025-03-03 14:46:13,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:13,429 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074871869] [2025-03-03 14:46:13,429 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:13,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:13,445 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 156 statements into 1 equivalence classes. [2025-03-03 14:46:13,457 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 156 of 156 statements. [2025-03-03 14:46:13,457 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:13,457 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:13,577 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2025-03-03 14:46:13,578 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:13,578 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2074871869] [2025-03-03 14:46:13,578 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2074871869] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-03 14:46:13,578 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-03 14:46:13,578 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-03 14:46:13,578 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [230746806] [2025-03-03 14:46:13,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-03 14:46:13,578 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2025-03-03 14:46:13,578 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:13,579 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-03 14:46:13,579 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-03 14:46:13,579 INFO L87 Difference]: Start difference. First operand 5961 states and 7691 transitions. Second operand has 7 states, 7 states have (on average 12.857142857142858) internal successors, (90), 6 states have internal predecessors, (90), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 3 states have call predecessors, (13), 2 states have call successors, (13) [2025-03-03 14:46:14,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:14,807 INFO L93 Difference]: Finished difference Result 17481 states and 22611 transitions. [2025-03-03 14:46:14,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-03 14:46:14,807 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 12.857142857142858) internal successors, (90), 6 states have internal predecessors, (90), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 3 states have call predecessors, (13), 2 states have call successors, (13) Word has length 156 [2025-03-03 14:46:14,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:14,850 INFO L225 Difference]: With dead ends: 17481 [2025-03-03 14:46:14,850 INFO L226 Difference]: Without dead ends: 11819 [2025-03-03 14:46:14,865 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2025-03-03 14:46:14,866 INFO L435 NwaCegarLoop]: 477 mSDtfsCounter, 219 mSDsluCounter, 2054 mSDsCounter, 0 mSdLazyCounter, 132 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 224 SdHoareTripleChecker+Valid, 2531 SdHoareTripleChecker+Invalid, 132 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 132 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:14,866 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [224 Valid, 2531 Invalid, 132 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 132 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2025-03-03 14:46:14,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11819 states. [2025-03-03 14:46:15,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11819 to 8890. [2025-03-03 14:46:15,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8890 states, 6511 states have (on average 1.2902779910919981) internal successors, (8401), 6570 states have internal predecessors, (8401), 1550 states have call successors, (1550), 828 states have call predecessors, (1550), 828 states have return successors, (1550), 1491 states have call predecessors, (1550), 1550 states have call successors, (1550) [2025-03-03 14:46:15,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8890 states to 8890 states and 11501 transitions. [2025-03-03 14:46:15,696 INFO L78 Accepts]: Start accepts. Automaton has 8890 states and 11501 transitions. Word has length 156 [2025-03-03 14:46:15,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:15,698 INFO L471 AbstractCegarLoop]: Abstraction has 8890 states and 11501 transitions. [2025-03-03 14:46:15,698 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 12.857142857142858) internal successors, (90), 6 states have internal predecessors, (90), 3 states have call successors, (14), 2 states have call predecessors, (14), 2 states have return successors, (13), 3 states have call predecessors, (13), 2 states have call successors, (13) [2025-03-03 14:46:15,698 INFO L276 IsEmpty]: Start isEmpty. Operand 8890 states and 11501 transitions. [2025-03-03 14:46:15,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2025-03-03 14:46:15,711 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:15,711 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:15,711 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable28 [2025-03-03 14:46:15,711 INFO L396 AbstractCegarLoop]: === Iteration 30 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:15,712 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:15,712 INFO L85 PathProgramCache]: Analyzing trace with hash -1574929623, now seen corresponding path program 1 times [2025-03-03 14:46:15,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:15,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341866320] [2025-03-03 14:46:15,712 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:15,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:15,728 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 156 statements into 1 equivalence classes. [2025-03-03 14:46:15,773 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 156 of 156 statements. [2025-03-03 14:46:15,775 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:15,775 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:16,516 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 20 proven. 9 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2025-03-03 14:46:16,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:16,517 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341866320] [2025-03-03 14:46:16,517 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341866320] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:16,517 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1860558101] [2025-03-03 14:46:16,517 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:16,517 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:16,517 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:16,519 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:16,520 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2025-03-03 14:46:16,622 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 156 statements into 1 equivalence classes. [2025-03-03 14:46:16,694 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 156 of 156 statements. [2025-03-03 14:46:16,694 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:16,694 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:16,698 INFO L256 TraceCheckSpWp]: Trace formula consists of 779 conjuncts, 32 conjuncts are in the unsatisfiable core [2025-03-03 14:46:16,701 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:16,922 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 65 proven. 4 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2025-03-03 14:46:16,922 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-03 14:46:17,113 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 27 proven. 6 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2025-03-03 14:46:17,113 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1860558101] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-03 14:46:17,114 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-03 14:46:17,114 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 13, 10] total 28 [2025-03-03 14:46:17,114 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1330586939] [2025-03-03 14:46:17,114 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-03 14:46:17,114 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 28 states [2025-03-03 14:46:17,114 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:17,115 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2025-03-03 14:46:17,115 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=681, Unknown=0, NotChecked=0, Total=756 [2025-03-03 14:46:17,115 INFO L87 Difference]: Start difference. First operand 8890 states and 11501 transitions. Second operand has 28 states, 28 states have (on average 7.785714285714286) internal successors, (218), 24 states have internal predecessors, (218), 7 states have call successors, (32), 4 states have call predecessors, (32), 8 states have return successors, (34), 10 states have call predecessors, (34), 7 states have call successors, (34) [2025-03-03 14:46:20,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:20,923 INFO L93 Difference]: Finished difference Result 24911 states and 32123 transitions. [2025-03-03 14:46:20,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2025-03-03 14:46:20,924 INFO L78 Accepts]: Start accepts. Automaton has has 28 states, 28 states have (on average 7.785714285714286) internal successors, (218), 24 states have internal predecessors, (218), 7 states have call successors, (32), 4 states have call predecessors, (32), 8 states have return successors, (34), 10 states have call predecessors, (34), 7 states have call successors, (34) Word has length 156 [2025-03-03 14:46:20,924 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:20,990 INFO L225 Difference]: With dead ends: 24911 [2025-03-03 14:46:20,990 INFO L226 Difference]: Without dead ends: 16293 [2025-03-03 14:46:21,009 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 378 GetRequests, 315 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 772 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=522, Invalid=3638, Unknown=0, NotChecked=0, Total=4160 [2025-03-03 14:46:21,010 INFO L435 NwaCegarLoop]: 542 mSDtfsCounter, 870 mSDsluCounter, 7933 mSDsCounter, 0 mSdLazyCounter, 3722 mSolverCounterSat, 345 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 870 SdHoareTripleChecker+Valid, 8475 SdHoareTripleChecker+Invalid, 4067 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 345 IncrementalHoareTripleChecker+Valid, 3722 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.5s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:21,010 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [870 Valid, 8475 Invalid, 4067 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [345 Valid, 3722 Invalid, 0 Unknown, 0 Unchecked, 1.5s Time] [2025-03-03 14:46:21,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16293 states. [2025-03-03 14:46:22,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16293 to 10657. [2025-03-03 14:46:22,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10657 states, 7796 states have (on average 1.2895074397126731) internal successors, (10053), 7872 states have internal predecessors, (10053), 1852 states have call successors, (1852), 1008 states have call predecessors, (1852), 1008 states have return successors, (1852), 1776 states have call predecessors, (1852), 1852 states have call successors, (1852) [2025-03-03 14:46:22,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10657 states to 10657 states and 13757 transitions. [2025-03-03 14:46:22,496 INFO L78 Accepts]: Start accepts. Automaton has 10657 states and 13757 transitions. Word has length 156 [2025-03-03 14:46:22,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:22,497 INFO L471 AbstractCegarLoop]: Abstraction has 10657 states and 13757 transitions. [2025-03-03 14:46:22,497 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 28 states, 28 states have (on average 7.785714285714286) internal successors, (218), 24 states have internal predecessors, (218), 7 states have call successors, (32), 4 states have call predecessors, (32), 8 states have return successors, (34), 10 states have call predecessors, (34), 7 states have call successors, (34) [2025-03-03 14:46:22,497 INFO L276 IsEmpty]: Start isEmpty. Operand 10657 states and 13757 transitions. [2025-03-03 14:46:22,508 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 166 [2025-03-03 14:46:22,508 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:22,508 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:22,517 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2025-03-03 14:46:22,709 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:22,709 INFO L396 AbstractCegarLoop]: === Iteration 31 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:22,710 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:22,710 INFO L85 PathProgramCache]: Analyzing trace with hash -1283120114, now seen corresponding path program 1 times [2025-03-03 14:46:22,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:22,710 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982954945] [2025-03-03 14:46:22,710 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:22,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:22,726 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 165 statements into 1 equivalence classes. [2025-03-03 14:46:22,749 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 165 of 165 statements. [2025-03-03 14:46:22,750 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:22,750 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:23,318 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 23 proven. 9 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2025-03-03 14:46:23,318 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:23,318 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982954945] [2025-03-03 14:46:23,318 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982954945] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:23,318 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1623340442] [2025-03-03 14:46:23,318 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:23,318 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:23,319 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:23,320 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:23,322 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2025-03-03 14:46:23,429 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 165 statements into 1 equivalence classes. [2025-03-03 14:46:23,499 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 165 of 165 statements. [2025-03-03 14:46:23,499 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:23,499 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:23,503 INFO L256 TraceCheckSpWp]: Trace formula consists of 783 conjuncts, 11 conjuncts are in the unsatisfiable core [2025-03-03 14:46:23,506 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:23,597 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 50 proven. 4 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2025-03-03 14:46:23,598 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-03 14:46:23,685 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 27 proven. 2 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2025-03-03 14:46:23,685 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1623340442] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-03 14:46:23,686 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-03 14:46:23,686 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 7, 7] total 15 [2025-03-03 14:46:23,686 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [27521960] [2025-03-03 14:46:23,686 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-03 14:46:23,686 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2025-03-03 14:46:23,686 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:23,687 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2025-03-03 14:46:23,687 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=180, Unknown=0, NotChecked=0, Total=210 [2025-03-03 14:46:23,687 INFO L87 Difference]: Start difference. First operand 10657 states and 13757 transitions. Second operand has 15 states, 15 states have (on average 13.133333333333333) internal successors, (197), 14 states have internal predecessors, (197), 6 states have call successors, (37), 4 states have call predecessors, (37), 6 states have return successors, (37), 7 states have call predecessors, (37), 6 states have call successors, (37) [2025-03-03 14:46:26,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:26,590 INFO L93 Difference]: Finished difference Result 22053 states and 28456 transitions. [2025-03-03 14:46:26,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2025-03-03 14:46:26,591 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 13.133333333333333) internal successors, (197), 14 states have internal predecessors, (197), 6 states have call successors, (37), 4 states have call predecessors, (37), 6 states have return successors, (37), 7 states have call predecessors, (37), 6 states have call successors, (37) Word has length 165 [2025-03-03 14:46:26,591 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:26,643 INFO L225 Difference]: With dead ends: 22053 [2025-03-03 14:46:26,643 INFO L226 Difference]: Without dead ends: 11604 [2025-03-03 14:46:26,663 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 374 GetRequests, 336 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 318 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=249, Invalid=1311, Unknown=0, NotChecked=0, Total=1560 [2025-03-03 14:46:26,664 INFO L435 NwaCegarLoop]: 356 mSDtfsCounter, 1279 mSDsluCounter, 2741 mSDsCounter, 0 mSdLazyCounter, 885 mSolverCounterSat, 489 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1279 SdHoareTripleChecker+Valid, 3097 SdHoareTripleChecker+Invalid, 1374 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 489 IncrementalHoareTripleChecker+Valid, 885 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:26,664 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1279 Valid, 3097 Invalid, 1374 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [489 Valid, 885 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2025-03-03 14:46:26,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11604 states. [2025-03-03 14:46:28,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11604 to 11305. [2025-03-03 14:46:28,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11305 states, 8274 states have (on average 1.2887357988880832) internal successors, (10663), 8355 states have internal predecessors, (10663), 1960 states have call successors, (1960), 1070 states have call predecessors, (1960), 1070 states have return successors, (1960), 1879 states have call predecessors, (1960), 1960 states have call successors, (1960) [2025-03-03 14:46:28,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11305 states to 11305 states and 14583 transitions. [2025-03-03 14:46:28,378 INFO L78 Accepts]: Start accepts. Automaton has 11305 states and 14583 transitions. Word has length 165 [2025-03-03 14:46:28,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:28,379 INFO L471 AbstractCegarLoop]: Abstraction has 11305 states and 14583 transitions. [2025-03-03 14:46:28,379 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 13.133333333333333) internal successors, (197), 14 states have internal predecessors, (197), 6 states have call successors, (37), 4 states have call predecessors, (37), 6 states have return successors, (37), 7 states have call predecessors, (37), 6 states have call successors, (37) [2025-03-03 14:46:28,379 INFO L276 IsEmpty]: Start isEmpty. Operand 11305 states and 14583 transitions. [2025-03-03 14:46:28,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2025-03-03 14:46:28,392 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:28,392 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:28,400 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2025-03-03 14:46:28,592 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:28,593 INFO L396 AbstractCegarLoop]: === Iteration 32 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:28,594 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:28,594 INFO L85 PathProgramCache]: Analyzing trace with hash 1940933587, now seen corresponding path program 1 times [2025-03-03 14:46:28,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:28,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798596091] [2025-03-03 14:46:28,594 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:28,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:28,612 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 173 statements into 1 equivalence classes. [2025-03-03 14:46:28,650 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 173 of 173 statements. [2025-03-03 14:46:28,650 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:28,650 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:29,100 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 23 proven. 6 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2025-03-03 14:46:29,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:29,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798596091] [2025-03-03 14:46:29,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1798596091] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:29,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1831486029] [2025-03-03 14:46:29,101 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:29,101 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:29,101 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:29,103 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:29,104 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2025-03-03 14:46:29,210 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 173 statements into 1 equivalence classes. [2025-03-03 14:46:29,270 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 173 of 173 statements. [2025-03-03 14:46:29,271 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:29,271 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:29,274 INFO L256 TraceCheckSpWp]: Trace formula consists of 817 conjuncts, 30 conjuncts are in the unsatisfiable core [2025-03-03 14:46:29,277 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:29,593 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 76 proven. 10 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2025-03-03 14:46:29,593 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-03 14:46:29,945 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 23 proven. 6 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2025-03-03 14:46:29,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1831486029] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-03 14:46:29,945 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-03 14:46:29,945 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 12, 9] total 22 [2025-03-03 14:46:29,945 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1220324315] [2025-03-03 14:46:29,945 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-03 14:46:29,946 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 22 states [2025-03-03 14:46:29,946 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:29,947 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-03-03 14:46:29,947 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=370, Unknown=0, NotChecked=0, Total=462 [2025-03-03 14:46:29,948 INFO L87 Difference]: Start difference. First operand 11305 states and 14583 transitions. Second operand has 22 states, 22 states have (on average 10.318181818181818) internal successors, (227), 22 states have internal predecessors, (227), 8 states have call successors, (35), 5 states have call predecessors, (35), 6 states have return successors, (34), 8 states have call predecessors, (34), 8 states have call successors, (34) [2025-03-03 14:46:32,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:32,888 INFO L93 Difference]: Finished difference Result 24835 states and 32155 transitions. [2025-03-03 14:46:32,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2025-03-03 14:46:32,889 INFO L78 Accepts]: Start accepts. Automaton has has 22 states, 22 states have (on average 10.318181818181818) internal successors, (227), 22 states have internal predecessors, (227), 8 states have call successors, (35), 5 states have call predecessors, (35), 6 states have return successors, (34), 8 states have call predecessors, (34), 8 states have call successors, (34) Word has length 173 [2025-03-03 14:46:32,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:32,954 INFO L225 Difference]: With dead ends: 24835 [2025-03-03 14:46:32,954 INFO L226 Difference]: Without dead ends: 15471 [2025-03-03 14:46:32,973 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 377 GetRequests, 337 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 451 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=314, Invalid=1408, Unknown=0, NotChecked=0, Total=1722 [2025-03-03 14:46:32,973 INFO L435 NwaCegarLoop]: 345 mSDtfsCounter, 1030 mSDsluCounter, 2141 mSDsCounter, 0 mSdLazyCounter, 1461 mSolverCounterSat, 189 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1030 SdHoareTripleChecker+Valid, 2486 SdHoareTripleChecker+Invalid, 1650 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 189 IncrementalHoareTripleChecker+Valid, 1461 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:32,974 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1030 Valid, 2486 Invalid, 1650 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [189 Valid, 1461 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2025-03-03 14:46:32,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15471 states. [2025-03-03 14:46:34,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15471 to 14703. [2025-03-03 14:46:34,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14703 states, 10742 states have (on average 1.2926829268292683) internal successors, (13886), 10851 states have internal predecessors, (13886), 2565 states have call successors, (2565), 1395 states have call predecessors, (2565), 1395 states have return successors, (2565), 2456 states have call predecessors, (2565), 2565 states have call successors, (2565) [2025-03-03 14:46:34,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14703 states to 14703 states and 19016 transitions. [2025-03-03 14:46:34,899 INFO L78 Accepts]: Start accepts. Automaton has 14703 states and 19016 transitions. Word has length 173 [2025-03-03 14:46:34,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:34,900 INFO L471 AbstractCegarLoop]: Abstraction has 14703 states and 19016 transitions. [2025-03-03 14:46:34,900 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 22 states, 22 states have (on average 10.318181818181818) internal successors, (227), 22 states have internal predecessors, (227), 8 states have call successors, (35), 5 states have call predecessors, (35), 6 states have return successors, (34), 8 states have call predecessors, (34), 8 states have call successors, (34) [2025-03-03 14:46:34,900 INFO L276 IsEmpty]: Start isEmpty. Operand 14703 states and 19016 transitions. [2025-03-03 14:46:34,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2025-03-03 14:46:34,908 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:34,909 INFO L218 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:34,916 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2025-03-03 14:46:35,109 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:35,109 INFO L396 AbstractCegarLoop]: === Iteration 33 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:35,110 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:35,110 INFO L85 PathProgramCache]: Analyzing trace with hash 1613640849, now seen corresponding path program 1 times [2025-03-03 14:46:35,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:35,110 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66219948] [2025-03-03 14:46:35,110 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:35,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:35,122 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 173 statements into 1 equivalence classes. [2025-03-03 14:46:35,145 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 173 of 173 statements. [2025-03-03 14:46:35,145 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:35,145 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:35,562 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 31 proven. 6 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2025-03-03 14:46:35,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-03 14:46:35,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [66219948] [2025-03-03 14:46:35,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [66219948] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-03 14:46:35,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1872462246] [2025-03-03 14:46:35,562 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:35,562 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-03 14:46:35,563 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-03 14:46:35,565 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-03 14:46:35,566 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2025-03-03 14:46:35,690 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 173 statements into 1 equivalence classes. [2025-03-03 14:46:35,757 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 173 of 173 statements. [2025-03-03 14:46:35,757 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:35,757 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-03 14:46:35,761 INFO L256 TraceCheckSpWp]: Trace formula consists of 816 conjuncts, 40 conjuncts are in the unsatisfiable core [2025-03-03 14:46:35,764 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-03 14:46:36,082 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 74 proven. 14 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2025-03-03 14:46:36,082 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-03 14:46:36,582 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 25 proven. 6 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2025-03-03 14:46:36,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1872462246] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-03 14:46:36,582 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-03 14:46:36,582 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 13, 10] total 28 [2025-03-03 14:46:36,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054334381] [2025-03-03 14:46:36,582 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-03 14:46:36,582 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 28 states [2025-03-03 14:46:36,583 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-03 14:46:36,583 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2025-03-03 14:46:36,583 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=654, Unknown=0, NotChecked=0, Total=756 [2025-03-03 14:46:36,583 INFO L87 Difference]: Start difference. First operand 14703 states and 19016 transitions. Second operand has 28 states, 28 states have (on average 9.035714285714286) internal successors, (253), 26 states have internal predecessors, (253), 8 states have call successors, (42), 5 states have call predecessors, (42), 7 states have return successors, (41), 10 states have call predecessors, (41), 8 states have call successors, (41) [2025-03-03 14:46:42,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-03 14:46:42,269 INFO L93 Difference]: Finished difference Result 36901 states and 47650 transitions. [2025-03-03 14:46:42,269 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2025-03-03 14:46:42,269 INFO L78 Accepts]: Start accepts. Automaton has has 28 states, 28 states have (on average 9.035714285714286) internal successors, (253), 26 states have internal predecessors, (253), 8 states have call successors, (42), 5 states have call predecessors, (42), 7 states have return successors, (41), 10 states have call predecessors, (41), 8 states have call successors, (41) Word has length 173 [2025-03-03 14:46:42,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2025-03-03 14:46:42,348 INFO L225 Difference]: With dead ends: 36901 [2025-03-03 14:46:42,348 INFO L226 Difference]: Without dead ends: 22278 [2025-03-03 14:46:42,373 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 392 GetRequests, 338 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 656 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=471, Invalid=2609, Unknown=0, NotChecked=0, Total=3080 [2025-03-03 14:46:42,373 INFO L435 NwaCegarLoop]: 652 mSDtfsCounter, 1061 mSDsluCounter, 8211 mSDsCounter, 0 mSdLazyCounter, 3841 mSolverCounterSat, 317 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1065 SdHoareTripleChecker+Valid, 8863 SdHoareTripleChecker+Invalid, 4158 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 317 IncrementalHoareTripleChecker+Valid, 3841 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.7s IncrementalHoareTripleChecker+Time [2025-03-03 14:46:42,373 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1065 Valid, 8863 Invalid, 4158 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [317 Valid, 3841 Invalid, 0 Unknown, 0 Unchecked, 1.7s Time] [2025-03-03 14:46:42,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22278 states. [2025-03-03 14:46:44,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22278 to 18174. [2025-03-03 14:46:44,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18174 states, 13229 states have (on average 1.289742232973014) internal successors, (17062), 13374 states have internal predecessors, (17062), 3197 states have call successors, (3197), 1747 states have call predecessors, (3197), 1747 states have return successors, (3197), 3052 states have call predecessors, (3197), 3197 states have call successors, (3197) [2025-03-03 14:46:44,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18174 states to 18174 states and 23456 transitions. [2025-03-03 14:46:44,791 INFO L78 Accepts]: Start accepts. Automaton has 18174 states and 23456 transitions. Word has length 173 [2025-03-03 14:46:44,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2025-03-03 14:46:44,792 INFO L471 AbstractCegarLoop]: Abstraction has 18174 states and 23456 transitions. [2025-03-03 14:46:44,792 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 28 states, 28 states have (on average 9.035714285714286) internal successors, (253), 26 states have internal predecessors, (253), 8 states have call successors, (42), 5 states have call predecessors, (42), 7 states have return successors, (41), 10 states have call predecessors, (41), 8 states have call successors, (41) [2025-03-03 14:46:44,792 INFO L276 IsEmpty]: Start isEmpty. Operand 18174 states and 23456 transitions. [2025-03-03 14:46:44,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2025-03-03 14:46:44,800 INFO L210 NwaCegarLoop]: Found error trace [2025-03-03 14:46:44,800 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:44,808 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2025-03-03 14:46:45,000 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable32 [2025-03-03 14:46:45,001 INFO L396 AbstractCegarLoop]: === Iteration 34 === Targeting assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2025-03-03 14:46:45,001 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-03 14:46:45,001 INFO L85 PathProgramCache]: Analyzing trace with hash 1703119505, now seen corresponding path program 1 times [2025-03-03 14:46:45,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-03 14:46:45,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920612482] [2025-03-03 14:46:45,001 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-03 14:46:45,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-03 14:46:45,013 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 181 statements into 1 equivalence classes. [2025-03-03 14:46:45,102 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 181 of 181 statements. [2025-03-03 14:46:45,102 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:45,102 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-03 14:46:45,102 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-03 14:46:45,109 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 181 statements into 1 equivalence classes. [2025-03-03 14:46:45,201 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 181 of 181 statements. [2025-03-03 14:46:45,201 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-03 14:46:45,201 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-03 14:46:45,267 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-03 14:46:45,267 INFO L340 BasicCegarLoop]: Counterexample is feasible [2025-03-03 14:46:45,268 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location assertErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2025-03-03 14:46:45,269 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable33 [2025-03-03 14:46:45,272 INFO L422 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-03 14:46:45,415 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2025-03-03 14:46:45,420 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.03 02:46:45 BoogieIcfgContainer [2025-03-03 14:46:45,420 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2025-03-03 14:46:45,421 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-03 14:46:45,421 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-03 14:46:45,421 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-03 14:46:45,421 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 03.03 02:45:51" (3/4) ... [2025-03-03 14:46:45,422 INFO L140 WitnessPrinter]: Generating witness for reachability counterexample [2025-03-03 14:46:45,636 INFO L127 tionWitnessGenerator]: Generated YAML witness of length 144. [2025-03-03 14:46:45,732 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-03 14:46:45,739 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.yml [2025-03-03 14:46:45,739 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-03 14:46:45,739 INFO L158 Benchmark]: Toolchain (without parser) took 55341.57ms. Allocated memory was 142.6MB in the beginning and 3.5GB in the end (delta: 3.4GB). Free memory was 105.2MB in the beginning and 3.3GB in the end (delta: -3.2GB). Peak memory consumption was 2.2GB. Max. memory is 16.1GB. [2025-03-03 14:46:45,740 INFO L158 Benchmark]: CDTParser took 0.15ms. Allocated memory is still 201.3MB. Free memory is still 126.7MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-03 14:46:45,740 INFO L158 Benchmark]: CACSL2BoogieTranslator took 328.27ms. Allocated memory is still 142.6MB. Free memory was 105.2MB in the beginning and 87.0MB in the end (delta: 18.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-03 14:46:45,740 INFO L158 Benchmark]: Boogie Procedure Inliner took 64.12ms. Allocated memory is still 142.6MB. Free memory was 87.0MB in the beginning and 84.4MB in the end (delta: 2.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-03 14:46:45,740 INFO L158 Benchmark]: Boogie Preprocessor took 57.54ms. Allocated memory is still 142.6MB. Free memory was 84.4MB in the beginning and 81.0MB in the end (delta: 3.4MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-03 14:46:45,740 INFO L158 Benchmark]: IcfgBuilder took 595.03ms. Allocated memory is still 142.6MB. Free memory was 81.0MB in the beginning and 40.2MB in the end (delta: 40.8MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2025-03-03 14:46:45,740 INFO L158 Benchmark]: TraceAbstraction took 53973.07ms. Allocated memory was 142.6MB in the beginning and 3.5GB in the end (delta: 3.4GB). Free memory was 39.1MB in the beginning and 1.3GB in the end (delta: -1.3GB). Peak memory consumption was 2.1GB. Max. memory is 16.1GB. [2025-03-03 14:46:45,740 INFO L158 Benchmark]: Witness Printer took 318.31ms. Allocated memory is still 3.5GB. Free memory was 1.3GB in the beginning and 3.3GB in the end (delta: -2.0GB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2025-03-03 14:46:45,741 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15ms. Allocated memory is still 201.3MB. Free memory is still 126.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 328.27ms. Allocated memory is still 142.6MB. Free memory was 105.2MB in the beginning and 87.0MB in the end (delta: 18.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 64.12ms. Allocated memory is still 142.6MB. Free memory was 87.0MB in the beginning and 84.4MB in the end (delta: 2.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 57.54ms. Allocated memory is still 142.6MB. Free memory was 84.4MB in the beginning and 81.0MB in the end (delta: 3.4MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 595.03ms. Allocated memory is still 142.6MB. Free memory was 81.0MB in the beginning and 40.2MB in the end (delta: 40.8MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * TraceAbstraction took 53973.07ms. Allocated memory was 142.6MB in the beginning and 3.5GB in the end (delta: 3.4GB). Free memory was 39.1MB in the beginning and 1.3GB in the end (delta: -1.3GB). Peak memory consumption was 2.1GB. Max. memory is 16.1GB. * Witness Printer took 318.31ms. Allocated memory is still 3.5GB. Free memory was 1.3GB in the beginning and 3.3GB in the end (delta: -2.0GB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 610]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L24] msg_t nomsg = (msg_t )-1; [L25] port_t cs1 ; [L26] int8_t cs1_old ; [L27] int8_t cs1_new ; [L28] port_t cs2 ; [L29] int8_t cs2_old ; [L30] int8_t cs2_new ; [L31] port_t s1s2 ; [L32] int8_t s1s2_old ; [L33] int8_t s1s2_new ; [L34] port_t s1s1 ; [L35] int8_t s1s1_old ; [L36] int8_t s1s1_new ; [L37] port_t s2s1 ; [L38] int8_t s2s1_old ; [L39] int8_t s2s1_new ; [L40] port_t s2s2 ; [L41] int8_t s2s2_old ; [L42] int8_t s2s2_new ; [L43] port_t s1p ; [L44] int8_t s1p_old ; [L45] int8_t s1p_new ; [L46] port_t s2p ; [L47] int8_t s2p_old ; [L48] int8_t s2p_new ; [L51] _Bool side1Failed ; [L52] _Bool side2Failed ; [L53] msg_t side1_written ; [L54] msg_t side2_written ; [L60] static _Bool side1Failed_History_0 ; [L61] static _Bool side1Failed_History_1 ; [L62] static _Bool side1Failed_History_2 ; [L63] static _Bool side2Failed_History_0 ; [L64] static _Bool side2Failed_History_1 ; [L65] static _Bool side2Failed_History_2 ; [L66] static int8_t active_side_History_0 ; [L67] static int8_t active_side_History_1 ; [L68] static int8_t active_side_History_2 ; [L69] static msg_t manual_selection_History_0 ; [L70] static msg_t manual_selection_History_1 ; [L71] static msg_t manual_selection_History_2 ; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=0, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L534] int c1 ; [L535] int i2 ; [L538] c1 = 0 [L539] side1Failed = __VERIFIER_nondet_bool() [L540] side2Failed = __VERIFIER_nondet_bool() [L541] side1_written = __VERIFIER_nondet_char() [L542] side2_written = __VERIFIER_nondet_char() [L543] side1Failed_History_0 = __VERIFIER_nondet_bool() [L544] side1Failed_History_1 = __VERIFIER_nondet_bool() [L545] side1Failed_History_2 = __VERIFIER_nondet_bool() [L546] side2Failed_History_0 = __VERIFIER_nondet_bool() [L547] side2Failed_History_1 = __VERIFIER_nondet_bool() [L548] side2Failed_History_2 = __VERIFIER_nondet_bool() [L549] active_side_History_0 = __VERIFIER_nondet_char() [L550] active_side_History_1 = __VERIFIER_nondet_char() [L551] active_side_History_2 = __VERIFIER_nondet_char() [L552] manual_selection_History_0 = __VERIFIER_nondet_char() [L553] manual_selection_History_1 = __VERIFIER_nondet_char() [L554] manual_selection_History_2 = __VERIFIER_nondet_char() [L555] CALL, EXPR init() [L197] COND FALSE !((int )side1Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L200] COND FALSE !((int )side2Failed_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L203] COND FALSE !((int )active_side_History_0 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L206] COND FALSE !((int )manual_selection_History_0 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L209] COND FALSE !((int )side1Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L212] COND FALSE !((int )side2Failed_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L215] COND FALSE !((int )active_side_History_1 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L218] COND FALSE !((int )manual_selection_History_1 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L221] COND FALSE !((int )side1Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L224] COND FALSE !((int )side2Failed_History_2 != 0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L227] COND FALSE !((int )active_side_History_2 != -2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L230] COND FALSE !((int )manual_selection_History_2 != 0) [L233] return (1); VAL [\result=1, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L555] RET, EXPR init() [L555] i2 = init() [L556] CALL assume_abort_if_not(i2) VAL [\old(cond)=1, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L58] COND FALSE !(!cond) VAL [\old(cond)=1, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L556] RET assume_abort_if_not(i2) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=0, cs1_old=0, cs2=0, cs2_new=0, cs2_old=0, i2=1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=0, s1s1=0, s1s1_new=0, s1s1_old=0, s1s2=0, s1s2_new=0, s1s2_old=0, s2p=0, s2p_new=0, s2p_old=0, s2s1=0, s2s1_new=0, s2s1_old=0, s2s2=0, s2s2_new=0, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L557] cs1_old = nomsg [L558] cs1_new = nomsg [L559] cs2_old = nomsg [L560] cs2_new = nomsg [L561] s1s2_old = nomsg [L562] s1s2_new = nomsg [L563] s1s1_old = nomsg [L564] s1s1_new = nomsg [L565] s2s1_old = nomsg [L566] s2s1_new = nomsg [L567] s2s2_old = nomsg [L568] s2s2_new = nomsg [L569] s1p_old = nomsg [L570] s1p_new = nomsg [L571] s2p_old = nomsg [L572] s2p_new = nomsg [L573] i2 = 0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, i2=1, manual_selection_History_0=0, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L574] COND TRUE 1 [L576] CALL Console_task_each_pals_period() [L251] msg_t manual_selection ; [L252] char tmp ; [L255] tmp = __VERIFIER_nondet_char() [L256] manual_selection = tmp [L257] CALL write_manual_selection_history(manual_selection) [L167] manual_selection_History_2 = manual_selection_History_1 [L168] manual_selection_History_1 = manual_selection_History_0 [L169] manual_selection_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=-1, cs2=0, cs2_new=-1, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L257] RET write_manual_selection_history(manual_selection) [L258] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L259] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L260] manual_selection = (msg_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L576] RET Console_task_each_pals_period() [L577] CALL Side1_activestandby_task_each_pals_period() [L266] int8_t side1 ; [L267] int8_t side2 ; [L268] msg_t manual_selection ; [L269] int8_t next_state ; [L272] side1 = nomsg [L273] side2 = nomsg [L274] manual_selection = (msg_t )0 [L275] side1Failed = __VERIFIER_nondet_bool() [L276] CALL write_side1_failed_history(side1Failed) [L77] side1Failed_History_2 = side1Failed_History_1 [L78] side1Failed_History_1 = side1Failed_History_0 [L79] side1Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L276] RET write_side1_failed_history(side1Failed) [L277] COND TRUE \read(side1Failed) [L278] s1s1_new = nomsg != nomsg && s1s1_new == nomsg ? nomsg : s1s1_new [L279] s1s2_new = nomsg != nomsg && s1s2_new == nomsg ? nomsg : s1s2_new [L280] s1p_new = nomsg != nomsg && s1p_new == nomsg ? nomsg : s1p_new [L281] side1_written = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=1, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L577] RET Side1_activestandby_task_each_pals_period() [L578] CALL Side2_activestandby_task_each_pals_period() [L323] int8_t side1 ; [L324] int8_t side2 ; [L325] msg_t manual_selection ; [L326] int8_t next_state ; [L329] side1 = nomsg [L330] side2 = nomsg [L331] manual_selection = (msg_t )0 [L332] side2Failed = __VERIFIER_nondet_bool() [L333] CALL write_side2_failed_history(side2Failed) [L107] side2Failed_History_2 = side2Failed_History_1 [L108] side2Failed_History_1 = side2Failed_History_0 [L109] side2Failed_History_0 = val VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L333] RET write_side2_failed_history(side2Failed) [L334] COND FALSE !(\read(side2Failed)) [L341] side1 = s1s2_old [L342] s1s2_old = nomsg [L343] side2 = s2s2_old [L344] s2s2_old = nomsg [L345] manual_selection = cs2_old [L346] cs2_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L347] COND TRUE (int )side1 == (int )side2 [L348] next_state = (int8_t )0 VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, next_state=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L371] s2s1_new = next_state != nomsg && s2s1_new == nomsg ? next_state : s2s1_new [L372] s2s2_new = next_state != nomsg && s2s2_new == nomsg ? next_state : s2s2_new [L373] s2p_new = next_state != nomsg && s2p_new == nomsg ? next_state : s2p_new [L374] side2_written = next_state VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L578] RET Side2_activestandby_task_each_pals_period() [L579] CALL Pendulum_prism_task_each_pals_period() [L380] int8_t active_side ; [L381] int8_t tmp ; [L382] int8_t side1 ; [L383] int8_t side2 ; VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [\old(index)=0, \result=-2, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] RET, EXPR read_active_side_history((unsigned char)0) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L386] tmp = read_active_side_history((unsigned char)0) [L387] active_side = tmp [L388] side1 = nomsg [L389] side2 = nomsg [L390] side1 = s1p_old [L391] s1p_old = nomsg [L392] side2 = s2p_old [L393] s2p_old = nomsg VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L394] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L397] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L400] COND FALSE !((int )side1 == 0) [L407] active_side = (int8_t )0 VAL [active_side=0, active_side_History_0=-2, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L409] CALL write_active_side_history(active_side) [L137] active_side_History_2 = active_side_History_1 [L138] active_side_History_1 = active_side_History_0 [L139] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=127, cs1_old=-1, cs2=0, cs2_new=127, cs2_old=-1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=0, s2p_old=-1, s2s1=0, s2s1_new=0, s2s1_old=-1, s2s2=0, s2s2_new=0, s2s2_old=-1, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L409] RET write_active_side_history(active_side) [L579] RET Pendulum_prism_task_each_pals_period() [L580] cs1_old = cs1_new [L581] cs1_new = nomsg [L582] cs2_old = cs2_new [L583] cs2_new = nomsg [L584] s1s2_old = s1s2_new [L585] s1s2_new = nomsg [L586] s1s1_old = s1s1_new [L587] s1s1_new = nomsg [L588] s2s1_old = s2s1_new [L589] s2s1_new = nomsg [L590] s2s2_old = s2s2_new [L591] s2s2_new = nomsg [L592] s1p_old = s1p_new [L593] s1p_new = nomsg [L594] s2p_old = s2p_new [L595] s2p_new = nomsg [L596] CALL, EXPR check() [L415] int tmp ; [L416] msg_t tmp___0 ; [L417] _Bool tmp___1 ; [L418] _Bool tmp___2 ; [L419] _Bool tmp___3 ; [L420] _Bool tmp___4 ; [L421] int8_t tmp___5 ; [L422] _Bool tmp___6 ; [L423] _Bool tmp___7 ; [L424] _Bool tmp___8 ; [L425] int8_t tmp___9 ; [L426] _Bool tmp___10 ; [L427] _Bool tmp___11 ; [L428] _Bool tmp___12 ; [L429] msg_t tmp___13 ; [L430] _Bool tmp___14 ; [L431] _Bool tmp___15 ; [L432] _Bool tmp___16 ; [L433] _Bool tmp___17 ; [L434] int8_t tmp___18 ; [L435] int8_t tmp___19 ; [L436] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L439] COND FALSE !(! side1Failed) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L442] COND TRUE ! side2Failed [L443] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L447] CALL assume_abort_if_not((_Bool )tmp) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L58] COND FALSE !(!cond) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L447] RET assume_abort_if_not((_Bool )tmp) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L448] CALL, EXPR read_manual_selection_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L178] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L181] COND TRUE (int )index == 1 [L182] return (manual_selection_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L448] RET, EXPR read_manual_selection_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L448] tmp___0 = read_manual_selection_history((unsigned char)1) [L449] COND TRUE ! tmp___0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L450] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L450] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L450] tmp___1 = read_side1_failed_history((unsigned char)1) [L451] COND TRUE ! tmp___1 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L452] CALL, EXPR read_side1_failed_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND TRUE (int )index == 0 [L89] return (side1Failed_History_0); VAL [\old(index)=0, \result=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L452] RET, EXPR read_side1_failed_history((unsigned char)0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L452] tmp___2 = read_side1_failed_history((unsigned char)0) [L453] COND FALSE !(! tmp___2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L478] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L478] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L478] tmp___7 = read_side1_failed_history((unsigned char)1) [L479] COND FALSE !(\read(tmp___7)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L494] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L494] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L494] tmp___11 = read_side1_failed_history((unsigned char)1) [L495] COND TRUE ! tmp___11 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L496] CALL, EXPR read_side2_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L118] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L121] COND TRUE (int )index == 1 [L122] return (side2Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L496] RET, EXPR read_side2_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L496] tmp___12 = read_side2_failed_history((unsigned char)1) [L497] COND FALSE !(\read(tmp___12)) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L510] CALL, EXPR read_active_side_history((unsigned char)2) VAL [\old(index)=2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L148] COND FALSE !((int )index == 0) VAL [\old(index)=2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=2, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L151] COND FALSE !((int )index == 1) VAL [\old(index)=2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, index=2, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L154] COND TRUE (int )index == 2 [L155] return (active_side_History_2); VAL [\old(index)=2, \result=-2, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L510] RET, EXPR read_active_side_history((unsigned char)2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L510] tmp___20 = read_active_side_history((unsigned char)2) [L511] COND FALSE !((int )tmp___20 > -2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L529] return (1); VAL [\result=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0, tmp=1] [L596] RET, EXPR check() [L596] c1 = check() [L597] CALL assert(c1) VAL [\old(arg)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L608] COND FALSE !(! arg) VAL [\old(arg)=1, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L597] RET assert(c1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, c1=1, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, i2=1, manual_selection_History_0=127, manual_selection_History_1=0, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L574] COND TRUE 1 [L576] CALL Console_task_each_pals_period() [L251] msg_t manual_selection ; [L252] char tmp ; [L255] tmp = __VERIFIER_nondet_char() [L256] manual_selection = tmp [L257] CALL write_manual_selection_history(manual_selection) [L167] manual_selection_History_2 = manual_selection_History_1 [L168] manual_selection_History_1 = manual_selection_History_0 [L169] manual_selection_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=127, cs2=0, cs2_new=-1, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L257] RET write_manual_selection_history(manual_selection) [L258] cs1_new = manual_selection != nomsg && cs1_new == nomsg ? manual_selection : cs1_new [L259] cs2_new = manual_selection != nomsg && cs2_new == nomsg ? manual_selection : cs2_new [L260] manual_selection = (msg_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=127, cs2=0, cs2_new=4, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=1, side1Failed_History_0=1, side1Failed_History_1=0, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L576] RET Console_task_each_pals_period() [L577] CALL Side1_activestandby_task_each_pals_period() [L266] int8_t side1 ; [L267] int8_t side2 ; [L268] msg_t manual_selection ; [L269] int8_t next_state ; [L272] side1 = nomsg [L273] side2 = nomsg [L274] manual_selection = (msg_t )0 [L275] side1Failed = __VERIFIER_nondet_bool() [L276] CALL write_side1_failed_history(side1Failed) [L77] side1Failed_History_2 = side1Failed_History_1 [L78] side1Failed_History_1 = side1Failed_History_0 [L79] side1Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=127, cs2=0, cs2_new=4, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=0, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L276] RET write_side1_failed_history(side1Failed) [L277] COND FALSE !(\read(side1Failed)) [L284] side1 = s1s1_old [L285] s1s1_old = nomsg [L286] side2 = s2s1_old [L287] s2s1_old = nomsg [L288] manual_selection = cs1_old [L289] cs1_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L290] COND FALSE !((int )side1 == (int )side2) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L293] COND TRUE (int )side1 == (int )nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L294] COND TRUE (int )side2 != (int )nomsg [L295] next_state = (int8_t )0 VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, next_state=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=-1, s1s1=0, s1s1_new=-1, s1s1_old=-1, s1s2=0, s1s2_new=-1, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=-1, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L314] s1s1_new = next_state != nomsg && s1s1_new == nomsg ? next_state : s1s1_new [L315] s1s2_new = next_state != nomsg && s1s2_new == nomsg ? next_state : s1s2_new [L316] s1p_new = next_state != nomsg && s1p_new == nomsg ? next_state : s1p_new [L317] side1_written = next_state VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=0, side2Failed_History_0=0, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L577] RET Side1_activestandby_task_each_pals_period() [L578] CALL Side2_activestandby_task_each_pals_period() [L323] int8_t side1 ; [L324] int8_t side2 ; [L325] msg_t manual_selection ; [L326] int8_t next_state ; [L329] side1 = nomsg [L330] side2 = nomsg [L331] manual_selection = (msg_t )0 [L332] side2Failed = __VERIFIER_nondet_bool() [L333] CALL write_side2_failed_history(side2Failed) [L107] side2Failed_History_2 = side2Failed_History_1 [L108] side2Failed_History_1 = side2Failed_History_0 [L109] side2Failed_History_0 = val VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=0] [L333] RET write_side2_failed_history(side2Failed) [L334] COND TRUE \read(side2Failed) [L335] s2s1_new = nomsg != nomsg && s2s1_new == nomsg ? nomsg : s2s1_new [L336] s2s2_new = nomsg != nomsg && s2s2_new == nomsg ? nomsg : s2s2_new [L337] s2p_new = nomsg != nomsg && s2p_new == nomsg ? nomsg : s2p_new [L338] side2_written = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L578] RET Side2_activestandby_task_each_pals_period() [L579] CALL Pendulum_prism_task_each_pals_period() [L380] int8_t active_side ; [L381] int8_t tmp ; [L382] int8_t side1 ; [L383] int8_t side2 ; VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L386] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [\old(index)=0, \result=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L386] RET, EXPR read_active_side_history((unsigned char)0) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=0, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L386] tmp = read_active_side_history((unsigned char)0) [L387] active_side = tmp [L388] side1 = nomsg [L389] side2 = nomsg [L390] side1 = s1p_old [L391] s1p_old = nomsg [L392] side2 = s2p_old [L393] s2p_old = nomsg VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L394] COND FALSE !((int )side1 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L397] COND FALSE !((int )side2 == 1) VAL [active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L400] COND FALSE !((int )side1 == 0) [L407] active_side = (int8_t )0 VAL [active_side=0, active_side_History_0=0, active_side_History_1=-2, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L409] CALL write_active_side_history(active_side) [L137] active_side_History_2 = active_side_History_1 [L138] active_side_History_1 = active_side_History_0 [L139] active_side_History_0 = val VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=4, cs1_old=-1, cs2=0, cs2_new=4, cs2_old=127, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=0, s1p_old=-1, s1s1=0, s1s1_new=0, s1s1_old=-1, s1s2=0, s1s2_new=0, s1s2_old=-1, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=0, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L409] RET write_active_side_history(active_side) [L579] RET Pendulum_prism_task_each_pals_period() [L580] cs1_old = cs1_new [L581] cs1_new = nomsg [L582] cs2_old = cs2_new [L583] cs2_new = nomsg [L584] s1s2_old = s1s2_new [L585] s1s2_new = nomsg [L586] s1s1_old = s1s1_new [L587] s1s1_new = nomsg [L588] s2s1_old = s2s1_new [L589] s2s1_new = nomsg [L590] s2s2_old = s2s2_new [L591] s2s2_new = nomsg [L592] s1p_old = s1p_new [L593] s1p_new = nomsg [L594] s2p_old = s2p_new [L595] s2p_new = nomsg [L596] CALL, EXPR check() [L415] int tmp ; [L416] msg_t tmp___0 ; [L417] _Bool tmp___1 ; [L418] _Bool tmp___2 ; [L419] _Bool tmp___3 ; [L420] _Bool tmp___4 ; [L421] int8_t tmp___5 ; [L422] _Bool tmp___6 ; [L423] _Bool tmp___7 ; [L424] _Bool tmp___8 ; [L425] int8_t tmp___9 ; [L426] _Bool tmp___10 ; [L427] _Bool tmp___11 ; [L428] _Bool tmp___12 ; [L429] msg_t tmp___13 ; [L430] _Bool tmp___14 ; [L431] _Bool tmp___15 ; [L432] _Bool tmp___16 ; [L433] _Bool tmp___17 ; [L434] int8_t tmp___18 ; [L435] int8_t tmp___19 ; [L436] int8_t tmp___20 ; VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L439] COND TRUE ! side1Failed [L440] tmp = 1 VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L447] CALL assume_abort_if_not((_Bool )tmp) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L58] COND FALSE !(!cond) VAL [\old(cond)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L447] RET assume_abort_if_not((_Bool )tmp) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L448] CALL, EXPR read_manual_selection_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L178] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, index=1, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L181] COND TRUE (int )index == 1 [L182] return (manual_selection_History_1); VAL [\old(index)=1, \result=127, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L448] RET, EXPR read_manual_selection_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L448] tmp___0 = read_manual_selection_history((unsigned char)1) [L449] COND FALSE !(! tmp___0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L478] CALL, EXPR read_side1_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L88] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, index=1, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L91] COND TRUE (int )index == 1 [L92] return (side1Failed_History_1); VAL [\old(index)=1, \result=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L478] RET, EXPR read_side1_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L478] tmp___7 = read_side1_failed_history((unsigned char)1) [L479] COND TRUE \read(tmp___7) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L480] CALL, EXPR read_side2_failed_history((unsigned char)1) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L118] COND FALSE !((int )index == 0) VAL [\old(index)=1, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, index=1, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L121] COND TRUE (int )index == 1 [L122] return (side2Failed_History_1); VAL [\old(index)=1, \result=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L480] RET, EXPR read_side2_failed_history((unsigned char)1) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L480] tmp___8 = read_side2_failed_history((unsigned char)1) [L481] COND TRUE ! tmp___8 VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L482] CALL, EXPR read_active_side_history((unsigned char)0) VAL [\old(index)=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L148] COND TRUE (int )index == 0 [L149] return (active_side_History_0); VAL [\old(index)=0, \result=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L482] RET, EXPR read_active_side_history((unsigned char)0) VAL [active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L482] tmp___5 = read_active_side_history((unsigned char)0) [L483] COND TRUE ! ((int )tmp___5 == 2) [L484] return (0); VAL [\result=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1, tmp=1] [L596] RET, EXPR check() [L596] c1 = check() [L597] CALL assert(c1) VAL [\old(arg)=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L608] COND TRUE ! arg VAL [\old(arg)=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] [L610] reach_error() VAL [\old(arg)=0, active_side_History_0=0, active_side_History_1=0, active_side_History_2=-2, cs1=0, cs1_new=-1, cs1_old=4, cs2=0, cs2_new=-1, cs2_old=4, manual_selection_History_0=4, manual_selection_History_1=127, manual_selection_History_2=0, nomsg=-1, s1p=0, s1p_new=-1, s1p_old=0, s1s1=0, s1s1_new=-1, s1s1_old=0, s1s2=0, s1s2_new=-1, s1s2_old=0, s2p=0, s2p_new=-1, s2p_old=-1, s2s1=0, s2s1_new=-1, s2s1_old=-1, s2s2=0, s2s2_new=-1, s2s2_old=-1, side1Failed=0, side1Failed_History_0=0, side1Failed_History_1=1, side1Failed_History_2=0, side1_written=0, side2Failed=1, side2Failed_History_0=1, side2Failed_History_1=0, side2Failed_History_2=0, side2_written=-1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 8 procedures, 177 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 53.7s, OverallIterations: 34, TraceHistogramMax: 5, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.1s, AutomataDifference: 26.7s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 12255 SdHoareTripleChecker+Valid, 8.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 12200 mSDsluCounter, 61047 SdHoareTripleChecker+Invalid, 7.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 50071 mSDsCounter, 3041 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 16096 IncrementalHoareTripleChecker+Invalid, 19137 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 3041 mSolverCounterUnsat, 10976 mSDtfsCounter, 16096 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 2710 GetRequests, 2257 SyntacticMatches, 0 SemanticMatches, 453 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4537 ImplicationChecksByTransitivity, 5.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=18174occurred in iteration=33, InterpolantAutomatonStates: 368, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 11.5s AutomataMinimizationTime, 33 MinimizatonAttempts, 17410 StatesRemovedByMinimization, 24 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.4s SsaConstructionTime, 1.4s SatisfiabilityAnalysisTime, 10.5s InterpolantComputationTime, 4582 NumberOfCodeBlocks, 4582 NumberOfCodeBlocksAsserted, 42 NumberOfCheckSat, 5328 ConstructedInterpolants, 0 QuantifiedInterpolants, 15524 SizeOfPredicates, 24 NumberOfNonLiveVariables, 5919 ConjunctsInSsa, 225 ConjunctsInUnsatCore, 47 InterpolantComputations, 27 PerfectInterpolantSequences, 1944/2145 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2025-03-03 14:46:45,768 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE