./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8fc3dc66 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe --- Real Ultimate output --- This is Ultimate 0.3.0-?-8fc3dc6-m [2025-03-17 19:55:45,923 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-17 19:55:45,982 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf [2025-03-17 19:55:45,987 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-17 19:55:45,989 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-17 19:55:45,989 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-17 19:55:46,005 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-17 19:55:46,005 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-17 19:55:46,005 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-17 19:55:46,005 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-17 19:55:46,005 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-17 19:55:46,006 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * Use SBE=true [2025-03-17 19:55:46,006 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-17 19:55:46,006 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-17 19:55:46,006 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-17 19:55:46,007 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-17 19:55:46,007 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-17 19:55:46,007 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-17 19:55:46,007 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-17 19:55:46,007 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-17 19:55:46,007 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-17 19:55:46,007 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-17 19:55:46,007 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-17 19:55:46,007 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 68763c9a2179c48c1fc2989bd19031bbd8829c13b9c8eeaf244defd8aef53cfe [2025-03-17 19:55:46,212 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-17 19:55:46,220 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-17 19:55:46,222 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-17 19:55:46,223 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-17 19:55:46,223 INFO L274 PluginConnector]: CDTParser initialized [2025-03-17 19:55:46,225 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2025-03-17 19:55:47,350 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/893b21e10/49cb76a384b9412aa54ccc8bb790c0fa/FLAGfbc8c6296 [2025-03-17 19:55:47,596 INFO L384 CDTParser]: Found 1 translation units. [2025-03-17 19:55:47,601 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/termination-memory-alloca/Urban-2013WST-Fig2-modified1000-alloca.i [2025-03-17 19:55:47,617 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/893b21e10/49cb76a384b9412aa54ccc8bb790c0fa/FLAGfbc8c6296 [2025-03-17 19:55:47,919 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/893b21e10/49cb76a384b9412aa54ccc8bb790c0fa [2025-03-17 19:55:47,920 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-17 19:55:47,921 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-17 19:55:47,923 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-17 19:55:47,923 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-17 19:55:47,926 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-17 19:55:47,926 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 07:55:47" (1/1) ... [2025-03-17 19:55:47,927 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7eefc02b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:47, skipping insertion in model container [2025-03-17 19:55:47,927 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 07:55:47" (1/1) ... [2025-03-17 19:55:47,950 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-17 19:55:48,128 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 19:55:48,136 INFO L200 MainTranslator]: Completed pre-run [2025-03-17 19:55:48,169 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 19:55:48,187 INFO L204 MainTranslator]: Completed translation [2025-03-17 19:55:48,188 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48 WrapperNode [2025-03-17 19:55:48,188 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-17 19:55:48,189 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-17 19:55:48,189 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-17 19:55:48,189 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-17 19:55:48,194 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48" (1/1) ... [2025-03-17 19:55:48,201 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48" (1/1) ... [2025-03-17 19:55:48,215 INFO L138 Inliner]: procedures = 109, calls = 13, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 31 [2025-03-17 19:55:48,216 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-17 19:55:48,217 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-17 19:55:48,217 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-17 19:55:48,217 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-17 19:55:48,221 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48" (1/1) ... [2025-03-17 19:55:48,222 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48" (1/1) ... [2025-03-17 19:55:48,223 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48" (1/1) ... [2025-03-17 19:55:48,232 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [4, 3]. 57 percent of accesses are in the largest equivalence class. The 0 initializations are split as follows [0, 0]. The 3 writes are split as follows [2, 1]. [2025-03-17 19:55:48,232 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48" (1/1) ... [2025-03-17 19:55:48,232 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48" (1/1) ... [2025-03-17 19:55:48,239 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48" (1/1) ... [2025-03-17 19:55:48,240 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48" (1/1) ... [2025-03-17 19:55:48,240 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48" (1/1) ... [2025-03-17 19:55:48,241 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48" (1/1) ... [2025-03-17 19:55:48,241 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-17 19:55:48,244 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-17 19:55:48,244 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-17 19:55:48,244 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-17 19:55:48,245 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48" (1/1) ... [2025-03-17 19:55:48,248 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 19:55:48,258 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:55:48,271 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 19:55:48,278 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-17 19:55:48,294 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-03-17 19:55:48,294 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-03-17 19:55:48,294 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-03-17 19:55:48,294 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-03-17 19:55:48,294 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-03-17 19:55:48,294 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-17 19:55:48,294 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-17 19:55:48,294 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-17 19:55:48,357 INFO L256 CfgBuilder]: Building ICFG [2025-03-17 19:55:48,358 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-17 19:55:48,444 INFO L? ?]: Removed 4 outVars from TransFormulas that were not future-live. [2025-03-17 19:55:48,444 INFO L307 CfgBuilder]: Performing block encoding [2025-03-17 19:55:48,449 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-17 19:55:48,449 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-17 19:55:48,450 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 07:55:48 BoogieIcfgContainer [2025-03-17 19:55:48,450 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-17 19:55:48,450 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-17 19:55:48,450 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-17 19:55:48,456 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-17 19:55:48,457 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 19:55:48,457 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.03 07:55:47" (1/3) ... [2025-03-17 19:55:48,458 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5e0613ee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 07:55:48, skipping insertion in model container [2025-03-17 19:55:48,458 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 19:55:48,458 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:55:48" (2/3) ... [2025-03-17 19:55:48,458 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5e0613ee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 07:55:48, skipping insertion in model container [2025-03-17 19:55:48,458 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 19:55:48,459 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 07:55:48" (3/3) ... [2025-03-17 19:55:48,460 INFO L363 chiAutomizerObserver]: Analyzing ICFG Urban-2013WST-Fig2-modified1000-alloca.i [2025-03-17 19:55:48,503 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-17 19:55:48,503 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-17 19:55:48,503 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-17 19:55:48,503 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-17 19:55:48,504 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-17 19:55:48,504 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-17 19:55:48,504 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-17 19:55:48,504 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-17 19:55:48,508 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:48,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2025-03-17 19:55:48,521 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:55:48,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:55:48,524 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 19:55:48,524 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2025-03-17 19:55:48,524 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-17 19:55:48,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:48,525 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2025-03-17 19:55:48,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:55:48,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:55:48,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 19:55:48,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2025-03-17 19:55:48,531 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-17 19:55:48,531 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !true;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-17 19:55:48,534 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:48,535 INFO L85 PathProgramCache]: Analyzing trace with hash 45, now seen corresponding path program 1 times [2025-03-17 19:55:48,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:48,540 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837468054] [2025-03-17 19:55:48,541 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:55:48,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:48,599 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:55:48,612 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:48,613 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:55:48,613 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:48,613 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:55:48,615 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:55:48,620 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:48,622 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:55:48,622 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:48,631 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:55:48,634 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:48,634 INFO L85 PathProgramCache]: Analyzing trace with hash 1291802, now seen corresponding path program 1 times [2025-03-17 19:55:48,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:48,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079968037] [2025-03-17 19:55:48,635 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:55:48,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:48,643 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-03-17 19:55:48,645 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-03-17 19:55:48,645 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:55:48,645 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:55:48,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:48,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:55:48,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079968037] [2025-03-17 19:55:48,675 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079968037] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 19:55:48,675 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 19:55:48,675 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-17 19:55:48,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717610554] [2025-03-17 19:55:48,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 19:55:48,677 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 19:55:48,678 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:55:48,696 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-17 19:55:48,696 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-17 19:55:48,698 INFO L87 Difference]: Start difference. First operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:48,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:55:48,701 INFO L93 Difference]: Finished difference Result 9 states and 10 transitions. [2025-03-17 19:55:48,702 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9 states and 10 transitions. [2025-03-17 19:55:48,703 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2025-03-17 19:55:48,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9 states to 6 states and 7 transitions. [2025-03-17 19:55:48,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2025-03-17 19:55:48,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2025-03-17 19:55:48,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6 states and 7 transitions. [2025-03-17 19:55:48,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 19:55:48,707 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6 states and 7 transitions. [2025-03-17 19:55:48,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6 states and 7 transitions. [2025-03-17 19:55:48,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6 to 6. [2025-03-17 19:55:48,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.1666666666666667) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:48,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 7 transitions. [2025-03-17 19:55:48,723 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6 states and 7 transitions. [2025-03-17 19:55:48,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-17 19:55:48,726 INFO L432 stractBuchiCegarLoop]: Abstraction has 6 states and 7 transitions. [2025-03-17 19:55:48,726 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-17 19:55:48,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6 states and 7 transitions. [2025-03-17 19:55:48,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2025-03-17 19:55:48,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:55:48,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:55:48,728 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 19:55:48,728 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-03-17 19:55:48,728 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-17 19:55:48,728 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-17 19:55:48,728 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:48,729 INFO L85 PathProgramCache]: Analyzing trace with hash 45, now seen corresponding path program 2 times [2025-03-17 19:55:48,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:48,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [191252024] [2025-03-17 19:55:48,729 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 19:55:48,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:48,737 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:55:48,746 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:48,746 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 19:55:48,746 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:48,746 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:55:48,748 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:55:48,753 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:48,753 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:55:48,753 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:48,754 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:55:48,755 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:48,755 INFO L85 PathProgramCache]: Analyzing trace with hash 40044995, now seen corresponding path program 1 times [2025-03-17 19:55:48,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:48,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979226782] [2025-03-17 19:55:48,755 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:55:48,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:48,761 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-03-17 19:55:48,766 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-03-17 19:55:48,766 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:55:48,766 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:55:48,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:48,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:55:48,868 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979226782] [2025-03-17 19:55:48,868 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [979226782] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 19:55:48,868 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 19:55:48,868 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-17 19:55:48,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203482575] [2025-03-17 19:55:48,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 19:55:48,869 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 19:55:48,869 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:55:48,869 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 19:55:48,869 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-17 19:55:48,870 INFO L87 Difference]: Start difference. First operand 6 states and 7 transitions. cyclomatic complexity: 2 Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:48,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:55:48,899 INFO L93 Difference]: Finished difference Result 8 states and 9 transitions. [2025-03-17 19:55:48,899 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8 states and 9 transitions. [2025-03-17 19:55:48,899 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2025-03-17 19:55:48,900 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8 states to 8 states and 9 transitions. [2025-03-17 19:55:48,900 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2025-03-17 19:55:48,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2025-03-17 19:55:48,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8 states and 9 transitions. [2025-03-17 19:55:48,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 19:55:48,900 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8 states and 9 transitions. [2025-03-17 19:55:48,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8 states and 9 transitions. [2025-03-17 19:55:48,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8 to 8. [2025-03-17 19:55:48,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 1.125) internal successors, (9), 7 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:48,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 9 transitions. [2025-03-17 19:55:48,901 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8 states and 9 transitions. [2025-03-17 19:55:48,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 19:55:48,902 INFO L432 stractBuchiCegarLoop]: Abstraction has 8 states and 9 transitions. [2025-03-17 19:55:48,902 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-17 19:55:48,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states and 9 transitions. [2025-03-17 19:55:48,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2025-03-17 19:55:48,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:55:48,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:55:48,902 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 19:55:48,903 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1] [2025-03-17 19:55:48,903 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-17 19:55:48,903 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-17 19:55:48,903 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:48,903 INFO L85 PathProgramCache]: Analyzing trace with hash 45, now seen corresponding path program 3 times [2025-03-17 19:55:48,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:48,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735229502] [2025-03-17 19:55:48,903 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 19:55:48,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:48,909 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:55:48,913 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:48,913 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 19:55:48,913 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:48,913 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:55:48,914 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:55:48,917 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:48,920 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:55:48,920 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:48,921 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:55:48,923 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:48,923 INFO L85 PathProgramCache]: Analyzing trace with hash -171430748, now seen corresponding path program 1 times [2025-03-17 19:55:48,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:48,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162665499] [2025-03-17 19:55:48,923 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:55:48,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:48,929 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-03-17 19:55:48,933 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-03-17 19:55:48,933 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:55:48,933 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:55:49,102 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:49,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:55:49,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162665499] [2025-03-17 19:55:49,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162665499] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:55:49,103 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1782285665] [2025-03-17 19:55:49,103 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:55:49,103 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:55:49,103 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:55:49,105 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:55:49,107 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2025-03-17 19:55:49,137 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-03-17 19:55:49,144 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-03-17 19:55:49,144 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:55:49,145 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:55:49,146 INFO L256 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 6 conjuncts are in the unsatisfiable core [2025-03-17 19:55:49,147 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:55:49,172 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-03-17 19:55:49,188 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:49,204 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:49,204 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:55:49,238 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:49,238 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1782285665] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:55:49,238 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:55:49,238 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5] total 10 [2025-03-17 19:55:49,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1603027797] [2025-03-17 19:55:49,238 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:55:49,238 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 19:55:49,238 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:55:49,239 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-17 19:55:49,239 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2025-03-17 19:55:49,239 INFO L87 Difference]: Start difference. First operand 8 states and 9 transitions. cyclomatic complexity: 2 Second operand has 10 states, 10 states have (on average 1.5) internal successors, (15), 10 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:49,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:55:49,297 INFO L93 Difference]: Finished difference Result 14 states and 15 transitions. [2025-03-17 19:55:49,297 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 15 transitions. [2025-03-17 19:55:49,297 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2025-03-17 19:55:49,297 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 15 transitions. [2025-03-17 19:55:49,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2025-03-17 19:55:49,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2025-03-17 19:55:49,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 15 transitions. [2025-03-17 19:55:49,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 19:55:49,298 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 15 transitions. [2025-03-17 19:55:49,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 15 transitions. [2025-03-17 19:55:49,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2025-03-17 19:55:49,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.0714285714285714) internal successors, (15), 13 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:49,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 15 transitions. [2025-03-17 19:55:49,298 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14 states and 15 transitions. [2025-03-17 19:55:49,300 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 19:55:49,300 INFO L432 stractBuchiCegarLoop]: Abstraction has 14 states and 15 transitions. [2025-03-17 19:55:49,300 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-17 19:55:49,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 15 transitions. [2025-03-17 19:55:49,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2025-03-17 19:55:49,301 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:55:49,301 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:55:49,301 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 19:55:49,301 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [5, 4, 1, 1, 1, 1] [2025-03-17 19:55:49,301 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-17 19:55:49,301 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-17 19:55:49,301 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:49,301 INFO L85 PathProgramCache]: Analyzing trace with hash 45, now seen corresponding path program 4 times [2025-03-17 19:55:49,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:49,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487635018] [2025-03-17 19:55:49,302 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 19:55:49,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:49,321 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-03-17 19:55:49,322 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:49,322 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 19:55:49,325 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:49,325 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:55:49,326 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:55:49,327 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:49,327 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:55:49,327 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:49,328 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:55:49,331 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:49,332 INFO L85 PathProgramCache]: Analyzing trace with hash 1857330119, now seen corresponding path program 2 times [2025-03-17 19:55:49,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:49,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1818810764] [2025-03-17 19:55:49,332 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 19:55:49,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:49,341 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 13 statements into 2 equivalence classes. [2025-03-17 19:55:49,346 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 13 of 13 statements. [2025-03-17 19:55:49,346 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-17 19:55:49,346 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:55:49,648 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:49,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:55:49,648 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1818810764] [2025-03-17 19:55:49,648 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1818810764] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:55:49,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [734426031] [2025-03-17 19:55:49,649 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 19:55:49,649 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:55:49,649 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:55:49,651 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:55:49,653 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2025-03-17 19:55:49,684 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 13 statements into 2 equivalence classes. [2025-03-17 19:55:49,702 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 13 of 13 statements. [2025-03-17 19:55:49,702 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-17 19:55:49,702 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:55:49,703 INFO L256 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 12 conjuncts are in the unsatisfiable core [2025-03-17 19:55:49,705 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:55:49,711 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-03-17 19:55:49,720 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:49,753 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:49,769 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:49,787 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:49,804 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:49,805 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:55:49,898 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:49,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [734426031] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:55:49,899 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:55:49,899 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 8] total 22 [2025-03-17 19:55:49,899 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [297887907] [2025-03-17 19:55:49,899 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:55:49,899 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 19:55:49,899 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:55:49,900 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-03-17 19:55:49,901 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=297, Unknown=0, NotChecked=0, Total=462 [2025-03-17 19:55:49,901 INFO L87 Difference]: Start difference. First operand 14 states and 15 transitions. cyclomatic complexity: 2 Second operand has 22 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:50,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:55:50,075 INFO L93 Difference]: Finished difference Result 26 states and 27 transitions. [2025-03-17 19:55:50,075 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 27 transitions. [2025-03-17 19:55:50,076 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2025-03-17 19:55:50,076 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 26 states and 27 transitions. [2025-03-17 19:55:50,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26 [2025-03-17 19:55:50,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26 [2025-03-17 19:55:50,076 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26 states and 27 transitions. [2025-03-17 19:55:50,076 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 19:55:50,076 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26 states and 27 transitions. [2025-03-17 19:55:50,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states and 27 transitions. [2025-03-17 19:55:50,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2025-03-17 19:55:50,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.0384615384615385) internal successors, (27), 25 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:50,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 27 transitions. [2025-03-17 19:55:50,078 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26 states and 27 transitions. [2025-03-17 19:55:50,080 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2025-03-17 19:55:50,080 INFO L432 stractBuchiCegarLoop]: Abstraction has 26 states and 27 transitions. [2025-03-17 19:55:50,080 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-17 19:55:50,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 27 transitions. [2025-03-17 19:55:50,081 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2025-03-17 19:55:50,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:55:50,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:55:50,081 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 19:55:50,081 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [11, 10, 1, 1, 1, 1] [2025-03-17 19:55:50,081 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-17 19:55:50,081 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-17 19:55:50,081 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:50,081 INFO L85 PathProgramCache]: Analyzing trace with hash 45, now seen corresponding path program 5 times [2025-03-17 19:55:50,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:50,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [151140927] [2025-03-17 19:55:50,083 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 19:55:50,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:50,087 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:55:50,091 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:50,091 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 19:55:50,091 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:50,091 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:55:50,092 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:55:50,093 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:50,093 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:55:50,093 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:50,094 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:55:50,095 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:50,096 INFO L85 PathProgramCache]: Analyzing trace with hash 2020849485, now seen corresponding path program 3 times [2025-03-17 19:55:50,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:50,096 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1180060895] [2025-03-17 19:55:50,096 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 19:55:50,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:50,103 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 25 statements into 11 equivalence classes. [2025-03-17 19:55:50,117 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) and asserted 25 of 25 statements. [2025-03-17 19:55:50,117 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2025-03-17 19:55:50,117 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:55:50,794 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:50,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:55:50,794 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1180060895] [2025-03-17 19:55:50,794 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1180060895] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:55:50,794 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [463957828] [2025-03-17 19:55:50,794 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 19:55:50,794 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:55:50,794 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:55:50,797 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:55:50,799 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2025-03-17 19:55:50,836 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 25 statements into 11 equivalence classes. [2025-03-17 19:55:50,882 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) and asserted 25 of 25 statements. [2025-03-17 19:55:50,882 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2025-03-17 19:55:50,882 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:55:50,883 INFO L256 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 24 conjuncts are in the unsatisfiable core [2025-03-17 19:55:50,886 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:55:50,892 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-03-17 19:55:50,900 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:50,919 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:50,933 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:50,945 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:50,961 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:50,981 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:51,004 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:51,023 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:51,045 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:51,066 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:51,085 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:51,085 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:55:51,324 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:51,324 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [463957828] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:55:51,324 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:55:51,324 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 14, 14] total 40 [2025-03-17 19:55:51,324 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110321968] [2025-03-17 19:55:51,325 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:55:51,325 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 19:55:51,325 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:55:51,325 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2025-03-17 19:55:51,326 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=570, Invalid=990, Unknown=0, NotChecked=0, Total=1560 [2025-03-17 19:55:51,326 INFO L87 Difference]: Start difference. First operand 26 states and 27 transitions. cyclomatic complexity: 2 Second operand has 40 states, 40 states have (on average 1.725) internal successors, (69), 40 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:51,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:55:51,769 INFO L93 Difference]: Finished difference Result 50 states and 51 transitions. [2025-03-17 19:55:51,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50 states and 51 transitions. [2025-03-17 19:55:51,770 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2025-03-17 19:55:51,770 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50 states to 50 states and 51 transitions. [2025-03-17 19:55:51,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50 [2025-03-17 19:55:51,771 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50 [2025-03-17 19:55:51,771 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50 states and 51 transitions. [2025-03-17 19:55:51,771 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 19:55:51,771 INFO L218 hiAutomatonCegarLoop]: Abstraction has 50 states and 51 transitions. [2025-03-17 19:55:51,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states and 51 transitions. [2025-03-17 19:55:51,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2025-03-17 19:55:51,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.02) internal successors, (51), 49 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:51,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 51 transitions. [2025-03-17 19:55:51,776 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50 states and 51 transitions. [2025-03-17 19:55:51,776 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2025-03-17 19:55:51,777 INFO L432 stractBuchiCegarLoop]: Abstraction has 50 states and 51 transitions. [2025-03-17 19:55:51,777 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-17 19:55:51,777 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 51 transitions. [2025-03-17 19:55:51,778 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2025-03-17 19:55:51,778 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:55:51,778 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:55:51,778 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 19:55:51,779 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [23, 22, 1, 1, 1, 1] [2025-03-17 19:55:51,779 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-17 19:55:51,779 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-17 19:55:51,779 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:51,779 INFO L85 PathProgramCache]: Analyzing trace with hash 45, now seen corresponding path program 6 times [2025-03-17 19:55:51,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:51,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612834889] [2025-03-17 19:55:51,780 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 19:55:51,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:51,784 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:55:51,786 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:51,786 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 19:55:51,786 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:51,786 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:55:51,787 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:55:51,787 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:51,787 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:55:51,788 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:51,789 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:55:51,789 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:51,789 INFO L85 PathProgramCache]: Analyzing trace with hash 1277043545, now seen corresponding path program 4 times [2025-03-17 19:55:51,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:51,790 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585247454] [2025-03-17 19:55:51,790 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 19:55:51,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:51,807 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 49 statements into 2 equivalence classes. [2025-03-17 19:55:51,838 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 49 of 49 statements. [2025-03-17 19:55:51,838 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 19:55:51,838 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:55:53,886 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:53,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:55:53,886 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1585247454] [2025-03-17 19:55:53,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1585247454] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:55:53,886 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [550475108] [2025-03-17 19:55:53,886 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 19:55:53,886 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:55:53,886 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:55:53,889 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:55:53,890 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2025-03-17 19:55:53,939 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 49 statements into 2 equivalence classes. [2025-03-17 19:55:54,155 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 49 of 49 statements. [2025-03-17 19:55:54,155 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 19:55:54,155 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:55:54,157 INFO L256 TraceCheckSpWp]: Trace formula consists of 362 conjuncts, 48 conjuncts are in the unsatisfiable core [2025-03-17 19:55:54,163 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:55:54,167 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-03-17 19:55:54,173 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,196 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,223 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,243 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,263 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,282 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,302 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,322 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,343 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,364 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,386 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,409 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,432 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,451 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,473 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,495 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,518 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,548 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,575 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,602 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,629 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,655 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:55:54,682 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:54,682 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:55:55,402 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:55:55,402 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [550475108] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:55:55,402 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:55:55,402 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 26, 26] total 94 [2025-03-17 19:55:55,402 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1268805339] [2025-03-17 19:55:55,402 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:55:55,403 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 19:55:55,403 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:55:55,404 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2025-03-17 19:55:55,410 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3036, Invalid=5706, Unknown=0, NotChecked=0, Total=8742 [2025-03-17 19:55:55,411 INFO L87 Difference]: Start difference. First operand 50 states and 51 transitions. cyclomatic complexity: 2 Second operand has 94 states, 94 states have (on average 1.5) internal successors, (141), 94 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:56,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:55:56,678 INFO L93 Difference]: Finished difference Result 98 states and 99 transitions. [2025-03-17 19:55:56,678 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98 states and 99 transitions. [2025-03-17 19:55:56,679 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-17 19:55:56,680 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98 states to 98 states and 99 transitions. [2025-03-17 19:55:56,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98 [2025-03-17 19:55:56,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98 [2025-03-17 19:55:56,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98 states and 99 transitions. [2025-03-17 19:55:56,680 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 19:55:56,680 INFO L218 hiAutomatonCegarLoop]: Abstraction has 98 states and 99 transitions. [2025-03-17 19:55:56,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states and 99 transitions. [2025-03-17 19:55:56,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 98. [2025-03-17 19:55:56,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 1.010204081632653) internal successors, (99), 97 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:55:56,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 99 transitions. [2025-03-17 19:55:56,684 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98 states and 99 transitions. [2025-03-17 19:55:56,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2025-03-17 19:55:56,686 INFO L432 stractBuchiCegarLoop]: Abstraction has 98 states and 99 transitions. [2025-03-17 19:55:56,688 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-17 19:55:56,688 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98 states and 99 transitions. [2025-03-17 19:55:56,688 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-03-17 19:55:56,688 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:55:56,689 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:55:56,689 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 19:55:56,689 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [47, 46, 1, 1, 1, 1] [2025-03-17 19:55:56,689 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-17 19:55:56,689 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-17 19:55:56,690 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:56,690 INFO L85 PathProgramCache]: Analyzing trace with hash 45, now seen corresponding path program 7 times [2025-03-17 19:55:56,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:56,690 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387495550] [2025-03-17 19:55:56,690 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 19:55:56,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:56,695 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:55:56,696 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:56,696 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:55:56,696 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:56,696 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:55:56,697 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:55:56,698 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:55:56,698 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:55:56,698 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:55:56,699 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:55:56,699 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:55:56,699 INFO L85 PathProgramCache]: Analyzing trace with hash -207761551, now seen corresponding path program 5 times [2025-03-17 19:55:56,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:55:56,699 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100336318] [2025-03-17 19:55:56,699 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 19:55:56,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:55:56,718 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 97 statements into 47 equivalence classes. [2025-03-17 19:55:56,820 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) and asserted 97 of 97 statements. [2025-03-17 19:55:56,820 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2025-03-17 19:55:56,820 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:56:00,891 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:56:00,891 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:56:00,891 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100336318] [2025-03-17 19:56:00,891 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100336318] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:56:00,891 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [716639659] [2025-03-17 19:56:00,891 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 19:56:00,892 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:56:00,892 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:56:00,893 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:56:00,895 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2025-03-17 19:56:00,968 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 97 statements into 47 equivalence classes. [2025-03-17 19:56:17,220 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) and asserted 97 of 97 statements. [2025-03-17 19:56:17,221 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2025-03-17 19:56:17,221 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:56:17,233 INFO L256 TraceCheckSpWp]: Trace formula consists of 722 conjuncts, 96 conjuncts are in the unsatisfiable core [2025-03-17 19:56:17,241 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:56:17,246 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2025-03-17 19:56:17,251 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,264 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,280 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,297 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,310 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,326 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,342 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,360 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,376 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,393 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,411 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,430 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,448 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,467 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,494 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,516 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,547 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,569 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,595 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,630 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,658 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,684 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,708 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,732 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,758 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,784 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,813 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,842 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,871 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,897 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,924 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,952 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:17,987 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,015 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,042 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,070 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,104 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,135 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,168 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,201 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,239 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,275 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,309 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,352 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,395 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,434 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 11 [2025-03-17 19:56:18,466 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:56:18,466 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:56:20,527 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:56:20,527 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [716639659] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:56:20,527 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:56:20,527 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 50, 50] total 160 [2025-03-17 19:56:20,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1681247168] [2025-03-17 19:56:20,528 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:56:20,528 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-17 19:56:20,528 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:56:20,530 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 160 interpolants. [2025-03-17 19:56:20,538 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9054, Invalid=16386, Unknown=0, NotChecked=0, Total=25440 [2025-03-17 19:56:20,539 INFO L87 Difference]: Start difference. First operand 98 states and 99 transitions. cyclomatic complexity: 2 Second operand has 160 states, 160 states have (on average 1.775) internal successors, (284), 160 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:56:24,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:56:24,109 INFO L93 Difference]: Finished difference Result 194 states and 195 transitions. [2025-03-17 19:56:24,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 194 states and 195 transitions. [2025-03-17 19:56:24,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193 [2025-03-17 19:56:24,112 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 194 states to 194 states and 195 transitions. [2025-03-17 19:56:24,112 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 194 [2025-03-17 19:56:24,112 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 194 [2025-03-17 19:56:24,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 194 states and 195 transitions. [2025-03-17 19:56:24,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 19:56:24,112 INFO L218 hiAutomatonCegarLoop]: Abstraction has 194 states and 195 transitions. [2025-03-17 19:56:24,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states and 195 transitions. [2025-03-17 19:56:24,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 194. [2025-03-17 19:56:24,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 194 states, 194 states have (on average 1.0051546391752577) internal successors, (195), 193 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:56:24,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 195 transitions. [2025-03-17 19:56:24,119 INFO L240 hiAutomatonCegarLoop]: Abstraction has 194 states and 195 transitions. [2025-03-17 19:56:24,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 190 states. [2025-03-17 19:56:24,120 INFO L432 stractBuchiCegarLoop]: Abstraction has 194 states and 195 transitions. [2025-03-17 19:56:24,120 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-17 19:56:24,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 194 states and 195 transitions. [2025-03-17 19:56:24,121 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 193 [2025-03-17 19:56:24,121 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:56:24,121 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:56:24,122 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-03-17 19:56:24,122 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [95, 94, 1, 1, 1, 1] [2025-03-17 19:56:24,122 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~mem4#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, main_~x2~0#1.base, main_~x2~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~x1~0#1.base, main_~x1~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~x2~0#1.base, main_~x2~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;" [2025-03-17 19:56:24,122 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem4#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);" "assume main_#t~mem4#1 <= 10;havoc main_#t~mem4#1;call write~int#0(1000, main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume main_#t~mem5#1 > 1;havoc main_#t~mem5#1;call main_#t~mem6#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);call write~int#0(main_#t~mem6#1 - 1, main_~x2~0#1.base, main_~x2~0#1.offset, 4);havoc main_#t~mem6#1;" "assume true;call main_#t~mem5#1 := read~int#0(main_~x2~0#1.base, main_~x2~0#1.offset, 4);" "assume !(main_#t~mem5#1 > 1);havoc main_#t~mem5#1;" "call main_#t~mem7#1 := read~int#1(main_~x1~0#1.base, main_~x1~0#1.offset, 4);call write~int#1(1 + main_#t~mem7#1, main_~x1~0#1.base, main_~x1~0#1.offset, 4);havoc main_#t~mem7#1;" [2025-03-17 19:56:24,123 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:56:24,123 INFO L85 PathProgramCache]: Analyzing trace with hash 45, now seen corresponding path program 8 times [2025-03-17 19:56:24,123 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:56:24,123 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834812491] [2025-03-17 19:56:24,123 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 19:56:24,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:56:24,125 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:56:24,126 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:56:24,126 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 19:56:24,126 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:56:24,126 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:56:24,127 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-03-17 19:56:24,127 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-03-17 19:56:24,127 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:56:24,127 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:56:24,128 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:56:24,128 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:56:24,128 INFO L85 PathProgramCache]: Analyzing trace with hash 1830320033, now seen corresponding path program 6 times [2025-03-17 19:56:24,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:56:24,128 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1488637160] [2025-03-17 19:56:24,128 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 19:56:24,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:56:24,160 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 193 statements into 95 equivalence classes. [2025-03-17 19:56:24,428 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) and asserted 193 of 193 statements. [2025-03-17 19:56:24,428 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2025-03-17 19:56:24,428 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:56:39,809 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:56:39,809 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:56:39,809 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1488637160] [2025-03-17 19:56:39,809 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1488637160] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:56:39,809 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1874201084] [2025-03-17 19:56:39,809 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 19:56:39,809 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:56:39,810 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:56:39,811 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:56:39,812 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2025-03-17 19:56:39,898 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 193 statements into 95 equivalence classes.