./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/termination-15/array16_alloca_fixed.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8fc3dc66 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/termination-15/array16_alloca_fixed.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2a580f3a42bca030605af1bbd4c6a77550e46d88a6197c1e34cf45bb050eadef --- Real Ultimate output --- This is Ultimate 0.3.0-?-8fc3dc6-m [2025-03-17 19:58:29,947 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-17 19:58:29,996 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf [2025-03-17 19:58:30,000 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-17 19:58:30,000 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-17 19:58:30,000 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-17 19:58:30,016 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-17 19:58:30,016 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-17 19:58:30,016 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-17 19:58:30,017 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-17 19:58:30,017 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-17 19:58:30,017 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-17 19:58:30,017 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-17 19:58:30,017 INFO L153 SettingsManager]: * Use SBE=true [2025-03-17 19:58:30,017 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-17 19:58:30,017 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-17 19:58:30,017 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-17 19:58:30,017 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-17 19:58:30,017 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-17 19:58:30,017 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-17 19:58:30,017 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-17 19:58:30,017 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-17 19:58:30,017 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-17 19:58:30,018 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-17 19:58:30,018 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-17 19:58:30,018 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-17 19:58:30,018 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-17 19:58:30,018 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-17 19:58:30,018 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-17 19:58:30,018 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-17 19:58:30,018 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-17 19:58:30,018 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-17 19:58:30,018 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-17 19:58:30,018 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-17 19:58:30,018 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-17 19:58:30,018 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-17 19:58:30,018 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-17 19:58:30,018 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2a580f3a42bca030605af1bbd4c6a77550e46d88a6197c1e34cf45bb050eadef [2025-03-17 19:58:30,257 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-17 19:58:30,266 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-17 19:58:30,268 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-17 19:58:30,269 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-17 19:58:30,269 INFO L274 PluginConnector]: CDTParser initialized [2025-03-17 19:58:30,270 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/termination-15/array16_alloca_fixed.i [2025-03-17 19:58:31,425 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/099110032/6e086cc3148145a1a7fd356e2ffc30e4/FLAGe4c619077 [2025-03-17 19:58:31,681 INFO L384 CDTParser]: Found 1 translation units. [2025-03-17 19:58:31,684 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/termination-15/array16_alloca_fixed.i [2025-03-17 19:58:31,694 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/099110032/6e086cc3148145a1a7fd356e2ffc30e4/FLAGe4c619077 [2025-03-17 19:58:31,705 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/099110032/6e086cc3148145a1a7fd356e2ffc30e4 [2025-03-17 19:58:31,706 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-17 19:58:31,707 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-17 19:58:31,708 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-17 19:58:31,708 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-17 19:58:31,711 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-17 19:58:31,712 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:31,712 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@37eaf57a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31, skipping insertion in model container [2025-03-17 19:58:31,712 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:31,731 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-17 19:58:31,937 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 19:58:31,946 INFO L200 MainTranslator]: Completed pre-run [2025-03-17 19:58:31,973 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-17 19:58:31,997 INFO L204 MainTranslator]: Completed translation [2025-03-17 19:58:31,997 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31 WrapperNode [2025-03-17 19:58:31,997 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-17 19:58:31,998 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-17 19:58:31,998 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-17 19:58:31,998 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-17 19:58:32,003 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:32,012 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:32,026 INFO L138 Inliner]: procedures = 151, calls = 10, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 49 [2025-03-17 19:58:32,026 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-17 19:58:32,026 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-17 19:58:32,026 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-17 19:58:32,026 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-17 19:58:32,032 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:32,032 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:32,034 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:32,044 INFO L175 MemorySlicer]: Split 4 memory accesses to 1 slices as follows [4]. 100 percent of accesses are in the largest equivalence class. The 0 initializations are split as follows [0]. The 2 writes are split as follows [2]. [2025-03-17 19:58:32,045 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:32,045 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:32,048 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:32,048 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:32,049 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:32,049 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:32,050 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-17 19:58:32,050 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-17 19:58:32,051 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-17 19:58:32,051 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-17 19:58:32,051 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31" (1/1) ... [2025-03-17 19:58:32,055 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 19:58:32,063 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:32,076 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 19:58:32,079 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-17 19:58:32,095 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-03-17 19:58:32,095 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-03-17 19:58:32,095 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-03-17 19:58:32,095 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-17 19:58:32,095 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-17 19:58:32,095 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-17 19:58:32,142 INFO L256 CfgBuilder]: Building ICFG [2025-03-17 19:58:32,144 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-17 19:58:32,242 INFO L1322 $ProcedureCfgBuilder]: dead code at ProgramPoint L368: call ULTIMATE.dealloc(main_#t~malloc206#1.base, main_#t~malloc206#1.offset);havoc main_#t~malloc206#1.base, main_#t~malloc206#1.offset; [2025-03-17 19:58:32,246 INFO L? ?]: Removed 8 outVars from TransFormulas that were not future-live. [2025-03-17 19:58:32,246 INFO L307 CfgBuilder]: Performing block encoding [2025-03-17 19:58:32,251 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-17 19:58:32,252 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-17 19:58:32,252 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 07:58:32 BoogieIcfgContainer [2025-03-17 19:58:32,252 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-17 19:58:32,253 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-17 19:58:32,253 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-17 19:58:32,257 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-17 19:58:32,257 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 19:58:32,258 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.03 07:58:31" (1/3) ... [2025-03-17 19:58:32,259 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@11827fcf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 07:58:32, skipping insertion in model container [2025-03-17 19:58:32,260 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 19:58:32,260 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.03 07:58:31" (2/3) ... [2025-03-17 19:58:32,260 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@11827fcf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.03 07:58:32, skipping insertion in model container [2025-03-17 19:58:32,260 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-17 19:58:32,261 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 07:58:32" (3/3) ... [2025-03-17 19:58:32,261 INFO L363 chiAutomizerObserver]: Analyzing ICFG array16_alloca_fixed.i [2025-03-17 19:58:32,296 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-17 19:58:32,296 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-17 19:58:32,297 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-17 19:58:32,297 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-17 19:58:32,297 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-17 19:58:32,297 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-17 19:58:32,298 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-17 19:58:32,298 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-17 19:58:32,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 12 states, 11 states have (on average 1.5454545454545454) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:32,314 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2025-03-17 19:58:32,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:32,315 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:32,318 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2025-03-17 19:58:32,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-17 19:58:32,318 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-17 19:58:32,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 12 states, 11 states have (on average 1.5454545454545454) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:32,319 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2025-03-17 19:58:32,319 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:32,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:32,320 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2025-03-17 19:58:32,320 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-17 19:58:32,323 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" [2025-03-17 19:58:32,324 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" [2025-03-17 19:58:32,330 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:32,330 INFO L85 PathProgramCache]: Analyzing trace with hash 1538143, now seen corresponding path program 1 times [2025-03-17 19:58:32,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:32,336 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876775722] [2025-03-17 19:58:32,337 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:32,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:32,387 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-03-17 19:58:32,406 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-03-17 19:58:32,408 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:32,408 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:32,408 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:32,415 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-03-17 19:58:32,421 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-03-17 19:58:32,421 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:32,421 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:32,434 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:32,436 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:32,437 INFO L85 PathProgramCache]: Analyzing trace with hash 40649, now seen corresponding path program 1 times [2025-03-17 19:58:32,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:32,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589016208] [2025-03-17 19:58:32,437 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:32,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:32,447 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-17 19:58:32,460 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-17 19:58:32,461 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:32,461 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:32,462 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:32,465 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-17 19:58:32,475 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-17 19:58:32,475 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:32,475 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:32,477 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:32,479 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:32,479 INFO L85 PathProgramCache]: Analyzing trace with hash -1421811285, now seen corresponding path program 1 times [2025-03-17 19:58:32,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:32,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [311720178] [2025-03-17 19:58:32,480 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:32,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:32,490 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-03-17 19:58:32,521 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-03-17 19:58:32,521 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:32,521 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:32,521 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:32,524 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-03-17 19:58:32,537 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-03-17 19:58:32,541 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:32,542 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:32,544 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:32,791 INFO L204 LassoAnalysis]: Preferences: [2025-03-17 19:58:32,791 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-17 19:58:32,792 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-17 19:58:32,793 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-17 19:58:32,793 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-03-17 19:58:32,793 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 19:58:32,794 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-17 19:58:32,794 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-17 19:58:32,794 INFO L132 ssoRankerPreferences]: Filename of dumped script: array16_alloca_fixed.i_Iteration1_Lasso [2025-03-17 19:58:32,794 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-17 19:58:32,794 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-17 19:58:32,804 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:32,810 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:32,935 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:32,938 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:32,939 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:32,941 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:32,944 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:32,946 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:32,948 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:32,951 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:32,953 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:33,135 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-17 19:58:33,137 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-03-17 19:58:33,138 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 19:58:33,138 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:33,140 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 19:58:33,142 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-03-17 19:58:33,144 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-17 19:58:33,155 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-17 19:58:33,155 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-17 19:58:33,155 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-17 19:58:33,156 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-17 19:58:33,156 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-17 19:58:33,160 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-17 19:58:33,160 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-17 19:58:33,163 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-17 19:58:33,170 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2025-03-17 19:58:33,170 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 19:58:33,170 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:33,174 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 19:58:33,176 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-03-17 19:58:33,177 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-17 19:58:33,187 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-17 19:58:33,188 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-17 19:58:33,188 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-17 19:58:33,188 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-17 19:58:33,190 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-17 19:58:33,191 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-17 19:58:33,196 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-17 19:58:33,202 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2025-03-17 19:58:33,202 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 19:58:33,202 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:33,204 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 19:58:33,206 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-03-17 19:58:33,207 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-17 19:58:33,217 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-17 19:58:33,218 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-17 19:58:33,218 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-17 19:58:33,218 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-17 19:58:33,225 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-17 19:58:33,226 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-17 19:58:33,236 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-03-17 19:58:33,268 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2025-03-17 19:58:33,270 INFO L444 ModelExtractionUtils]: 3 out of 19 variables were initially zero. Simplification set additionally 12 variables to zero. [2025-03-17 19:58:33,271 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 19:58:33,271 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:33,273 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 19:58:33,275 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-03-17 19:58:33,277 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-03-17 19:58:33,288 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-03-17 19:58:33,288 INFO L474 LassoAnalysis]: Proved termination. [2025-03-17 19:58:33,288 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~arr~0#1.offset, v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1, ULTIMATE.start_main_~i~0#1) = -1*ULTIMATE.start_main_~arr~0#1.offset + 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2025-03-17 19:58:33,294 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2025-03-17 19:58:33,303 INFO L156 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2025-03-17 19:58:33,309 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: #length [2025-03-17 19:58:33,310 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#length,GLOBAL] [2025-03-17 19:58:33,310 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: ~arr~0!offset [2025-03-17 19:58:33,321 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:33,327 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-03-17 19:58:33,331 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-03-17 19:58:33,331 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:33,331 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:33,333 INFO L256 TraceCheckSpWp]: Trace formula consists of 25 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-03-17 19:58:33,334 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:33,343 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-17 19:58:33,346 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-17 19:58:33,346 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:33,346 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:33,346 INFO L256 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-03-17 19:58:33,347 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:33,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:33,386 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-03-17 19:58:33,387 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 12 states, 11 states have (on average 1.5454545454545454) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:33,426 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 12 states, 11 states have (on average 1.5454545454545454) internal successors, (17), 11 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 19 states and 27 transitions. Complement of second has 5 states. [2025-03-17 19:58:33,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-03-17 19:58:33,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:33,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 12 transitions. [2025-03-17 19:58:33,438 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 12 transitions. Stem has 4 letters. Loop has 3 letters. [2025-03-17 19:58:33,439 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-17 19:58:33,439 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 12 transitions. Stem has 7 letters. Loop has 3 letters. [2025-03-17 19:58:33,439 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-17 19:58:33,439 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 12 transitions. Stem has 4 letters. Loop has 6 letters. [2025-03-17 19:58:33,439 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-17 19:58:33,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19 states and 27 transitions. [2025-03-17 19:58:33,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:33,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19 states to 11 states and 16 transitions. [2025-03-17 19:58:33,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2025-03-17 19:58:33,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2025-03-17 19:58:33,443 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 16 transitions. [2025-03-17 19:58:33,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 19:58:33,443 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11 states and 16 transitions. [2025-03-17 19:58:33,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 16 transitions. [2025-03-17 19:58:33,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 10. [2025-03-17 19:58:33,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.5) internal successors, (15), 9 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:33,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 15 transitions. [2025-03-17 19:58:33,459 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10 states and 15 transitions. [2025-03-17 19:58:33,459 INFO L432 stractBuchiCegarLoop]: Abstraction has 10 states and 15 transitions. [2025-03-17 19:58:33,459 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-17 19:58:33,459 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 15 transitions. [2025-03-17 19:58:33,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:33,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:33,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:33,460 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2025-03-17 19:58:33,460 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:33,460 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" [2025-03-17 19:58:33,460 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:33,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:33,461 INFO L85 PathProgramCache]: Analyzing trace with hash 47682440, now seen corresponding path program 1 times [2025-03-17 19:58:33,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:33,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560756892] [2025-03-17 19:58:33,461 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:33,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:33,467 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-03-17 19:58:33,471 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-03-17 19:58:33,471 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:33,471 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:33,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:33,532 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:33,532 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [560756892] [2025-03-17 19:58:33,532 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [560756892] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 19:58:33,532 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-17 19:58:33,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-17 19:58:33,533 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [524256168] [2025-03-17 19:58:33,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 19:58:33,534 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:33,535 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:33,535 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 1 times [2025-03-17 19:58:33,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:33,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [504662415] [2025-03-17 19:58:33,535 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:33,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:33,539 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:33,543 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:33,544 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:33,544 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:33,544 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:33,548 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:33,552 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:33,553 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:33,553 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:33,554 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:33,603 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:33,604 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-17 19:58:33,605 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2025-03-17 19:58:33,605 INFO L87 Difference]: Start difference. First operand 10 states and 15 transitions. cyclomatic complexity: 7 Second operand has 4 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:33,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:33,624 INFO L93 Difference]: Finished difference Result 12 states and 17 transitions. [2025-03-17 19:58:33,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12 states and 17 transitions. [2025-03-17 19:58:33,625 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:33,625 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12 states to 12 states and 17 transitions. [2025-03-17 19:58:33,625 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2025-03-17 19:58:33,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2025-03-17 19:58:33,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2025-03-17 19:58:33,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 19:58:33,625 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2025-03-17 19:58:33,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2025-03-17 19:58:33,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 10. [2025-03-17 19:58:33,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.4) internal successors, (14), 9 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:33,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 14 transitions. [2025-03-17 19:58:33,626 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10 states and 14 transitions. [2025-03-17 19:58:33,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-17 19:58:33,627 INFO L432 stractBuchiCegarLoop]: Abstraction has 10 states and 14 transitions. [2025-03-17 19:58:33,627 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-17 19:58:33,627 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 14 transitions. [2025-03-17 19:58:33,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:33,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:33,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:33,627 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:33,627 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:33,628 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" [2025-03-17 19:58:33,628 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:33,628 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:33,628 INFO L85 PathProgramCache]: Analyzing trace with hash -1126475907, now seen corresponding path program 1 times [2025-03-17 19:58:33,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:33,628 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775311712] [2025-03-17 19:58:33,628 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:33,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:33,632 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-17 19:58:33,637 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-17 19:58:33,637 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:33,637 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:33,637 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:33,639 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-17 19:58:33,648 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-17 19:58:33,649 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:33,649 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:33,654 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:33,654 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:33,655 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 2 times [2025-03-17 19:58:33,655 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:33,655 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510567699] [2025-03-17 19:58:33,655 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 19:58:33,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:33,659 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:33,663 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:33,664 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 19:58:33,664 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:33,664 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:33,665 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:33,667 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:33,667 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:33,667 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:33,668 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:33,669 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:33,669 INFO L85 PathProgramCache]: Analyzing trace with hash -211587845, now seen corresponding path program 1 times [2025-03-17 19:58:33,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:33,669 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [980569165] [2025-03-17 19:58:33,669 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:33,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:33,672 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-17 19:58:33,682 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-17 19:58:33,685 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:33,685 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:33,685 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:33,687 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-17 19:58:33,700 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-17 19:58:33,700 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:33,700 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:33,706 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:33,797 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2025-03-17 19:58:33,923 INFO L204 LassoAnalysis]: Preferences: [2025-03-17 19:58:33,923 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-17 19:58:33,923 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-17 19:58:33,923 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-17 19:58:33,923 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-03-17 19:58:33,923 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 19:58:33,923 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-17 19:58:33,923 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-17 19:58:33,923 INFO L132 ssoRankerPreferences]: Filename of dumped script: array16_alloca_fixed.i_Iteration3_Lasso [2025-03-17 19:58:33,923 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-17 19:58:33,923 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-17 19:58:33,926 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:33,932 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:34,024 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:34,026 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:34,027 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:34,029 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:34,030 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:34,031 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:34,033 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:34,035 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:34,037 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-17 19:58:34,204 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-17 19:58:34,204 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-03-17 19:58:34,204 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 19:58:34,204 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:34,206 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 19:58:34,207 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-03-17 19:58:34,208 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-17 19:58:34,217 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-17 19:58:34,217 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-17 19:58:34,217 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-17 19:58:34,217 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-17 19:58:34,218 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-17 19:58:34,218 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-17 19:58:34,218 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-17 19:58:34,219 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-17 19:58:34,224 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2025-03-17 19:58:34,225 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 19:58:34,225 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:34,226 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 19:58:34,228 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-03-17 19:58:34,229 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-17 19:58:34,239 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-17 19:58:34,239 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-17 19:58:34,239 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-17 19:58:34,239 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-17 19:58:34,243 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-17 19:58:34,243 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-17 19:58:34,249 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-03-17 19:58:34,267 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2025-03-17 19:58:34,267 INFO L444 ModelExtractionUtils]: 1 out of 19 variables were initially zero. Simplification set additionally 15 variables to zero. [2025-03-17 19:58:34,267 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-17 19:58:34,267 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:34,269 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-17 19:58:34,270 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-03-17 19:58:34,271 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-03-17 19:58:34,282 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-03-17 19:58:34,282 INFO L474 LassoAnalysis]: Proved termination. [2025-03-17 19:58:34,282 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~length~0#1, ULTIMATE.start_main_~j~0#1) = 1*ULTIMATE.start_main_~length~0#1 - 1*ULTIMATE.start_main_~j~0#1 Supporting invariants [] [2025-03-17 19:58:34,289 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2025-03-17 19:58:34,297 INFO L156 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2025-03-17 19:58:34,311 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:34,318 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-17 19:58:34,325 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-17 19:58:34,325 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:34,325 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:34,326 INFO L256 TraceCheckSpWp]: Trace formula consists of 43 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-03-17 19:58:34,326 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:34,339 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:34,340 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:34,341 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:34,341 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:34,342 INFO L256 TraceCheckSpWp]: Trace formula consists of 14 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-03-17 19:58:34,343 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:34,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:34,353 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-03-17 19:58:34,353 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 10 states and 14 transitions. cyclomatic complexity: 6 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:34,370 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 10 states and 14 transitions. cyclomatic complexity: 6. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 14 states and 20 transitions. Complement of second has 5 states. [2025-03-17 19:58:34,371 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-03-17 19:58:34,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:34,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 12 transitions. [2025-03-17 19:58:34,371 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 12 transitions. Stem has 8 letters. Loop has 2 letters. [2025-03-17 19:58:34,372 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-17 19:58:34,372 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 12 transitions. Stem has 10 letters. Loop has 2 letters. [2025-03-17 19:58:34,372 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-17 19:58:34,372 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 12 transitions. Stem has 8 letters. Loop has 4 letters. [2025-03-17 19:58:34,372 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-17 19:58:34,372 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 20 transitions. [2025-03-17 19:58:34,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:34,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 20 transitions. [2025-03-17 19:58:34,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2025-03-17 19:58:34,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2025-03-17 19:58:34,372 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 20 transitions. [2025-03-17 19:58:34,373 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:34,373 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 20 transitions. [2025-03-17 19:58:34,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 20 transitions. [2025-03-17 19:58:34,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2025-03-17 19:58:34,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:34,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 20 transitions. [2025-03-17 19:58:34,373 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14 states and 20 transitions. [2025-03-17 19:58:34,373 INFO L432 stractBuchiCegarLoop]: Abstraction has 14 states and 20 transitions. [2025-03-17 19:58:34,373 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-17 19:58:34,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 20 transitions. [2025-03-17 19:58:34,374 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:34,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:34,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:34,374 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:34,374 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:34,374 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:34,374 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:34,376 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:34,376 INFO L85 PathProgramCache]: Analyzing trace with hash -211587844, now seen corresponding path program 1 times [2025-03-17 19:58:34,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:34,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403270324] [2025-03-17 19:58:34,377 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:34,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:34,381 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-17 19:58:34,401 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-17 19:58:34,401 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:34,401 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:34,502 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2025-03-17 19:58:34,770 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:34,770 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:34,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403270324] [2025-03-17 19:58:34,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403270324] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:34,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [669582100] [2025-03-17 19:58:34,770 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:34,770 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:34,770 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:34,773 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:34,774 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2025-03-17 19:58:34,801 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-17 19:58:34,808 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-17 19:58:34,809 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:34,809 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:34,809 INFO L256 TraceCheckSpWp]: Trace formula consists of 54 conjuncts, 13 conjuncts are in the unsatisfiable core [2025-03-17 19:58:34,810 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:34,835 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2025-03-17 19:58:34,883 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2025-03-17 19:58:34,896 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:34,896 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:34,952 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2025-03-17 19:58:34,955 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2025-03-17 19:58:34,959 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:34,959 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [669582100] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:34,959 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:34,959 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 6, 6] total 15 [2025-03-17 19:58:34,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833935451] [2025-03-17 19:58:34,959 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:34,960 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:34,960 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:34,960 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 3 times [2025-03-17 19:58:34,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:34,961 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [129702388] [2025-03-17 19:58:34,961 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 19:58:34,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:34,964 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:34,967 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:34,967 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 19:58:34,967 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:34,967 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:34,968 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:34,970 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:34,970 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:34,970 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:34,971 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:35,007 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:35,007 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2025-03-17 19:58:35,008 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=187, Unknown=0, NotChecked=0, Total=240 [2025-03-17 19:58:35,008 INFO L87 Difference]: Start difference. First operand 14 states and 20 transitions. cyclomatic complexity: 9 Second operand has 16 states, 15 states have (on average 1.4666666666666666) internal successors, (22), 16 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:35,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:35,127 INFO L93 Difference]: Finished difference Result 27 states and 38 transitions. [2025-03-17 19:58:35,128 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 38 transitions. [2025-03-17 19:58:35,128 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2025-03-17 19:58:35,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 26 states and 37 transitions. [2025-03-17 19:58:35,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2025-03-17 19:58:35,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2025-03-17 19:58:35,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26 states and 37 transitions. [2025-03-17 19:58:35,129 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:35,129 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26 states and 37 transitions. [2025-03-17 19:58:35,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states and 37 transitions. [2025-03-17 19:58:35,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 19. [2025-03-17 19:58:35,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.4736842105263157) internal successors, (28), 18 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:35,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 28 transitions. [2025-03-17 19:58:35,131 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19 states and 28 transitions. [2025-03-17 19:58:35,131 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 19:58:35,131 INFO L432 stractBuchiCegarLoop]: Abstraction has 19 states and 28 transitions. [2025-03-17 19:58:35,131 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-17 19:58:35,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 28 transitions. [2025-03-17 19:58:35,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:35,132 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:35,132 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:35,132 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:35,132 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:35,132 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:35,132 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:35,132 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:35,132 INFO L85 PathProgramCache]: Analyzing trace with hash -1472455942, now seen corresponding path program 1 times [2025-03-17 19:58:35,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:35,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332245360] [2025-03-17 19:58:35,133 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:35,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:35,137 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-03-17 19:58:35,140 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-03-17 19:58:35,141 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:35,141 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:35,194 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:35,194 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:35,194 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1332245360] [2025-03-17 19:58:35,194 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1332245360] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:35,194 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1938924010] [2025-03-17 19:58:35,194 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:35,194 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:35,194 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:35,200 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:35,202 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2025-03-17 19:58:35,228 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-03-17 19:58:35,235 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-03-17 19:58:35,235 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:35,235 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:35,236 INFO L256 TraceCheckSpWp]: Trace formula consists of 66 conjuncts, 6 conjuncts are in the unsatisfiable core [2025-03-17 19:58:35,237 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:35,282 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:35,282 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:35,308 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:35,308 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1938924010] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:35,308 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:35,308 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 10 [2025-03-17 19:58:35,308 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1845172658] [2025-03-17 19:58:35,308 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:35,308 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:35,308 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:35,308 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 4 times [2025-03-17 19:58:35,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:35,308 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131226296] [2025-03-17 19:58:35,308 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 19:58:35,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:35,312 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-17 19:58:35,319 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:35,319 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 19:58:35,319 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:35,319 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:35,320 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:35,321 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:35,321 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:35,321 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:35,322 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:35,364 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:35,364 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-17 19:58:35,364 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2025-03-17 19:58:35,365 INFO L87 Difference]: Start difference. First operand 19 states and 28 transitions. cyclomatic complexity: 13 Second operand has 10 states, 10 states have (on average 2.3) internal successors, (23), 10 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:35,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:35,406 INFO L93 Difference]: Finished difference Result 27 states and 37 transitions. [2025-03-17 19:58:35,406 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 37 transitions. [2025-03-17 19:58:35,407 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:35,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 24 states and 34 transitions. [2025-03-17 19:58:35,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2025-03-17 19:58:35,407 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2025-03-17 19:58:35,407 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24 states and 34 transitions. [2025-03-17 19:58:35,407 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:35,407 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24 states and 34 transitions. [2025-03-17 19:58:35,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states and 34 transitions. [2025-03-17 19:58:35,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 21. [2025-03-17 19:58:35,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.4285714285714286) internal successors, (30), 20 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:35,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 30 transitions. [2025-03-17 19:58:35,409 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21 states and 30 transitions. [2025-03-17 19:58:35,409 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-17 19:58:35,409 INFO L432 stractBuchiCegarLoop]: Abstraction has 21 states and 30 transitions. [2025-03-17 19:58:35,410 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-17 19:58:35,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 30 transitions. [2025-03-17 19:58:35,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:35,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:35,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:35,410 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:35,410 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:35,411 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:35,411 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:35,411 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:35,411 INFO L85 PathProgramCache]: Analyzing trace with hash 1715913382, now seen corresponding path program 1 times [2025-03-17 19:58:35,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:35,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090489625] [2025-03-17 19:58:35,411 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:35,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:35,415 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-03-17 19:58:35,424 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-03-17 19:58:35,424 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:35,424 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:35,808 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:35,808 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:35,808 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2090489625] [2025-03-17 19:58:35,808 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2090489625] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:35,808 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1074469307] [2025-03-17 19:58:35,808 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:35,808 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:35,809 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:35,810 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:35,812 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2025-03-17 19:58:35,838 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-03-17 19:58:35,847 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-03-17 19:58:35,847 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:35,847 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:35,848 INFO L256 TraceCheckSpWp]: Trace formula consists of 76 conjuncts, 18 conjuncts are in the unsatisfiable core [2025-03-17 19:58:35,849 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:35,862 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2025-03-17 19:58:35,910 INFO L349 Elim1Store]: treesize reduction 25, result has 21.9 percent of original size [2025-03-17 19:58:35,910 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 13 [2025-03-17 19:58:35,926 INFO L349 Elim1Store]: treesize reduction 25, result has 21.9 percent of original size [2025-03-17 19:58:35,927 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 13 [2025-03-17 19:58:35,959 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2025-03-17 19:58:35,970 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:35,970 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:36,121 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2025-03-17 19:58:36,125 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 44 [2025-03-17 19:58:36,144 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:36,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1074469307] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:36,144 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:36,144 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 20 [2025-03-17 19:58:36,144 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1529395423] [2025-03-17 19:58:36,144 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:36,145 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:36,145 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:36,145 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 5 times [2025-03-17 19:58:36,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:36,145 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744471977] [2025-03-17 19:58:36,145 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 19:58:36,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:36,148 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:36,150 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:36,150 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 19:58:36,150 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:36,150 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:36,151 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:36,152 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:36,152 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:36,152 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:36,153 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:36,193 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:36,193 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2025-03-17 19:58:36,194 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=340, Unknown=0, NotChecked=0, Total=420 [2025-03-17 19:58:36,194 INFO L87 Difference]: Start difference. First operand 21 states and 30 transitions. cyclomatic complexity: 13 Second operand has 21 states, 20 states have (on average 1.55) internal successors, (31), 21 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:36,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:36,319 INFO L93 Difference]: Finished difference Result 23 states and 31 transitions. [2025-03-17 19:58:36,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 31 transitions. [2025-03-17 19:58:36,319 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:36,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 22 states and 30 transitions. [2025-03-17 19:58:36,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2025-03-17 19:58:36,320 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2025-03-17 19:58:36,320 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 30 transitions. [2025-03-17 19:58:36,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:36,320 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22 states and 30 transitions. [2025-03-17 19:58:36,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 30 transitions. [2025-03-17 19:58:36,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 17. [2025-03-17 19:58:36,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.3529411764705883) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:36,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 23 transitions. [2025-03-17 19:58:36,321 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17 states and 23 transitions. [2025-03-17 19:58:36,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-17 19:58:36,324 INFO L432 stractBuchiCegarLoop]: Abstraction has 17 states and 23 transitions. [2025-03-17 19:58:36,325 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-17 19:58:36,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 23 transitions. [2025-03-17 19:58:36,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:36,326 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:36,326 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:36,326 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:36,326 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:36,326 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:36,326 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:36,327 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:36,327 INFO L85 PathProgramCache]: Analyzing trace with hash 612821349, now seen corresponding path program 2 times [2025-03-17 19:58:36,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:36,327 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [950918254] [2025-03-17 19:58:36,327 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 19:58:36,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:36,333 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 15 statements into 2 equivalence classes. [2025-03-17 19:58:36,345 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 15 of 15 statements. [2025-03-17 19:58:36,346 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-17 19:58:36,346 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:36,589 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:36,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:36,590 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [950918254] [2025-03-17 19:58:36,590 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [950918254] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:36,590 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [391537976] [2025-03-17 19:58:36,590 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 19:58:36,590 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:36,590 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:36,592 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:36,594 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2025-03-17 19:58:36,624 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 15 statements into 2 equivalence classes. [2025-03-17 19:58:36,634 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 15 of 15 statements. [2025-03-17 19:58:36,634 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-17 19:58:36,634 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:36,635 INFO L256 TraceCheckSpWp]: Trace formula consists of 81 conjuncts, 21 conjuncts are in the unsatisfiable core [2025-03-17 19:58:36,637 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:36,692 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2025-03-17 19:58:36,792 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2025-03-17 19:58:36,801 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:36,801 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:36,890 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2025-03-17 19:58:36,892 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 14 [2025-03-17 19:58:36,910 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:36,911 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [391537976] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:36,911 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:36,911 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 21 [2025-03-17 19:58:36,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1691099199] [2025-03-17 19:58:36,911 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:36,911 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:36,912 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:36,912 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 6 times [2025-03-17 19:58:36,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:36,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018613414] [2025-03-17 19:58:36,912 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 19:58:36,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:36,915 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:36,916 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:36,916 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 19:58:36,916 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:36,916 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:36,917 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:36,918 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:36,918 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:36,918 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:36,919 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:36,953 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:36,953 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-03-17 19:58:36,953 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=388, Unknown=0, NotChecked=0, Total=462 [2025-03-17 19:58:36,954 INFO L87 Difference]: Start difference. First operand 17 states and 23 transitions. cyclomatic complexity: 9 Second operand has 22 states, 21 states have (on average 1.6666666666666667) internal successors, (35), 22 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:37,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:37,207 INFO L93 Difference]: Finished difference Result 38 states and 51 transitions. [2025-03-17 19:58:37,207 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 51 transitions. [2025-03-17 19:58:37,207 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2025-03-17 19:58:37,208 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 37 states and 50 transitions. [2025-03-17 19:58:37,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2025-03-17 19:58:37,208 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2025-03-17 19:58:37,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37 states and 50 transitions. [2025-03-17 19:58:37,208 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:37,208 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37 states and 50 transitions. [2025-03-17 19:58:37,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states and 50 transitions. [2025-03-17 19:58:37,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 24. [2025-03-17 19:58:37,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.375) internal successors, (33), 23 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:37,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 33 transitions. [2025-03-17 19:58:37,209 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 33 transitions. [2025-03-17 19:58:37,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2025-03-17 19:58:37,210 INFO L432 stractBuchiCegarLoop]: Abstraction has 24 states and 33 transitions. [2025-03-17 19:58:37,210 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-17 19:58:37,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 33 transitions. [2025-03-17 19:58:37,211 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:37,211 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:37,211 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:37,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:37,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:37,211 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:37,211 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:37,212 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:37,212 INFO L85 PathProgramCache]: Analyzing trace with hash 510796067, now seen corresponding path program 3 times [2025-03-17 19:58:37,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:37,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917136363] [2025-03-17 19:58:37,212 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 19:58:37,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:37,216 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 17 statements into 3 equivalence classes. [2025-03-17 19:58:37,222 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 17 of 17 statements. [2025-03-17 19:58:37,223 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-03-17 19:58:37,223 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:37,278 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:37,279 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:37,279 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917136363] [2025-03-17 19:58:37,279 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917136363] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:37,279 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1783298662] [2025-03-17 19:58:37,279 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 19:58:37,279 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:37,279 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:37,281 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:37,283 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2025-03-17 19:58:37,312 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 17 statements into 3 equivalence classes. [2025-03-17 19:58:37,322 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 17 of 17 statements. [2025-03-17 19:58:37,323 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-03-17 19:58:37,323 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:37,323 INFO L256 TraceCheckSpWp]: Trace formula consists of 93 conjuncts, 8 conjuncts are in the unsatisfiable core [2025-03-17 19:58:37,324 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:37,368 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:37,368 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:37,401 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:37,401 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1783298662] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:37,401 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:37,401 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 13 [2025-03-17 19:58:37,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732055419] [2025-03-17 19:58:37,401 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:37,401 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:37,402 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:37,402 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 7 times [2025-03-17 19:58:37,402 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:37,402 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [377880995] [2025-03-17 19:58:37,402 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 19:58:37,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:37,403 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:37,404 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:37,404 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:37,404 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:37,404 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:37,405 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:37,406 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:37,406 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:37,406 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:37,407 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:37,439 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:37,440 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-17 19:58:37,440 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=113, Unknown=0, NotChecked=0, Total=156 [2025-03-17 19:58:37,440 INFO L87 Difference]: Start difference. First operand 24 states and 33 transitions. cyclomatic complexity: 13 Second operand has 13 states, 13 states have (on average 2.3076923076923075) internal successors, (30), 13 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:37,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:37,484 INFO L93 Difference]: Finished difference Result 34 states and 44 transitions. [2025-03-17 19:58:37,484 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 44 transitions. [2025-03-17 19:58:37,484 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:37,485 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 29 states and 39 transitions. [2025-03-17 19:58:37,485 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2025-03-17 19:58:37,485 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2025-03-17 19:58:37,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 39 transitions. [2025-03-17 19:58:37,485 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:37,485 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29 states and 39 transitions. [2025-03-17 19:58:37,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 39 transitions. [2025-03-17 19:58:37,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 26. [2025-03-17 19:58:37,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.3461538461538463) internal successors, (35), 25 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:37,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 35 transitions. [2025-03-17 19:58:37,486 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26 states and 35 transitions. [2025-03-17 19:58:37,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-17 19:58:37,489 INFO L432 stractBuchiCegarLoop]: Abstraction has 26 states and 35 transitions. [2025-03-17 19:58:37,489 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-17 19:58:37,489 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 35 transitions. [2025-03-17 19:58:37,489 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:37,489 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:37,489 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:37,490 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:37,490 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:37,490 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:37,490 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:37,490 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:37,490 INFO L85 PathProgramCache]: Analyzing trace with hash -185875495, now seen corresponding path program 1 times [2025-03-17 19:58:37,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:37,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349129544] [2025-03-17 19:58:37,490 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:37,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:37,496 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 18 statements into 1 equivalence classes. [2025-03-17 19:58:37,509 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 18 of 18 statements. [2025-03-17 19:58:37,509 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:37,509 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:37,753 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:37,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:37,754 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [349129544] [2025-03-17 19:58:37,754 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [349129544] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:37,754 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1560686822] [2025-03-17 19:58:37,754 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:37,754 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:37,754 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:37,756 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:37,757 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2025-03-17 19:58:37,788 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 18 statements into 1 equivalence classes. [2025-03-17 19:58:37,799 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 18 of 18 statements. [2025-03-17 19:58:37,799 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:37,799 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:37,800 INFO L256 TraceCheckSpWp]: Trace formula consists of 103 conjuncts, 22 conjuncts are in the unsatisfiable core [2025-03-17 19:58:37,801 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:37,811 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 1 [2025-03-17 19:58:37,861 INFO L349 Elim1Store]: treesize reduction 27, result has 25.0 percent of original size [2025-03-17 19:58:37,862 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 15 [2025-03-17 19:58:37,876 INFO L349 Elim1Store]: treesize reduction 27, result has 25.0 percent of original size [2025-03-17 19:58:37,876 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 15 [2025-03-17 19:58:37,906 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 9 [2025-03-17 19:58:37,913 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:37,913 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:38,031 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2025-03-17 19:58:38,034 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 14 [2025-03-17 19:58:38,039 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:38,039 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1560686822] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:38,039 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:38,039 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 16 [2025-03-17 19:58:38,039 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264001629] [2025-03-17 19:58:38,039 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:38,040 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:38,040 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:38,040 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 8 times [2025-03-17 19:58:38,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:38,040 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1674692684] [2025-03-17 19:58:38,040 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 19:58:38,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:38,041 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:38,043 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:38,043 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 19:58:38,043 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:38,043 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:38,043 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:38,044 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:38,044 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:38,044 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:38,049 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:38,085 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:38,085 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2025-03-17 19:58:38,086 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=222, Unknown=0, NotChecked=0, Total=272 [2025-03-17 19:58:38,086 INFO L87 Difference]: Start difference. First operand 26 states and 35 transitions. cyclomatic complexity: 13 Second operand has 17 states, 16 states have (on average 1.9375) internal successors, (31), 17 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:38,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:38,194 INFO L93 Difference]: Finished difference Result 30 states and 39 transitions. [2025-03-17 19:58:38,194 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 39 transitions. [2025-03-17 19:58:38,195 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:38,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 29 states and 38 transitions. [2025-03-17 19:58:38,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2025-03-17 19:58:38,195 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2025-03-17 19:58:38,195 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 38 transitions. [2025-03-17 19:58:38,195 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:38,195 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29 states and 38 transitions. [2025-03-17 19:58:38,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 38 transitions. [2025-03-17 19:58:38,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 22. [2025-03-17 19:58:38,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.3181818181818181) internal successors, (29), 21 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:38,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 29 transitions. [2025-03-17 19:58:38,196 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22 states and 29 transitions. [2025-03-17 19:58:38,199 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2025-03-17 19:58:38,200 INFO L432 stractBuchiCegarLoop]: Abstraction has 22 states and 29 transitions. [2025-03-17 19:58:38,200 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-17 19:58:38,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 29 transitions. [2025-03-17 19:58:38,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:38,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:38,200 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:38,200 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:38,200 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:38,201 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:38,201 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:38,201 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:38,202 INFO L85 PathProgramCache]: Analyzing trace with hash -45179496, now seen corresponding path program 4 times [2025-03-17 19:58:38,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:38,202 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863105508] [2025-03-17 19:58:38,202 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 19:58:38,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:38,210 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 20 statements into 2 equivalence classes. [2025-03-17 19:58:38,219 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 19 of 20 statements. [2025-03-17 19:58:38,219 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-03-17 19:58:38,219 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:38,426 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:38,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:38,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1863105508] [2025-03-17 19:58:38,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1863105508] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:38,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1984707009] [2025-03-17 19:58:38,426 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 19:58:38,426 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:38,427 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:38,430 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:38,431 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2025-03-17 19:58:38,460 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 20 statements into 2 equivalence classes. [2025-03-17 19:58:38,469 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 19 of 20 statements. [2025-03-17 19:58:38,469 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-03-17 19:58:38,469 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:38,469 INFO L256 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 21 conjuncts are in the unsatisfiable core [2025-03-17 19:58:38,470 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:38,492 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 1 [2025-03-17 19:58:38,557 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 9 [2025-03-17 19:58:38,567 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:38,568 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:38,645 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2025-03-17 19:58:38,647 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 14 [2025-03-17 19:58:38,659 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:38,659 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1984707009] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:38,659 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:38,659 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 16 [2025-03-17 19:58:38,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190398931] [2025-03-17 19:58:38,659 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:38,659 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:38,659 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:38,660 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 9 times [2025-03-17 19:58:38,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:38,660 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1373741309] [2025-03-17 19:58:38,660 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 19:58:38,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:38,661 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:38,662 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:38,663 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 19:58:38,663 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:38,663 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:38,663 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:38,664 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:38,664 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:38,664 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:38,665 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:38,698 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:38,699 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2025-03-17 19:58:38,699 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=226, Unknown=0, NotChecked=0, Total=272 [2025-03-17 19:58:38,699 INFO L87 Difference]: Start difference. First operand 22 states and 29 transitions. cyclomatic complexity: 10 Second operand has 17 states, 16 states have (on average 2.0) internal successors, (32), 17 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:38,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:38,846 INFO L93 Difference]: Finished difference Result 39 states and 51 transitions. [2025-03-17 19:58:38,846 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 51 transitions. [2025-03-17 19:58:38,846 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2025-03-17 19:58:38,846 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 38 states and 50 transitions. [2025-03-17 19:58:38,847 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2025-03-17 19:58:38,847 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2025-03-17 19:58:38,847 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 50 transitions. [2025-03-17 19:58:38,847 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:38,847 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38 states and 50 transitions. [2025-03-17 19:58:38,847 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 50 transitions. [2025-03-17 19:58:38,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 29. [2025-03-17 19:58:38,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.3448275862068966) internal successors, (39), 28 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:38,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 39 transitions. [2025-03-17 19:58:38,848 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29 states and 39 transitions. [2025-03-17 19:58:38,849 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-17 19:58:38,849 INFO L432 stractBuchiCegarLoop]: Abstraction has 29 states and 39 transitions. [2025-03-17 19:58:38,849 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-17 19:58:38,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 39 transitions. [2025-03-17 19:58:38,850 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:38,850 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:38,850 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:38,850 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:38,850 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:38,850 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:38,850 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:38,850 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:38,851 INFO L85 PathProgramCache]: Analyzing trace with hash -467823466, now seen corresponding path program 5 times [2025-03-17 19:58:38,851 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:38,851 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1262205390] [2025-03-17 19:58:38,851 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 19:58:38,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:38,854 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 22 statements into 4 equivalence classes. [2025-03-17 19:58:38,860 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 22 of 22 statements. [2025-03-17 19:58:38,860 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-03-17 19:58:38,861 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:38,931 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 9 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:38,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:38,931 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1262205390] [2025-03-17 19:58:38,931 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1262205390] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:38,931 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2056378949] [2025-03-17 19:58:38,931 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 19:58:38,931 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:38,931 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:38,933 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:38,935 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2025-03-17 19:58:38,964 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 22 statements into 4 equivalence classes. [2025-03-17 19:58:38,982 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 22 of 22 statements. [2025-03-17 19:58:38,982 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-03-17 19:58:38,982 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:38,983 INFO L256 TraceCheckSpWp]: Trace formula consists of 120 conjuncts, 10 conjuncts are in the unsatisfiable core [2025-03-17 19:58:38,983 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:39,044 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:39,044 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:39,098 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 9 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:39,099 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2056378949] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:39,099 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:39,099 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 15 [2025-03-17 19:58:39,099 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274491777] [2025-03-17 19:58:39,099 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:39,099 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:39,099 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:39,099 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 10 times [2025-03-17 19:58:39,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:39,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061194568] [2025-03-17 19:58:39,099 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 19:58:39,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:39,100 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-17 19:58:39,102 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:39,102 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 19:58:39,102 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:39,102 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:39,102 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:39,103 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:39,103 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:39,103 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:39,104 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:39,137 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:39,137 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2025-03-17 19:58:39,137 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=151, Unknown=0, NotChecked=0, Total=210 [2025-03-17 19:58:39,138 INFO L87 Difference]: Start difference. First operand 29 states and 39 transitions. cyclomatic complexity: 14 Second operand has 15 states, 15 states have (on average 1.9333333333333333) internal successors, (29), 15 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:39,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:39,216 INFO L93 Difference]: Finished difference Result 71 states and 92 transitions. [2025-03-17 19:58:39,216 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 92 transitions. [2025-03-17 19:58:39,218 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2025-03-17 19:58:39,218 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 63 states and 82 transitions. [2025-03-17 19:58:39,218 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2025-03-17 19:58:39,218 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26 [2025-03-17 19:58:39,218 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63 states and 82 transitions. [2025-03-17 19:58:39,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:39,218 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63 states and 82 transitions. [2025-03-17 19:58:39,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states and 82 transitions. [2025-03-17 19:58:39,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 57. [2025-03-17 19:58:39,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.3157894736842106) internal successors, (75), 56 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:39,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 75 transitions. [2025-03-17 19:58:39,224 INFO L240 hiAutomatonCegarLoop]: Abstraction has 57 states and 75 transitions. [2025-03-17 19:58:39,224 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-17 19:58:39,224 INFO L432 stractBuchiCegarLoop]: Abstraction has 57 states and 75 transitions. [2025-03-17 19:58:39,224 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-17 19:58:39,224 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 75 transitions. [2025-03-17 19:58:39,225 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2025-03-17 19:58:39,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:39,226 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:39,226 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:39,227 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2025-03-17 19:58:39,227 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume main_~length~0#1 < 1;main_~length~0#1 := 1;" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:39,227 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:39,227 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:39,227 INFO L85 PathProgramCache]: Analyzing trace with hash 167575460, now seen corresponding path program 1 times [2025-03-17 19:58:39,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:39,227 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112552004] [2025-03-17 19:58:39,227 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:39,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:39,233 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-17 19:58:39,238 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-17 19:58:39,238 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:39,238 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:39,269 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2025-03-17 19:58:39,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:39,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2112552004] [2025-03-17 19:58:39,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2112552004] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:39,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [597624022] [2025-03-17 19:58:39,270 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:39,270 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:39,270 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:39,272 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:39,273 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2025-03-17 19:58:39,305 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-03-17 19:58:39,316 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-03-17 19:58:39,316 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:39,316 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:39,317 INFO L256 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-03-17 19:58:39,317 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:39,341 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2025-03-17 19:58:39,341 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-03-17 19:58:39,341 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [597624022] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-17 19:58:39,341 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-03-17 19:58:39,341 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [5] total 7 [2025-03-17 19:58:39,341 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97263092] [2025-03-17 19:58:39,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-17 19:58:39,343 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:39,343 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:39,343 INFO L85 PathProgramCache]: Analyzing trace with hash 1107262, now seen corresponding path program 1 times [2025-03-17 19:58:39,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:39,344 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588465711] [2025-03-17 19:58:39,344 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-17 19:58:39,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:39,345 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-03-17 19:58:39,347 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-03-17 19:58:39,348 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:39,348 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:39,348 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:39,349 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-03-17 19:58:39,350 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-03-17 19:58:39,350 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:39,350 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:39,351 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:39,416 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:39,416 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-17 19:58:39,416 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2025-03-17 19:58:39,416 INFO L87 Difference]: Start difference. First operand 57 states and 75 transitions. cyclomatic complexity: 25 Second operand has 5 states, 5 states have (on average 3.0) internal successors, (15), 5 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:39,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:39,431 INFO L93 Difference]: Finished difference Result 37 states and 47 transitions. [2025-03-17 19:58:39,431 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37 states and 47 transitions. [2025-03-17 19:58:39,431 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:39,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37 states to 31 states and 40 transitions. [2025-03-17 19:58:39,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2025-03-17 19:58:39,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2025-03-17 19:58:39,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31 states and 40 transitions. [2025-03-17 19:58:39,432 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:39,432 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31 states and 40 transitions. [2025-03-17 19:58:39,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states and 40 transitions. [2025-03-17 19:58:39,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 31. [2025-03-17 19:58:39,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.2903225806451613) internal successors, (40), 30 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:39,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 40 transitions. [2025-03-17 19:58:39,433 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31 states and 40 transitions. [2025-03-17 19:58:39,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-17 19:58:39,437 INFO L432 stractBuchiCegarLoop]: Abstraction has 31 states and 40 transitions. [2025-03-17 19:58:39,437 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-17 19:58:39,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 40 transitions. [2025-03-17 19:58:39,437 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:39,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:39,437 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:39,437 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:39,437 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:39,437 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:39,437 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:39,438 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:39,438 INFO L85 PathProgramCache]: Analyzing trace with hash 88171010, now seen corresponding path program 2 times [2025-03-17 19:58:39,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:39,438 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339463524] [2025-03-17 19:58:39,438 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 19:58:39,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:39,444 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 23 statements into 2 equivalence classes. [2025-03-17 19:58:39,458 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 23 of 23 statements. [2025-03-17 19:58:39,459 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-17 19:58:39,459 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:39,755 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:39,756 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:39,756 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339463524] [2025-03-17 19:58:39,756 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1339463524] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:39,756 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [877045331] [2025-03-17 19:58:39,756 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 19:58:39,756 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:39,756 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:39,758 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:39,760 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2025-03-17 19:58:39,794 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 23 statements into 2 equivalence classes. [2025-03-17 19:58:39,808 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 23 of 23 statements. [2025-03-17 19:58:39,808 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-17 19:58:39,808 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:39,809 INFO L256 TraceCheckSpWp]: Trace formula consists of 130 conjuncts, 30 conjuncts are in the unsatisfiable core [2025-03-17 19:58:39,810 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:39,871 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2025-03-17 19:58:39,937 INFO L190 IndexEqualityManager]: detected not equals via solver [2025-03-17 19:58:39,937 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 13 [2025-03-17 19:58:39,946 INFO L190 IndexEqualityManager]: detected not equals via solver [2025-03-17 19:58:39,947 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 13 [2025-03-17 19:58:40,047 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2025-03-17 19:58:40,057 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:40,058 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:40,165 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 20 [2025-03-17 19:58:40,168 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2025-03-17 19:58:40,177 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:40,177 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [877045331] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:40,177 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:40,177 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 12] total 26 [2025-03-17 19:58:40,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [983436141] [2025-03-17 19:58:40,177 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:40,177 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:40,178 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:40,178 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 11 times [2025-03-17 19:58:40,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:40,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996886099] [2025-03-17 19:58:40,178 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 19:58:40,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:40,180 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:40,180 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:40,180 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 19:58:40,181 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:40,181 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:40,181 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:40,182 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:40,182 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:40,182 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:40,183 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:40,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:40,234 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2025-03-17 19:58:40,234 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=600, Unknown=0, NotChecked=0, Total=702 [2025-03-17 19:58:40,234 INFO L87 Difference]: Start difference. First operand 31 states and 40 transitions. cyclomatic complexity: 13 Second operand has 27 states, 26 states have (on average 1.8846153846153846) internal successors, (49), 27 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:40,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:40,395 INFO L93 Difference]: Finished difference Result 37 states and 46 transitions. [2025-03-17 19:58:40,395 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37 states and 46 transitions. [2025-03-17 19:58:40,395 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:40,396 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37 states to 36 states and 45 transitions. [2025-03-17 19:58:40,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2025-03-17 19:58:40,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2025-03-17 19:58:40,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 45 transitions. [2025-03-17 19:58:40,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:40,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36 states and 45 transitions. [2025-03-17 19:58:40,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states and 45 transitions. [2025-03-17 19:58:40,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 27. [2025-03-17 19:58:40,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2592592592592593) internal successors, (34), 26 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:40,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 34 transitions. [2025-03-17 19:58:40,398 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 34 transitions. [2025-03-17 19:58:40,399 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2025-03-17 19:58:40,399 INFO L432 stractBuchiCegarLoop]: Abstraction has 27 states and 34 transitions. [2025-03-17 19:58:40,399 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-17 19:58:40,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 34 transitions. [2025-03-17 19:58:40,400 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:40,400 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:40,400 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:40,400 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 4, 3, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:40,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:40,400 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:40,400 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:40,401 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:40,401 INFO L85 PathProgramCache]: Analyzing trace with hash 1331009857, now seen corresponding path program 6 times [2025-03-17 19:58:40,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:40,402 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534795465] [2025-03-17 19:58:40,402 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 19:58:40,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:40,406 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 25 statements into 5 equivalence classes. [2025-03-17 19:58:40,440 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) and asserted 25 of 25 statements. [2025-03-17 19:58:40,443 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2025-03-17 19:58:40,444 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:40,753 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:40,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:40,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534795465] [2025-03-17 19:58:40,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534795465] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:40,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [596527862] [2025-03-17 19:58:40,753 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 19:58:40,753 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:40,753 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:40,755 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:40,757 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2025-03-17 19:58:40,794 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 25 statements into 5 equivalence classes. [2025-03-17 19:58:40,811 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) and asserted 25 of 25 statements. [2025-03-17 19:58:40,811 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2025-03-17 19:58:40,811 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:40,812 INFO L256 TraceCheckSpWp]: Trace formula consists of 135 conjuncts, 29 conjuncts are in the unsatisfiable core [2025-03-17 19:58:40,814 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:40,893 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2025-03-17 19:58:41,043 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2025-03-17 19:58:41,054 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:41,054 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:41,197 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2025-03-17 19:58:41,199 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 14 [2025-03-17 19:58:41,251 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:41,251 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [596527862] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:41,251 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:41,251 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 12] total 33 [2025-03-17 19:58:41,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1724340588] [2025-03-17 19:58:41,251 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:41,251 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:41,251 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:41,251 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 12 times [2025-03-17 19:58:41,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:41,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927950520] [2025-03-17 19:58:41,251 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-17 19:58:41,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:41,253 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:41,254 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:41,254 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-17 19:58:41,254 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:41,254 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:41,254 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:41,255 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:41,255 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:41,255 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:41,256 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:41,290 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:41,290 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2025-03-17 19:58:41,291 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=986, Unknown=0, NotChecked=0, Total=1122 [2025-03-17 19:58:41,291 INFO L87 Difference]: Start difference. First operand 27 states and 34 transitions. cyclomatic complexity: 10 Second operand has 34 states, 33 states have (on average 1.9696969696969697) internal successors, (65), 34 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:41,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:41,901 INFO L93 Difference]: Finished difference Result 62 states and 76 transitions. [2025-03-17 19:58:41,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 76 transitions. [2025-03-17 19:58:41,901 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2025-03-17 19:58:41,902 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 49 states and 62 transitions. [2025-03-17 19:58:41,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2025-03-17 19:58:41,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2025-03-17 19:58:41,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49 states and 62 transitions. [2025-03-17 19:58:41,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:41,904 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49 states and 62 transitions. [2025-03-17 19:58:41,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states and 62 transitions. [2025-03-17 19:58:41,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 36. [2025-03-17 19:58:41,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.2777777777777777) internal successors, (46), 35 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:41,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 46 transitions. [2025-03-17 19:58:41,905 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 46 transitions. [2025-03-17 19:58:41,908 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2025-03-17 19:58:41,908 INFO L432 stractBuchiCegarLoop]: Abstraction has 36 states and 46 transitions. [2025-03-17 19:58:41,908 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-17 19:58:41,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 46 transitions. [2025-03-17 19:58:41,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:41,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:41,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:41,909 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:41,909 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:41,909 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:41,909 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:41,909 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:41,910 INFO L85 PathProgramCache]: Analyzing trace with hash -430432779, now seen corresponding path program 3 times [2025-03-17 19:58:41,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:41,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451705692] [2025-03-17 19:58:41,910 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 19:58:41,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:41,915 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 28 statements into 6 equivalence classes. [2025-03-17 19:58:41,935 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 28 of 28 statements. [2025-03-17 19:58:41,935 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-03-17 19:58:41,935 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:42,251 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:42,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:42,251 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [451705692] [2025-03-17 19:58:42,251 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [451705692] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:42,251 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [798636960] [2025-03-17 19:58:42,251 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 19:58:42,252 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:42,253 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:42,255 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:42,257 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2025-03-17 19:58:42,295 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 28 statements into 6 equivalence classes. [2025-03-17 19:58:42,322 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 28 of 28 statements. [2025-03-17 19:58:42,322 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-03-17 19:58:42,322 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:42,323 INFO L256 TraceCheckSpWp]: Trace formula consists of 157 conjuncts, 30 conjuncts are in the unsatisfiable core [2025-03-17 19:58:42,325 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:42,349 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 1 [2025-03-17 19:58:42,384 INFO L349 Elim1Store]: treesize reduction 27, result has 25.0 percent of original size [2025-03-17 19:58:42,385 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 15 [2025-03-17 19:58:42,396 INFO L349 Elim1Store]: treesize reduction 27, result has 25.0 percent of original size [2025-03-17 19:58:42,396 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 15 [2025-03-17 19:58:42,466 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 9 [2025-03-17 19:58:42,468 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:42,468 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:42,602 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2025-03-17 19:58:42,603 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 14 [2025-03-17 19:58:42,614 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:42,614 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [798636960] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:42,614 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:42,614 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 21 [2025-03-17 19:58:42,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184162691] [2025-03-17 19:58:42,614 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:42,614 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:42,614 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:42,614 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 13 times [2025-03-17 19:58:42,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:42,614 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1958966343] [2025-03-17 19:58:42,614 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 19:58:42,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:42,616 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:42,617 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:42,617 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:42,617 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:42,617 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:42,617 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:42,618 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:42,618 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:42,618 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:42,619 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:42,650 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:42,651 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-03-17 19:58:42,651 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=400, Unknown=0, NotChecked=0, Total=462 [2025-03-17 19:58:42,651 INFO L87 Difference]: Start difference. First operand 36 states and 46 transitions. cyclomatic complexity: 14 Second operand has 22 states, 21 states have (on average 2.0476190476190474) internal successors, (43), 22 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:42,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:42,849 INFO L93 Difference]: Finished difference Result 44 states and 54 transitions. [2025-03-17 19:58:42,849 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 54 transitions. [2025-03-17 19:58:42,849 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:42,850 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 43 states and 53 transitions. [2025-03-17 19:58:42,850 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2025-03-17 19:58:42,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2025-03-17 19:58:42,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 53 transitions. [2025-03-17 19:58:42,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:42,850 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43 states and 53 transitions. [2025-03-17 19:58:42,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 53 transitions. [2025-03-17 19:58:42,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 32. [2025-03-17 19:58:42,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.25) internal successors, (40), 31 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:42,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 40 transitions. [2025-03-17 19:58:42,851 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32 states and 40 transitions. [2025-03-17 19:58:42,855 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-17 19:58:42,856 INFO L432 stractBuchiCegarLoop]: Abstraction has 32 states and 40 transitions. [2025-03-17 19:58:42,856 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-17 19:58:42,856 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 40 transitions. [2025-03-17 19:58:42,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:42,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:42,856 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:42,856 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:42,856 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:42,856 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:42,856 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:42,858 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:42,858 INFO L85 PathProgramCache]: Analyzing trace with hash -1622443980, now seen corresponding path program 7 times [2025-03-17 19:58:42,858 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:42,858 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15921242] [2025-03-17 19:58:42,858 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 19:58:42,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:42,863 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-17 19:58:42,875 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-17 19:58:42,875 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:42,875 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:43,174 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:43,174 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:43,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [15921242] [2025-03-17 19:58:43,174 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [15921242] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:43,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1979329282] [2025-03-17 19:58:43,175 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-17 19:58:43,175 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:43,175 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:43,177 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:43,178 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2025-03-17 19:58:43,216 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-17 19:58:43,230 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-17 19:58:43,230 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:43,230 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:43,231 INFO L256 TraceCheckSpWp]: Trace formula consists of 162 conjuncts, 29 conjuncts are in the unsatisfiable core [2025-03-17 19:58:43,232 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:43,247 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 1 [2025-03-17 19:58:43,347 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 9 [2025-03-17 19:58:43,358 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:43,358 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:43,459 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2025-03-17 19:58:43,461 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 14 [2025-03-17 19:58:43,471 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:43,472 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1979329282] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:43,472 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:43,472 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 14] total 22 [2025-03-17 19:58:43,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1689969132] [2025-03-17 19:58:43,472 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:43,472 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:43,472 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:43,472 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 14 times [2025-03-17 19:58:43,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:43,472 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086088258] [2025-03-17 19:58:43,472 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 19:58:43,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:43,477 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:43,478 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:43,478 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 19:58:43,478 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:43,478 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:43,478 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:43,479 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:43,479 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:43,479 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:43,480 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:43,510 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:43,510 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2025-03-17 19:58:43,511 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=442, Unknown=0, NotChecked=0, Total=506 [2025-03-17 19:58:43,511 INFO L87 Difference]: Start difference. First operand 32 states and 40 transitions. cyclomatic complexity: 11 Second operand has 23 states, 22 states have (on average 2.090909090909091) internal successors, (46), 23 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:43,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:43,743 INFO L93 Difference]: Finished difference Result 53 states and 66 transitions. [2025-03-17 19:58:43,743 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 66 transitions. [2025-03-17 19:58:43,743 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2025-03-17 19:58:43,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 52 states and 65 transitions. [2025-03-17 19:58:43,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2025-03-17 19:58:43,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2025-03-17 19:58:43,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 65 transitions. [2025-03-17 19:58:43,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:43,744 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52 states and 65 transitions. [2025-03-17 19:58:43,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 65 transitions. [2025-03-17 19:58:43,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 39. [2025-03-17 19:58:43,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.2820512820512822) internal successors, (50), 38 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:43,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 50 transitions. [2025-03-17 19:58:43,745 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39 states and 50 transitions. [2025-03-17 19:58:43,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2025-03-17 19:58:43,747 INFO L432 stractBuchiCegarLoop]: Abstraction has 39 states and 50 transitions. [2025-03-17 19:58:43,747 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-17 19:58:43,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 50 transitions. [2025-03-17 19:58:43,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:43,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:43,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:43,747 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:43,747 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:43,747 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:43,747 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:43,748 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:43,748 INFO L85 PathProgramCache]: Analyzing trace with hash -95537102, now seen corresponding path program 8 times [2025-03-17 19:58:43,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:43,748 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2103845986] [2025-03-17 19:58:43,748 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 19:58:43,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:43,752 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 32 statements into 2 equivalence classes. [2025-03-17 19:58:43,757 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 32 of 32 statements. [2025-03-17 19:58:43,757 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-17 19:58:43,757 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:43,871 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 21 proven. 44 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:43,872 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:43,872 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2103845986] [2025-03-17 19:58:43,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2103845986] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:43,872 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [3126268] [2025-03-17 19:58:43,872 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-17 19:58:43,872 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:43,872 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:43,874 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:43,876 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2025-03-17 19:58:43,913 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 32 statements into 2 equivalence classes. [2025-03-17 19:58:43,930 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 32 of 32 statements. [2025-03-17 19:58:43,930 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-17 19:58:43,930 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:43,931 INFO L256 TraceCheckSpWp]: Trace formula consists of 174 conjuncts, 14 conjuncts are in the unsatisfiable core [2025-03-17 19:58:43,932 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:44,038 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:44,038 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:44,121 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:44,121 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [3126268] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:44,121 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:44,121 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 22 [2025-03-17 19:58:44,121 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275719804] [2025-03-17 19:58:44,121 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:44,122 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:44,122 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:44,122 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 15 times [2025-03-17 19:58:44,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:44,122 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834931282] [2025-03-17 19:58:44,122 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 19:58:44,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:44,124 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:44,124 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:44,124 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-17 19:58:44,124 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:44,125 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:44,125 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:44,126 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:44,126 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:44,126 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:44,127 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:44,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:44,159 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-03-17 19:58:44,159 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=347, Unknown=0, NotChecked=0, Total=462 [2025-03-17 19:58:44,160 INFO L87 Difference]: Start difference. First operand 39 states and 50 transitions. cyclomatic complexity: 15 Second operand has 22 states, 22 states have (on average 2.3181818181818183) internal successors, (51), 22 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:44,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:44,242 INFO L93 Difference]: Finished difference Result 55 states and 67 transitions. [2025-03-17 19:58:44,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 67 transitions. [2025-03-17 19:58:44,243 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:44,243 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 44 states and 56 transitions. [2025-03-17 19:58:44,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2025-03-17 19:58:44,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2025-03-17 19:58:44,243 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 56 transitions. [2025-03-17 19:58:44,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:44,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44 states and 56 transitions. [2025-03-17 19:58:44,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 56 transitions. [2025-03-17 19:58:44,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 41. [2025-03-17 19:58:44,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.2682926829268293) internal successors, (52), 40 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:44,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 52 transitions. [2025-03-17 19:58:44,244 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41 states and 52 transitions. [2025-03-17 19:58:44,245 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2025-03-17 19:58:44,245 INFO L432 stractBuchiCegarLoop]: Abstraction has 41 states and 52 transitions. [2025-03-17 19:58:44,245 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-17 19:58:44,245 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 52 transitions. [2025-03-17 19:58:44,245 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:44,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:44,246 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:44,246 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:44,246 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:44,246 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:44,246 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:44,246 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:44,246 INFO L85 PathProgramCache]: Analyzing trace with hash 2138217310, now seen corresponding path program 4 times [2025-03-17 19:58:44,246 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:44,247 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2146803558] [2025-03-17 19:58:44,247 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 19:58:44,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:44,251 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 33 statements into 2 equivalence classes. [2025-03-17 19:58:44,270 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 32 of 33 statements. [2025-03-17 19:58:44,270 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-03-17 19:58:44,270 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:44,701 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:44,702 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:44,702 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2146803558] [2025-03-17 19:58:44,702 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2146803558] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:44,702 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [482361066] [2025-03-17 19:58:44,702 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 19:58:44,702 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:44,702 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:44,704 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:44,705 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2025-03-17 19:58:44,747 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 33 statements into 2 equivalence classes. [2025-03-17 19:58:44,762 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 32 of 33 statements. [2025-03-17 19:58:44,762 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-03-17 19:58:44,762 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:44,763 INFO L256 TraceCheckSpWp]: Trace formula consists of 168 conjuncts, 34 conjuncts are in the unsatisfiable core [2025-03-17 19:58:44,765 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:44,781 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 1 [2025-03-17 19:58:44,822 INFO L349 Elim1Store]: treesize reduction 27, result has 25.0 percent of original size [2025-03-17 19:58:44,822 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 15 [2025-03-17 19:58:44,833 INFO L349 Elim1Store]: treesize reduction 27, result has 25.0 percent of original size [2025-03-17 19:58:44,833 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 15 [2025-03-17 19:58:44,923 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 9 [2025-03-17 19:58:44,933 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:44,933 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:45,089 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 20 [2025-03-17 19:58:45,092 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 14 [2025-03-17 19:58:45,102 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:45,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [482361066] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:45,102 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:45,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2025-03-17 19:58:45,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872331962] [2025-03-17 19:58:45,102 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:45,103 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:45,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:45,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 16 times [2025-03-17 19:58:45,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:45,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [777319745] [2025-03-17 19:58:45,103 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-17 19:58:45,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:45,104 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-17 19:58:45,105 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:45,106 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-17 19:58:45,106 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:45,106 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:45,106 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:45,106 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:45,107 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:45,107 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:45,107 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:45,139 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:45,139 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2025-03-17 19:58:45,139 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=576, Unknown=0, NotChecked=0, Total=650 [2025-03-17 19:58:45,139 INFO L87 Difference]: Start difference. First operand 41 states and 52 transitions. cyclomatic complexity: 15 Second operand has 26 states, 25 states have (on average 2.08) internal successors, (52), 26 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:45,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:45,349 INFO L93 Difference]: Finished difference Result 51 states and 62 transitions. [2025-03-17 19:58:45,349 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 62 transitions. [2025-03-17 19:58:45,350 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:45,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 50 states and 61 transitions. [2025-03-17 19:58:45,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2025-03-17 19:58:45,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2025-03-17 19:58:45,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50 states and 61 transitions. [2025-03-17 19:58:45,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-17 19:58:45,350 INFO L218 hiAutomatonCegarLoop]: Abstraction has 50 states and 61 transitions. [2025-03-17 19:58:45,350 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states and 61 transitions. [2025-03-17 19:58:45,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 37. [2025-03-17 19:58:45,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 36 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:45,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 46 transitions. [2025-03-17 19:58:45,352 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37 states and 46 transitions. [2025-03-17 19:58:45,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2025-03-17 19:58:45,352 INFO L432 stractBuchiCegarLoop]: Abstraction has 37 states and 46 transitions. [2025-03-17 19:58:45,352 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-17 19:58:45,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 46 transitions. [2025-03-17 19:58:45,352 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-17 19:58:45,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-17 19:58:45,353 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-17 19:58:45,353 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1] [2025-03-17 19:58:45,353 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-17 19:58:45,353 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-17 19:58:45,353 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-17 19:58:45,353 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:45,353 INFO L85 PathProgramCache]: Analyzing trace with hash -954948835, now seen corresponding path program 9 times [2025-03-17 19:58:45,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:45,354 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1567020226] [2025-03-17 19:58:45,354 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 19:58:45,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:45,359 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 35 statements into 7 equivalence classes. [2025-03-17 19:58:45,373 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) and asserted 35 of 35 statements. [2025-03-17 19:58:45,374 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2025-03-17 19:58:45,374 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:45,780 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 12 proven. 69 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:45,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-17 19:58:45,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1567020226] [2025-03-17 19:58:45,781 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1567020226] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-17 19:58:45,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2119226082] [2025-03-17 19:58:45,781 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-17 19:58:45,781 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-17 19:58:45,781 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-17 19:58:45,783 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-17 19:58:45,785 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2025-03-17 19:58:45,827 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 35 statements into 7 equivalence classes. [2025-03-17 19:58:45,859 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) and asserted 35 of 35 statements. [2025-03-17 19:58:45,859 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2025-03-17 19:58:45,859 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-17 19:58:45,861 INFO L256 TraceCheckSpWp]: Trace formula consists of 189 conjuncts, 24 conjuncts are in the unsatisfiable core [2025-03-17 19:58:45,862 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-17 19:58:45,891 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 1 [2025-03-17 19:58:46,181 INFO L349 Elim1Store]: treesize reduction 5, result has 37.5 percent of original size [2025-03-17 19:58:46,182 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 12 [2025-03-17 19:58:46,193 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 25 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:46,194 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-17 19:58:46,530 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 20 [2025-03-17 19:58:46,532 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 14 [2025-03-17 19:58:46,574 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 20 proven. 61 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-17 19:58:46,574 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2119226082] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-17 19:58:46,574 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-17 19:58:46,574 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 33 [2025-03-17 19:58:46,574 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753767940] [2025-03-17 19:58:46,574 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-17 19:58:46,575 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-17 19:58:46,575 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-17 19:58:46,575 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 17 times [2025-03-17 19:58:46,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-17 19:58:46,575 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414694585] [2025-03-17 19:58:46,575 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-17 19:58:46,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-17 19:58:46,577 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:46,578 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:46,578 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-17 19:58:46,578 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:46,578 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-17 19:58:46,578 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-17 19:58:46,579 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-17 19:58:46,579 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-17 19:58:46,579 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-17 19:58:46,580 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-17 19:58:46,612 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-17 19:58:46,613 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2025-03-17 19:58:46,613 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=208, Invalid=914, Unknown=0, NotChecked=0, Total=1122 [2025-03-17 19:58:46,613 INFO L87 Difference]: Start difference. First operand 37 states and 46 transitions. cyclomatic complexity: 12 Second operand has 34 states, 33 states have (on average 2.0) internal successors, (66), 34 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-17 19:58:48,366 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.30s for a HTC check with result INVALID. Formula has sorts [Array, Bool, Int], hasArrays=true, hasNonlinArith=false, quantifiers [0, 1] [2025-03-17 19:58:48,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-17 19:58:48,575 INFO L93 Difference]: Finished difference Result 55 states and 65 transitions. [2025-03-17 19:58:48,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 65 transitions. [2025-03-17 19:58:48,576 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2025-03-17 19:58:48,576 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 0 states and 0 transitions. [2025-03-17 19:58:48,576 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 0 [2025-03-17 19:58:48,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 0 [2025-03-17 19:58:48,576 INFO L73 IsDeterministic]: Start isDeterministic. Operand 0 states and 0 transitions. [2025-03-17 19:58:48,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-17 19:58:48,576 INFO L218 hiAutomatonCegarLoop]: Abstraction has 0 states and 0 transitions. [2025-03-17 19:58:48,576 INFO L240 hiAutomatonCegarLoop]: Abstraction has 0 states and 0 transitions. [2025-03-17 19:58:48,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2025-03-17 19:58:48,576 INFO L432 stractBuchiCegarLoop]: Abstraction has 0 states and 0 transitions. [2025-03-17 19:58:48,577 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-17 19:58:48,577 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 0 states and 0 transitions. [2025-03-17 19:58:48,577 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2025-03-17 19:58:48,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is true [2025-03-17 19:58:48,582 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.03 07:58:48 BoogieIcfgContainer [2025-03-17 19:58:48,582 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-17 19:58:48,582 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-17 19:58:48,582 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-17 19:58:48,582 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-17 19:58:48,583 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.03 07:58:32" (3/4) ... [2025-03-17 19:58:48,584 INFO L149 WitnessPrinter]: No result that supports witness generation found [2025-03-17 19:58:48,584 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-17 19:58:48,585 INFO L158 Benchmark]: Toolchain (without parser) took 16877.70ms. Allocated memory was 142.6MB in the beginning and 453.0MB in the end (delta: 310.4MB). Free memory was 104.9MB in the beginning and 223.1MB in the end (delta: -118.1MB). Peak memory consumption was 197.9MB. Max. memory is 16.1GB. [2025-03-17 19:58:48,585 INFO L158 Benchmark]: CDTParser took 0.73ms. Allocated memory is still 201.3MB. Free memory is still 127.6MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-17 19:58:48,585 INFO L158 Benchmark]: CACSL2BoogieTranslator took 289.56ms. Allocated memory is still 142.6MB. Free memory was 103.8MB in the beginning and 86.1MB in the end (delta: 17.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-17 19:58:48,585 INFO L158 Benchmark]: Boogie Procedure Inliner took 27.73ms. Allocated memory is still 142.6MB. Free memory was 86.1MB in the beginning and 84.5MB in the end (delta: 1.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-17 19:58:48,586 INFO L158 Benchmark]: Boogie Preprocessor took 23.68ms. Allocated memory is still 142.6MB. Free memory was 84.5MB in the beginning and 83.4MB in the end (delta: 1.1MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-17 19:58:48,586 INFO L158 Benchmark]: IcfgBuilder took 201.89ms. Allocated memory is still 142.6MB. Free memory was 83.4MB in the beginning and 71.6MB in the end (delta: 11.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-17 19:58:48,586 INFO L158 Benchmark]: BuchiAutomizer took 16328.70ms. Allocated memory was 142.6MB in the beginning and 453.0MB in the end (delta: 310.4MB). Free memory was 71.6MB in the beginning and 223.2MB in the end (delta: -151.6MB). Peak memory consumption was 164.4MB. Max. memory is 16.1GB. [2025-03-17 19:58:48,587 INFO L158 Benchmark]: Witness Printer took 2.28ms. Allocated memory is still 453.0MB. Free memory was 223.2MB in the beginning and 223.1MB in the end (delta: 138.5kB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-17 19:58:48,587 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.73ms. Allocated memory is still 201.3MB. Free memory is still 127.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 289.56ms. Allocated memory is still 142.6MB. Free memory was 103.8MB in the beginning and 86.1MB in the end (delta: 17.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 27.73ms. Allocated memory is still 142.6MB. Free memory was 86.1MB in the beginning and 84.5MB in the end (delta: 1.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 23.68ms. Allocated memory is still 142.6MB. Free memory was 84.5MB in the beginning and 83.4MB in the end (delta: 1.1MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 201.89ms. Allocated memory is still 142.6MB. Free memory was 83.4MB in the beginning and 71.6MB in the end (delta: 11.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 16328.70ms. Allocated memory was 142.6MB in the beginning and 453.0MB in the end (delta: 310.4MB). Free memory was 71.6MB in the beginning and 223.2MB in the end (delta: -151.6MB). Peak memory consumption was 164.4MB. Max. memory is 16.1GB. * Witness Printer took 2.28ms. Allocated memory is still 453.0MB. Free memory was 223.2MB in the beginning and 223.1MB in the end (delta: 138.5kB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Unknown variable: #length - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#length,GLOBAL] - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Unknown variable: ~arr~0!offset * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 19 terminating modules (17 trivial, 2 deterministic, 0 nondeterministic). One deterministic module has affine ranking function null and consists of 3 locations. One deterministic module has affine ranking function (((long) -1 * j) + length) and consists of 3 locations. 17 modules have a trivial ranking function, the largest among these consists of 34 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 16.2s and 20 iterations. TraceHistogramMax:6. Analysis of lassos took 11.5s. Construction of modules took 2.9s. Büchi inclusion checks took 1.7s. Highest rank in rank-based complementation 3. Minimization of det autom 3. Minimization of nondet autom 16. Automata minimization 0.0s AutomataMinimizationTime, 18 MinimizatonAttempts, 118 StatesRemovedByMinimization, 16 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 532 SdHoareTripleChecker+Valid, 3.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 530 mSDsluCounter, 770 SdHoareTripleChecker+Invalid, 2.9s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 631 mSDsCounter, 196 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 3749 IncrementalHoareTripleChecker+Invalid, 3945 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 196 mSolverCounterUnsat, 139 mSDtfsCounter, 3749 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont0 unkn0 SFLI0 SFLT0 conc0 concLT0 SILN0 SILU17 SILI0 SILT0 lasso2 LassoPreprocessingBenchmarks: Lassos: inital105 mio100 ax100 hnf100 lsp100 ukn82 mio100 lsp56 div180 bol100 ite100 ukn100 eq150 hnf94 smp64 dnf100 smp100 tf100 neg100 sie100 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 25ms VariablesStem: 2 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 2 MotzkinApplications: 6 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Termination proven Buchi Automizer proved that your program is terminating RESULT: Ultimate proved your program to be correct! [2025-03-17 19:58:48,599 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Forceful destruction successful, exit code 0 [2025-03-17 19:58:48,799 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Forceful destruction successful, exit code 0 [2025-03-17 19:58:48,999 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Forceful destruction successful, exit code 0 [2025-03-17 19:58:49,199 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Forceful destruction successful, exit code 0 [2025-03-17 19:58:49,400 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Ended with exit code 0 [2025-03-17 19:58:49,600 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Forceful destruction successful, exit code 0 [2025-03-17 19:58:49,800 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2025-03-17 19:58:50,001 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Forceful destruction successful, exit code 0 [2025-03-17 19:58:50,201 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2025-03-17 19:58:50,401 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2025-03-17 19:58:50,602 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2025-03-17 19:58:50,801 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2025-03-17 19:58:51,002 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2025-03-17 19:58:51,201 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2025-03-17 19:58:51,402 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2025-03-17 19:58:51,602 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2025-03-17 19:58:51,807 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Result: TRUE